AD4195-4 AD | Alldatasheet
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24-Bit, 62.5kSPS, Multichannel, Low-Noise Precision Sigma-Delta ADC Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Input referred noise: 10nV at 3.8SPS, Gain = 128 ►Crosspoint multiplexed analog inputs ►4 Differential/8 Pseudodifferential inputs ►Ultra-low noise integrated PGA, gains of 0.5 to 128 ►Output data rate: 3.8SPS to 62.5kSPS ►Flexible digital filters ►Low latency sinc filters ►Simultaneous 50Hz/60Hz rejection ►Band-gap reference with 5ppm/°C drift typical ►Internal oscillator ►Analog power supply: 4.75V to 5.25V or ±2.5V ►Digital power supply: 1.7V to 5.25V ►Matched programmable excitation current sources ►Low-side power switches ►On-chip bias voltage generator ►Internal temperature sensor ►Four general-purpose inputs/outputs ►Internal and system calibration ►Sensor burnout detection ►Diagnostic functions ►Per channel configuration ►Flexible automatic channel sequencer ►3- or 4-wire serial interface (Schmitt trigger on SCLK) ►SPI, QSPI, MICROWIRE, and DSP compatible ►TDM compatible interface for data streaming ►Performance temperature range: −40°C to +105°C ►Functional temperature range: −40°C to +125°C ►Available in 32-lead 4mm x 6mm LFCSP package
APPLICATIONS
►Industrial process control: PLC/DCS modules ►Temperature measurement ►Pressure measurement ►Medical and scientific instrumentation ►Chromatography ►Environmental monitoring ►Electrical test and measurement ►Instrumentation ►Weigh scale FUNCTIONAL BLOCK DIAGRAM Figure 1. AD4195-4 Functional Block Diagram
analog.com Rev. 0 | 2 of 94 General-Purpose Inputs/Outputs (GPIO0 to ADC Conversion Modes and Accessing Reference Overvoltage/Undervoltage Analog Input Overvoltage/Undervoltage
analog.com Rev. 0 | 3 of 94
REVISION HISTORY
1/2025—Revision 0: Initial Version
analog.com Rev. 0 | 4 of 94 The AD4195-4 is a low noise, completely integrated analog front end for high precision measurement applications. The device con- tains a low noise, 24-bit Σ-Δ analog-to-digital converter (ADC) and can be configured to have four differential or eight single-ended or pseudodifferential inputs. The on-chip low-noise gain stage ensures that signals of small amplitude can be interfaced directly to the ADC. The AD4195-4 offers the highest degree of signal chain integration. The device contains an internal reference and accepts two external differential references, which can be internally buffered. Other key integrated features include: ►Programmable gain amplifier (PGA). Due to the programmable gain (0.5 to 128), the PGA allows direct interfacing to transduc- ers with low output amplitudes such as resistive bridges, thermo- couples, and resistance temperature detectors (RTDs). ►The PGA has a wide common-mode input range, which gives designers a greater margin for widely varying input common modes. ►Low drift, well matched precision current sources. Use the excita- tion current sources to excite 2-, 3-, and 4-wire RTDs or bridge type sensors. Excitation current output options include 10μA, 50μA, 100μA, 250μA, 500μA, 1mA, and 1.5mA. The currents can also be added if higher currents are required. ►Use the low-side power switch (PDSW) to power down bridge sensors between conversions. ►Voltage bias for thermocouples (the VBIAS source sets the common-mode voltage of a channel to (AVDD + AVSS)/2. ►The smart sequencer allows the conversion of each enabled preconfigured channel in a predetermined order, which allows a mix of transducer, system checks, and diagnostic measurements to be interleaved. The sequencer eliminates the need for repet- itive serial interface communication with the device to change configuration. Configure the 16-channels in the sequence. Each of these channels selects from eight user-defined ADC setups that allow selection of gain, filter type, output data rate, buffering, and reference source. The AD4195-4 also has extensive diagnostic functionality integrat- ed as part of its comprehensive feature set. These diagnostics include a cyclic redundancy check (CRC), signal chain checks, and serial interface checks, which lead to a more robust solution. The device also offers a multitude of filter options, which ensure that the user has the highest degree of flexibility. The part contains sinc filters, which allow faster settling. In addition, the AD4195-4 offers multiple options for simultaneous 50Hz and 60Hz rejection. The device operates with a single analog power supply from 4.75V to 5.25V or a bipolar 2.5V power supply. The digital supply has a range of 1.7V to 5.25V. It is specified for a temperature range of −40°C to +105°C. The AD4195-4 is housed in a 32-lead LFCSP package.
TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted. Table 1. Specifications
Table 1. Specifications (Continued)
1 Temperature range is −40°C to +105°C. 2 These specifications are not production tested but are supported by characterization data at the initial product release. the gain error to the order of the noise for the programmed ODR. 4 The minimum and maximum voltage on AINP and AINM are AVSS + 0.1V and AVDD − 0.1V. which applies when higher reference voltages are used. 6 This specification includes moisture sensitivity level (MSL) preconditioning effects. 7 This specification is with no load on the REFOUT, excitation currents, and digital output pins. Digital inputs are connected to IOVDD or DGND.
Table 2. Timing Characteristics
TA = 25°C, unless otherwise noted. Table 3. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. Table 4. Thermal Resistance sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 5. AD4195-4, 32-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 9. Pin Configuration Table 6. Pin Function Descriptions pin. A bias voltage midway between the analog power supply rails can be output at this pin. 2 REFIN+ Positive Reference Input. Apply an external reference between REFIN+ and REFIN−. REFIN+ can be anywhere between AVDD and AVSS + 1V. The nominal reference voltage (REFIN+ − REFIN−) is 2.5V, but the device functions with a reference from 1V to AVDD. 3 REFIN- Negative Reference Input. This reference input can be anywhere between AVSS and AVDD – 1V. 4 AVDD Analog Supply Voltage. This is relative to AVSS. +2.5V, respectively, which provides a ±2.5V supply to the ADC. 6 REGCAP_A Analog Low Dropout (LDO) Regulator Output. Decouple this pin to AVSS with a 1µF capacitor in parallel with a 0.1µF capacitor. current sources can also be made available at this pin. conversion sequence begins from the first enabled channel. the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data.
Table 6. Pin Function Descriptions (Continued) the register address selected during the instruction phase. clock. SYNC_OUT is applied to all AD4195-4 ADCs in a multi AD4195-4 system to force all the ADCs to have synchronous conversion behavior. 19 DGND Digital Ground Reference Point. 21 REGCAP_D Digital LDO Regulator Output. Decouple this pin to DGND with a 1µF capacitor in parallel with a 0.1µF capacitor. generates a synchronization signal SYNC_OUT from the applied START signal, SYNC_OUT being synchronized with the internal main clock. SYNC_OUT is applied to all AD4195-4 ADCs in a multi AD4195-4 system to force all the ADCs to have synchronous conversion behavior. AVDD. Any of the internal programmable excitation current sources can also be made available at this pin. AVDD. Any of the internal programmable excitation current sources can also be made available at this pin. pin. A bias voltage midway between the analog power supply rails can be output at this pin. pin. A bias voltage midway between the analog power supply rails can be output at this pin. pin. A bias voltage midway between the analog power supply rails can be output at this pin. pin. A bias voltage midway between the analog power supply rails can be output at this pin. pin. A bias voltage midway between the analog power supply rails can be output at this pin. pin. A bias voltage midway between the analog power supply rails can be output at this pin.
pin. A bias voltage midway between the analog power supply rails can be output at this pin. pin. A bias voltage midway between the analog power supply rails can be output at this pin. EP Exposed Pad. Connect the exposed pad to AVSS.
Figure 58. Internal Temperature Sensor Accuracy Figure 59. Internal Oscillator vs. Temperature
AD4195-4 for various output data rates, gain settings, and filters. when the ADC is continuously converting on a single channel. Table 7. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV) Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits)
Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits) (Continued) Table 9. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV) Table 10. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits) Table 11. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV)
Table 11. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV) (Continued) Table 12. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits) Table 13. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Sinc5 + Avg Filter, FILTER_FS = 208 Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Sinc5 + Avg Filter, FILTER_FS = 208
Table 15. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Sinc5 + Avg Filter Table 16. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Sinc5 + Avg Filter
Figure 60. AD4195-4 Basic Connection Diagram temperature, and weigh scale applications. differential analog inputs. The AD4195-4 uses flexible multiplexing. (AINP) and/or negative input (AINM). digital power supply voltages are selected using the multiplexer. with both internal and externally applied references. The AD4195-4 contains a Σ-Δ modulator followed by a digital filter. power supply monitoring, can be interleaved with conversions. front-end circuitry may require some settling time.
analog.com Rev. 0 | 31 of 94 excitation current chopping, offset register, and gain register. Each channel is then linked to a setup. Serial Interface The AD4195-4 has a 4-wire SPI (CS, SDI, SDO, SCLK). CS can be tied low. Therefore, only three pins are required for communication between the ADC and the microprocessor. The on-chip registers are accessed through the serial interface. Main Clock The device has an internal 16MHz clock. The clock is divided by 2 internally. Use the internal clock or an external clock as the clock source for the device. The internal clock can also be made available on Pin CLK if a clock source is required for external circuitry. Temperature Sensor The on-chip temperature sensor monitors the die temperature. General-Purpose Inputs/Outputs The AD4195-4 has four general-purpose inputs/outputs. These can be used for driving external circuitry. For example, an external multiplexer can be controlled by these outputs. Calibration Both internal offset calibration, and system offset and full-scale calibration are included on chip. Therefore, the user has the option of removing offset errors internal to the device only, or removing the offset or gain errors of the complete end system. The full-scale error for all gains is factory calibrated. Therefore, no further internal full-scale calibrations are required. Excitation Currents The device contains two excitation currents that can be set inde- pendently to 10µA, 50µA, 100µA, 250µA, 500µA, 1mA, or 1.5mA. The excitation currents can be added by outputting them on the same pin. Bias Voltage A bias voltage generator is included on chip. Therefore, signals from thermocouples can be biased suitably. The bias voltage is set to (AVDD + AVSS)/2 and can be made available on any analog input pin. Bridge Power-Down Switches (PDSW) Two low-side power switches allow the user to power down bridges that are interfaced to the ADC. Diagnostics The AD4195-4 includes numerous diagnostics such as the follow- ing: ►Reference detection ►Overvoltage/Undervoltage detection ►CRC on SPI communications ►CRC on the memory map ►SPI read/write checks These diagnostics allow a high level of fault coverage in an applica- tion. POWER SUPPLIES The AD4195-4 operates with an analog power supply voltage from 4.75V to 5.25V. The device accepts a digital power supply from 1.7V to 5.25V. The device has two independent power supply pins: AVDD and IOVDD: ►AVDD is referred to AVSS. AVDD powers the internal analog regulator that supplies the ADC. ►IOVDD is referred to DGND. This supply sets the interface logic levels on the SPI interface and powers an internal regulator for operation of the digital processing. Unipolar Analog Supply Operation (AVSS = DGND) When the AD4195-4 is powered from a unipolar analog supply, AVSS and DGND can be shorted together on one single ground plane. With this setup, an external level shifting circuit is required when using truly bipolar inputs to shift the common-mode voltage. Recommended regulators include the LT1962EMS8-5, which has a low quiescent current. Bipolar Analog Supply Operation (AVSS ≠ DGND) The AD4195-4 can operate with AVSS set to a negative voltage, which allows true bipolar inputs to be applied. This allows a truly fully-differential input signal centered around 0V to be applied to the AD4195-4 without the need for an external level shifting circuit. For example, with a 5V split supply, AVDD = +2.5V and AVSS = −2.5V. In this use case, the AD4195-4-internally level shifts the signals, which allows the digital output to function between DGND (nominally 0V) and IOVDD. The maximum difference allowed between AVSS and IOVDD is 6.35V. Therefore, if AVSS = −2.5V, IOVDD can equal +3.85V or less.
is the drive edge, and the rising edge of SCLK is the sample edge. data is clocked in on the rising/sample edge. Figure 61. SPI Mode 3, SCLK Edges For more details, see the Digital Interface section. ►Channel configuration: Select AINP and AINM for each channel. Select one of the eight allowable setups for each channel. gain, reference source, and polarity. on AINP and AINM, and reference detect. ►ADC control: Select ADC operating mode and main clock source. inputs because each channel can have its own dedicated setup. to be interleaved with conversions. Channels are enabled using the CHANNEL_EN register. 18, respectively. The CHANNEL_EN register is shown in Table 19. Table 17. CHANNEL_SETUP0 Register Table 18. CHANNEL_MAP0 Register
Table 19. CHANNEL_EN Register Figure 62. Setup Structure
minimize any error due to lead resistance. select the reference source, and set the gain and the polarity. Table 20. MISC0 Register Table 21. AFE0 Register Table 22. FILTER0 Register Table 23. FILTER_FS0 Register Table 24. OFFSET0 Register Table 25. GAIN0 Register
ADC. The power-on reset value of an offset register is 0x000000. coefficient for the ADC. The gain registers are read/write registers. see the Calibration section. (for example, the SPI_ERR flag) in the ERROR register is set. details on the diagnostics available, see the Diagnostics section. The details of this register are shown in Table 30. Table 26. INTERFACE_CONFIG_C Register Table 27. INTERFACE_STATUS_A Register
Table 28. ERROR_EN Register Table 29. ERROR Register Table 30. ADC Control Register
The channels are enabled through the CHANNEL_EN register. the highest enabled channel. Any unabled channels are bypassed. conversions on all enabled channels are complete. Figure 65. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups
analog.com Rev. 0 | 42 of 94 1. Power-down switches (which can be enabled on GPIO0 and GPIO1). 2. GPIO_OUTPUT_DATA. Any GPIOs not used as power-down switches can function as general-purpose output pins. 3. CHANNEL_TO_GPIO. The relevant bits of the current channel in the sequencer are output on any pins not used for functions as mentioned in priority 1 and 2 above. Note that it is possible to enable excitation currents or enable REFIN2 (GPIO0/GPIO1) on these pins also. Therefore, the user must review all settings to ensure the pins have correct function in the application. BIAS VOLTAGE GENERATOR A bias voltage generator is included on the AD4195-4 (see Fig- ure 71). When enabled on an analog input, it biases the pin to (AVDD + AVSS)/2. This function is useful in unbiased thermocouple applications, as the voltage generated by the thermocouple must be biased around some DC voltage if the ADC operates from a unipolar power supply. The bias voltage generator is controlled using the VBIAS bits in the V_BIAS register (see Table 115). The power-up time of the bias voltage generator is dependent on the load capacitance. For more details, see the Specifications section. MULTIPLEXER CHOPPING The AD4195-4 includes multiplexer chopping (enabled using the CHOP_ADC bits in Table 101). With chop enabled (the two bits are set to 01 binary), the ADC offset and offset drift are minimized. When chop is enabled, the analog input pins are continuously swapped. Therefore, with the analog input pins connected in one di- rection, the settling time of the filter is allowed to elapse until a valid conversion is available. The analog input pins are then inverted and another valid conversion is obtained. Subsequent conversions are then averaged to minimize the offset. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. As two conversions are being averaged, the RMS noise improves by √2. Therefore, the p-p resolution improves by 0.5 bits approximately. Chopping may affect the output data rate and settling time. For example, with the Sinc3 filter, the output data rate is reduced by a factor of three approximately while the settling time is increased by a factor of two approximately when comparing chopping enabled versus chopping disabled. For other filters such as the post filters, chopping has only a small impact on the output data rate and settling time. The Digital Filter section lists the settling times for the different filter types with chop disabled. With chop enabled, the first conversion takes a time of twice this settling time while subsequent conversions occur at the settling time specified for the filter. Chopping also adds first order notches at odd integer multiples of nfADC/2. For example, using the Sinc3 filter with an output data rate of 50SPS, notches are placed at 25Hz, 75Hz, and 125Hz. CLOCK The AD4195-4 includes an internal 16MHz clock on chip. Use either the internal or an external clock as the clock source to the AD4195-4. The clock source is selected using the CLOCKSEL bits in the CLOCK_CTRL register (see Table 83). The internal clock can also be made available at the CLK pin. This is useful when several ADCs are used in an application and the devices must be synchronized. The internal clock from one device can be used as the clock source for all ADCs in the system. For more details, see the ADC Synchronization section. The AD4195-4 can also use an externally supplied clock connected to the CLK pin. The logic levels of this clock input are defined by the voltage applied to the IOVDD pin. The AD4195-4 includes an internal divide by 2, 4, 8, which is se- lectable through the CLOCKDIV bits in the CLOCK_CTRL register. This divider divides the internal or external clock source selected for the ADC. The default setting is an internal divide by 2. STANDBY AND POWER-DOWN MODES In standby mode, most blocks are powered down. The LDOs remain active so that registers maintain their contents. By default, all other functions are disabled in standby mode. However, through the STANDBY_CTRL Register, a user can select which functions to remain active in standby mode. The excitation currents, internal reference, power-down switches, pull-up currents, bias voltage, and internal clock, if enabled in the system, can remain active in standby mode by setting bits in the STANDBY_CTRL register appropriately. Diagnostics are disabled in standby mode. When exiting standby mode, the AD4195-4 requires 160 MCLK cy- cles approximately to power up and settle. MCLK is the main clock being used by the ADC rather than the applied clock frequency (internal oscillator or external clock frequency). Therefore, if the applied clock is divided by 4 or 8, the time to exit standby is longer. If an external main clock is being used, ensure that it is active before issuing the command to exit standby mode. Do not write to the ADC_ CTRL register again until the ADC has powered up and settled. In power-down mode, all blocks are powered down, including the LDOs. All registers lose their contents, and the digital outputs GPIO0 to GPIO3 are placed in tristate. To prevent accidental entry to power-down mode, the ADC must first be placed into standby mode. If an external main clock is being used, keep it active until the device is placed in power-down mode. Exiting power-down mode requires the pattern of 63 1s and one 0 repeated three times on SDI with CS low. The AD4195-4 requires 1.4ms approximately to power up and settle. After this time, the user can access the on-chip registers.
analog.com Rev. 0 | 43 of 94 CALIBRATION The AD4195-4 provides three calibration modes that can be used to eliminate the offset and gain errors on a per setup basis: ►Internal zero-scale calibration mode ►System zero-scale calibration mode ►System full-scale calibration mode The internal gain error is factory calibrated. Therefore, internal full-scale calibration is not supported on the AD4195-4. Only one channel can be active during calibration. When converting an ana- log input, the internal ADC conversion result is scaled using the ADC calibration registers before being written to the DATA register. The default value of the OFFSET register is 0x000000, and the nominal value of the GAIN register is 0x555555. The calibration range of the ADC gain is from 0.4 × VREF/gain to 1.05 × VREF/gain. For more details, see the Span and Offset Limits section. The following equations show how the values in the OFFSET and GAIN registers are used within the AD4195-4. Note that the OFFSET register uses twos complement. In unipolar mode, the ideal relationship, that is, not taking into account the ADC gain error and offset error, is as follows: Da ta = 0.75 × V I N V RE F × 2 23 − O f f s et × G ai n 0 × 400000 × 2 (1) In bipolar mode, the ideal relationship, that is, not taking into account the ADC gain error and offset error, is as follows: Da ta = 0.75 × V IN V RE F × 2 23 − O f f s et × G ai n 0 × 400000 (2) To start a calibration, write the relevant value to the mode bits in the ADC_CTRL register (see Table 89). The RDY pin (shared with SDO by default but can be output on DIG_AUX1) and the RDYB bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding OFFSET or GAIN register are updated, the RDYB bit in the status register is reset, the RDY pin returns low, and the AD4195-4 reverts to idle mode. Note that if the RDY pin is shared with SDO, the pin is tristated when CS is high. During an internal offset calibration, the selected positive analog input pin is disconnected, and it is connected internally to the selected negative analog input pin. For this reason, it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. System calibrations expect the system zero-scale (offset) voltage or system full-scale (gain) voltage to be applied to the selected positive and negative pins before initiating the calibration mode. As a result, errors external to the ADC are removed. The system zero- scale calibration must be performed before the system full-scale calibration. From an operational point of view, treat a calibration like another ADC conversion. Set the system software to monitor the RDYB bit in the status register or the RDY pin to determine the end of a calibration via a polling sequence or an interrupt-driven routine. An internal/system offset calibration and system full-scale calibra- tion requires a time equal to the settling time of the selected filter to be completed. A calibration can be performed at any output data rate. Using lower output data rates results in better calibration accuracy and is accurate for all output data rates. The internal gain error is factory calibrated for all gains. Therefore, if the default value in the GAIN register is not overwritten by a system full-scale calibration or a di- rect write to the GAIN register, the AD4195-4 automatically applies the appropriate gain coefficient internally when the PGA gain is changed. If a system full-scale calibration has been performed or the GAIN register has been written to, a new calibration is then required for a given channel if the reference source or the PGA gain for that channel is changed. The AD4195-4 provides the user with access to the on-chip calibra- tion registers, which allows the microprocessor to read the calibra- tion coefficients from the device and to write its own calibration coefficients from prestored values in the electronically erasable programmable read‐ only memory (EEPROM). A read or write of the OFFSET and GAIN registers can be performed at any time except during an internal or self-calibration. The values in the calibration registers are 24 bits wide. The span and offset of the device can also be controlled using the registers. SPAN AND OFFSET LIMITS System calibration can be used to compensate for offset or gain errors in the external circuit and to control the input span and offset of the device. Whenever system calibration is performed, the amount of input offset and span adjustments that can be accommodated is limited. The input span is the difference between the input voltage that corresponds to the positive full-scale code and the input voltage that corresponds to the negative full-scale code. The range of input span achievable with system calibration has a minimum value of 0.8 × VREF/gain and a maximum value of 2.1 × VREF/gain. The input span and offset adjustment must also account for the limitation on the positive full-scale code voltage (1.05 × VREF/gain) and negative full-scale code voltage (−1.05 × VREF/gain). Therefore, to determine the limits for system offset (zero-scale) and gain (full-scale) calibrations, the user must ensure that the offset after adjustment plus the maximum positive span range after adjustment does not exceed 1.05 × VREF/gain. The amount of offset and span adjustment that can be accommo- dated depends also on whether the configuration is unipolar or bipolar. This is the best shown by the following examples.
analog.com Rev. 0 | 44 of 94 If the device is used in unipolar mode with a required span of 0.8 × VREF/gain, the offset range that the system calibration can handle is from −1.05 × VREF/gain to +0.25 × VREF/gain. If the device is used in unipolar mode with a required span of VREF/gain, the offset range that the system calibration can handle is from −1.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the device is used in unipolar mode and required to remove an offset of 0.2× VREF/gain, the span range that the system calibration can handle is 0.85 × VREF/gain. If the device is used in bipolar mode with a required span of ±0.4 × VREF/gain, then the offset range that the system calibration can handle is from −0.65 × VREF/gain to +0.65 × VREF/gain. If the device is used in bipolar mode with a required span of ±VREF/gain, the offset range the system calibration can handle is from −0.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the device is used in bipolar mode and required to remove an offset of ±0.2 × VREF/gain, the span range that the system calibration can handle is ±0.85 × VREF/gain.
from frequencies at the fMOD rate and at odd multiples of this rate. pushes the first unprotected zone of the AD4195-4 out to 2 × fMOD. However, the modulator is open to noise for even multiples of fMOD. There is no attenuation at these zones. chop frequency used on the AD4195-4. Figure 92. Rejection of Out of Band Tones (ADC Only) depends on the environment of operation.
analog.com Rev. 0 | 52 of 94 The AD4195-4 digital interface is used to access the user configu- ration registers, initiate the ADC conversions, perform diagnostic tests, and readback conversion results. The interface uses 4 wires (CS, SCLK, SDI, and SDO). The part can also be operated with CS hardwired low. The interface is compatible with QSPI™ and MICROWIRE interface standards as well as most digital signal processors (DSPs). For both read and write SPI transactions, data is sampled on the rising edge of SCLK. For all SPI transactions, the most significant bit (MSB) of each byte is shifted first. The SDO line also acts as a data ready signal (RDY) by default. When data is available to be read from the AD4195-4 device, the SDO line is brought low. Alternatively, a dedicated data ready signal can be brought out on DIG_AUX1. All communication to the AD4195-4 begins with an instruction phase, which indicates whether the operation is a read or write operation and which register is being accessed. This is followed by the data phase where the data is written to the ADC (using SDI) or read from the ADC using SDO. The logic level of the AD4195-4 digital interface is set by the IOVDD voltage, and can range from 1.7V to 5.25V. For a detailed description of the addresses and functions of each of the AD4195-4 user configuration registers, see the On-Chip Register Map section. ADC CONVERSION MODES AND ACCESSING CONVERSIONS By default, the ADC continuously converts using the Sinc5 + Avg fil- ter (MODE bits in Table 89 set to 000b). Each enabled channel has a dedicated data register (Bit MULTI_DATA_REG_SEL in Table 89 is set to 0). Register DATA_PER_CHANNELn holds the conversion result for CHANNELn. The RDYB bit in Table 69 goes low each time a conversion on all enabled channels is complete. If CS is low, the SDO line also goes low when conversions on all enabled channels are complete because the RDY signal is available on SDO by default. RDY can alternatively be output on DIG_AUX1. When per channel data registers are used, STATUS bits cannot be automatically appended to the conversion result. To read each data register, an instruction phase is required, which indicates that the next operation is a read of the data register. RDY returns high when the conversion results from the enabled channels have been read. Enabled channels can also share a data register (Bit MULTI_DA- TA_REG_SEL in Table 89 is set to 1). The RDYB bit in Table 69 goes low each time a conversion is complete. The RDY signal also goes low if CS is low or RDY is output on DIG_AUX1. When reading the conversions, the 24-bit conversion can be accessed through the DATA_24B register. To read the contents of the STA- TUS register along with the conversion result, read Register DA- TA_24B_STATUS. The AD4195-4 also supports 16-bit conversion reads where the 16MSBs only of the conversion result can be read. The relevant registers are DATA_16B to read the 16-bit conversion and DATA_16B_STATUS to read the status bits along with the conversion result. When the conversion result is read from the data register, RDY goes high. The user can read the data registers additional times when the data register is shared or when per channel data registers are used, if required. However, the user must ensure that a data register is not being accessed at the completion of the next conversion if the register is to be updated. Otherwise, the new conversion word is lost. When several channels are enabled, the ADC automatically se- quences through the enabled channels. When per channel data registers are used, the user must configure the part for a single conversion on each enabled channel (REPEAT bits in Table 97 for the channel set to 0). When the enabled channels share a data register, multiple conversions can be performed on a channel each time it is selected in the sequence (again using the REPEAT bits in Table 97 for the channel). When all channels are converted, the sequence starts again with the first channel. The channels are converted in order from lowest enabled channel to highest enabled channel. The appropriate data register is updated as soon as each conversion is available. When the MODE bits in Table 89 are set to 100b, the sequence is performed once and the ADC is then placed in standby mode. If one channel only is enabled, a single conversion is performed. Rather than having an instruction and a data phase when reading back the conversions, there are two further options to simplify the readback of conversions: continuous read and continuous transmit. For more details, see the Continuous Read and the Continuous Transmit sections. CONTINUOUS READ Continuous read is designed to provide maximum throughput from the ADC. Access to the register map is disabled to allow simple shift register access to the ADC conversion data. Continuous read is enabled using the CONT_READ bits in Table 89 (setting 01b enables continuous read), which turns the SPI interface into a simple (duplex) shift register that can only shift out an ADC conversion result while simultaneously checking for an exit command and/or software reset. No instruction phase is required when reading ADC data. Continuous read can only be used when all enabled channels share a data register. This interface option only supports read access from the ADC data register plus optionally appended status register and/or CRC. Conversion data is 24-bit wide in this mode. CS can be toggled at the end of the read or held permanently low. Taking CS high three-states SDO and resets the SPI state. If CS is not brought high after performing the ADC read, the LSB of data continues to drive SDO (or revert to RDY, depending on the DIG_AUX1 configuration). Continuous read must only be used if the ADC is enabled in a continuous conversion mode. The SDI pin must be kept low or high
analog.com Rev. 0 | 55 of 94 DEVICE IDENTIFICATION The following registers contain identification information about the AD4195-4. The VENDOR_ID register, to identify Analog Devices, Inc., as the vendor of the device, the CHIP_TYPE register to identify the category of Analog Devices products the device belongs to, the PRODUCT_ID register to be used in conjunction with CHIP_TYPE to identify a device, and the CHIP_GRADE register to record the device revision and performance grade. The SPI_RE- VISION register offers information on the SPI interface revision. The AD4195-4 identifies as follows: ►VENDOR_ID = 0x0456 ►CHIP_TYPE = 0x07 ►PRODUCT_ID = 0x004C ►CHIP_GRADE = 0x04 ►SPI_REVISION = 0x83 DEVICE RESET The AD4195-4 provides three options for performing a device reset: a hardware reset, a software reset, and a reset by writing a specific sequence to the SDI pin. A reset sets the state of all user configuration registers listed in the on-chip register map to their default values (for more details, see the On-Chip Register Map section). The POR_FLAG_S bit in Table 69 is set when a reset occurs. A POR hardware reset is initiated by taking the IOVDD/REGCAP_D power supply below a threshold voltage and the AD4195-4 remains in a reset state until the voltage returns above the threshold volt- age. The threshold voltage has hysteresis to ensure the voltage recovers sufficiently before exiting POR. To implement a software reset, Bit SW_RESET and Bit RESET_SW in Table 43 both need to be set to 1. These bits are automatically reset to 0 when the reset has occurred. Another reset option is to write a specific pattern to the AD4195-4. This is required when the SPI is operated with CS hardwired low. To initiate a reset, write a pattern of 63 1s followed by one 0 three times to the AD4195-4while CS is held low. Note that a software reset is not possible in continuous read or continuous transmit. A reset by writing the specific sequence of 1s and 0s works for all operating modes. The AD4195-4 requires a short period of time to reset. If the digital host attempts to perform an SPI transaction before the device is ready, the transaction may not succeed and the NOT_READY_ERR bit in Table 67 is set. The bit can be cleared by writing 1 to its location. Interrogate the NOT_READY_ERR bit in Table 67 and the DEVICE_ERROR bit in Table 93 to verify complete initialization. If any error bit is flagged, perform a device reset. IO DRIVE STRENGTH The serial interface can operate with a power supply as low as 1.7V. However, at this low voltage, the digital outputs may not have sufficient drive strength if there is moderate parasitic capacitance on the board or the SCLK frequency is high. The DIG_OUT_STR bit in Table 81 increases the drive strength of all digital output pins. SDO_RDYB_DLY The serial interface uses a shared SDO and RDY pin by default. During a data read, this pin outputs the data from the register being read. After the read is complete, the pin reverts to outputting the RDY signal after a short fixed period of time (see the parameter t7 in the Timing Characteristics section). However, this time may be too short for some microcontrollers to reliably sample the last data bit and can be extended until the CS pin is brought high by setting the SDO_RDYB_DLY bit in the PIN_MUXING register (see Table 81) to 1. This means that CS must be used to frame each read operation and complete the serial interface transaction. Note that RDY can also be output on the DIG_AUX1 pin if separate SDO and RDY pins are required. In this case, the SDO pin contin- ues to output the LSB of the data register.
analog.com Rev. 0 | 56 of 94 The AD4195-4 offers several synchronization options, which allow the user to control the start of conversions on a single device or to ensure synchronization of multiple devices in a multi AD4195-4 design. STANDARD SYNCHRONIZATION When the SYNC_CTRL bits in the PIN_MUXING register (see Table 81) are set to 01b, the SYNC_IN pin functions as a synchroni- zation input. The SYNC_IN input lets the user reset the modulator and the digital filter without affecting any of the setup conditions on the device. The sequencer is also reset. This feature allows the user to control the start of sampling. SYNC_IN must be low for at least two main clock cycles to ensure that synchronization occurs. If multiple AD4195-4 devices are operated from a common main clock, they can be synchronized to sample their analog inputs simultaneously. This synchronization is normally done after each AD4195-4 device has performed its own calibration or has calibra- tion coefficients loaded into its calibration registers. A falling edge on the SYNC_IN input resets the digital filter and the analog modulator and places the AD4195-4 into a consistent known state. While SYNC_IN is low, the AD4195-4 is maintained in this known state. The device is taken out of reset on the main clock rising edge following the SYNC_IN input low to high transition. Therefore, when multiple devices are being synchronized, take the SYNC_IN input high on the main clock falling edge to ensure that all devices sample SYNC_IN as high on the main clock rising edge. If the SYNC_IN input is not taken high sufficiently before the main clock edge, a difference of one main clock cycle between the devices is possible, that is, the instant at which conversions are available differs from device to device by a maximum of one main clock cycle. SYNC_IN can also be used as a start conversion command for a single channel when in standard synchronization mode. Taking SYNC_IN high starts a conversion, and the falling edge of the RDY output indicates when the conversion is complete. The settling time is required for each data register update. After the conversion is complete, bring SYNC_IN low in preparation for the next conversion start signal. ALTERNATE SYNCHRONIZATION In alternate synchronization mode (SYNC_CTRL bits in Table 81 are set to 10b), the SYNC_IN input operates as a start conversion command when several channels of the AD4195-4 are enabled. When the SYNC_IN input is taken low, the ADC completes the conversion on the current channel, selects the next channel in the sequence, and then waits until the SYNC_IN input is taken high to commence the conversion. The RDY output goes low when the conversion is complete on the current channel, and the data register is updated with the corresponding conversion. Therefore, the SYNC_IN input does not interfere with the sampling on the cur- rently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. Alternate synchronization mode can be used only when several channels are enabled. It is not recommended to use this mode when a single channel is enabled.
analog.com Rev. 0 | 57 of 94 SYNCHRONIZING MULTIPLE AD4195-4 DEVICES The AD4195-4 supports synchronization of multiple AD4195-4 devices in a system. DIG_AUX1 and DIG_AUX2 can be used to synchronize the devices. The devices must share a common main clock. On one ADC, the main ADC, DIG_AUX2 is config- ured as a START pin using the DIG_AUX2_CTRL bits in the PIN_MUXING register (see Table 81). DIG_AUX1 is configured as a SYNC_OUT pin using the DIG_AUX1_CTRL bits in Table 81. From the START signal applied to the main ADC, a synchronization signal SYNC_OUT is generated, SYNC_OUT being synchronized with the internal main clock. SYNC_OUT is then applied to the SYNC_IN pins of all ADCs to force all ADCs to have synchronous conversion behavior.
analog.com Rev. 0 | 58 of 94 The AD4195-4 has numerous diagnostic functions on chip. Use the following features to ensure that: ►There are no overvoltages or undervoltages on the external reference/analog inputs. ►The external reference, if used, is present. ►The excitation currents, if used, are within specification. ►Only valid data is written to the on-chip registers. ►The power supply rails/internal LDOs are at expected levels. DEVICE ERROR If an error occurs when the AD4195-4 powers up and initializes, the DEVICE_ERROR flag in the ERROR register (see Table 93) is set. A device reset is recommended. The DEVICE_ERROR bit is cleared when the device initializes correctly from power-up or after a device reset. This bit cannot be cleared through a read operation. REFERENCE DETECT The AD4195-4 includes on-chip circuitry to detect if there is a valid reference for conversions or calibrations when the user selects an external reference as the reference source. This is a valuable feature in applications such as RTDs or strain gauges where the reference is derived externally. This feature is enabled when the REF_DIFF_MIN_ERR_EN bit in ERROR_EN register (see Table 91) is set to 1. If the voltage between the selected REFINn+ and REFINn− pins goes below 0.6V, the AD4195-4 detects that it no longer has a valid reference. In this case, the REF_DIFF_MIN_ERR bit in Table 93 is set to 1. The MAIN_ERR_S bit in the STATUS register (see Table 69) is also set. To clear the REF_DIFF_MIN_ERR bit, write a 1 to the bit. REFERENCE OVERVOLTAGE/UNDERVOLTAGE DETECTION The absolute voltage on the REFINn+ input pin can also be moni- tored. The REF_OV_UV_ERR_EN bit in the ERROR_EN register (see Table 91) enables the overvoltage/undervoltage reference diagnostic. An overvoltage is flagged when the voltage on REFINn+ exceeds AVDD by at least 65mV, whereas an undervoltage is flagged when the voltage on REFINn+ goes below AVSS by at least 65mV. The REF_OV_UV_ERR bit in the ERROR register (see Table 93) is set to 1 if an overvoltage or undervoltage is detected. To clear the REF_OV_UV_ERR bit, write a 1 to the bit. Note that the absolute voltage on the affected pin must be reduced to AVDD + 0.015V to reset the bit for an overvoltage condition, whereas the voltage on the pin must be reduced to AVSS − 0.01V to reset the bit for an undervoltage condition. CONVERSION ERRORS The conversion process can also be monitored by the AD4195-4. The function can be enabled using the ADC_CONV_ERR_EN bit in the ERROR_EN register (see Table 91). With this function enabled, the ADC_CONV_ERR bit is set if an error occurs. The ADC_CONV_ERR flag is set if there is a saturation (overflow or underflow) of the ADC result. This flag is updated in conjunction with the update of the data register and can be cleared by writing 1 to the bit. ANALOG INPUT OVERVOLTAGE/ UNDERVOLTAGE DETECTION The overvoltage/undervoltage monitor checks the absolute voltage on the internal multiplexer output pins, MUX+ and MUX−. MUX+ and MUX− can be separately checked for overvoltages and under- voltages. AINP_OV_UV_ERR_EN enables the undervoltage and overvoltage checks on MUX+. An overvoltage occurs when the voltage on MUX+ exceeds AVDD by at least 65mV, whereas an undervoltage occurs when the voltage on MUX+ goes below AVSS by at least 65mV. Similarly, an overvoltage/undervoltage check on MUX− is enabled using the AINM_OV_UV_ERR_EN bit in the ERROR_EN register (see Table 91). The error bits are AINP_OV_UV_ERR and AINM_OV_UV_ERR in the ERROR register (see Table 93) and these are set to 1 if an overvoltage/un- dervoltage is detected. To clear either bit, write 1 to the bit. Note that the absolute voltage on the affected pin must be reduced to AVDD + 0.015V for an overvoltage condition before the bit is cleared, whereas the voltage on the pin must be reduced to AVSS − 0.01V for an undervoltage condition before the bit is cleared. EXCITATION CURRENT COMPLIANCE The internal excitation currents require headroom to supply the specified excitation current value. The IOUTn_COMP_ERR flags in the ERROR register (see Table 93) are set to 1 when the excitation current magnitude is less than expected due to insufficient headroom. The flags can be enabled through the IOUTn_COMP_ERR_EN bits in the ERROR_EN register (see Table 91). To clear an error flag, write 1 to the appropriate bit. POWER SUPPLY MONITORS Along with converting external voltages, the ADC can monitor the analog and digital power supply voltages. When the inputs of (AVDD to AVSS) or (IOVDD to DGND) are selected, the voltage (AVDD to AVSS or IOVDD to DGND) is internally attenuated by 5, and the resulting voltage is applied to the Σ-Δ modulator. This is useful because variations in the power supply voltage can be monitored. LDO MONITORING There are several LDO checks included on the AD4195-4. Similar to the external power supplies, the voltage generated by the analog and digital LDOs are selectable as inputs to the ADC. The voltage generated by ALDO and DLDO can also be monitored by enabling the ALDO_PSM_ERR_EN bit and the DLDO_PSM_ERR_EN bit, respectively, in the ERROR_EN register (see Table 91). When enabled, the output voltage of LDO is continuously monitored. If the ALDO voltage drops below 1.5V typically, the ALDO_PSM_ERR flag is asserted. If the DLDO voltage drops below 1.6V typically, the
100100100000110010000100000000 XOR result
100011000110010000100000000 XOR result
11111110010000100000000 XOR result
1111101110000100000000 XOR result
111100000000100000000 XOR result
11100111000100000000 XOR result
1100100100100000000 XOR result
100101010100000000 XOR result
101101100000000 XOR result
1101011000000 XOR result
101010110000 XOR result
1010001000 XOR result
corruption or further register writes, the MM_CRC_ERR bit is set. location in the ERROR register. AVSS. These currents enable open-wire detection. Figure 100. Burnout Currents
analog.com Rev. 0 | 62 of 94 PULL-UP CURRENTS While the burnout currents are only active while a channel is being converted, the AD4195-4 also includes 100nA pull-up currents. These currents, if enabled, remain active on the AIN pins continu- ously. These currents can be enabled/disabled on a per pin basis through the I_PULL_UP register. If an AIN pin is floating, it is pulled to AVDD when the pull-up current is enabled. Therefore, an open on the pin is detectable. Note that if both AIN pins are floating and the pull-up currents are enabled, both pins are pulled to AVDD. Therefore, an open is not directly detectable. However, a conversion on each AIN pin with respect to AVSS can be used to detect the open. TEMPERATURE SENSOR Embedded in the AD4195-4 is a temperature sensor that is useful to monitor the die temperature. This is selected using the AINP[4:0] and AINM[4:0] bits in the CHANNEL_MAPn register. The sensitivity is 477µV/K, approximately. Subtract 5°C from the temperature sensor result. The temperature sensor has an accuracy of ±2°C typically.
analog.com Rev. 0 | 63 of 94 The analog inputs and reference inputs are differential. Therefore, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the device removes common-mode noise on these inputs. The analog and digital sup- plies to the AD4195-4 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of 2 x fMOD (fMOD being 2MHz when the main clock is 16MHz and clock divide = 2). The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD4195-4 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD4195-4 is high and the noise levels from the converter are so low, care must be taken with regard to grounding and layout. The PCB that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it results in the best shielding. In any layout, the user must keep in mind the flow of currents in the system, which ensure that the paths for all return currents are as close as possible to the paths the currents took to reach their destinations. Avoid running digital lines under the device because this couples noise onto the die. Allow the analog ground plane to run under the AD4195-4 to prevent noise coupling. The power supply lines to the AD4195-4 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. The AD4195-4 has two power supply pin: AVDD and IOVDD. The AVDD pin is referenced to AVSS, and the IOVDD pin is referenced to DGND. Decouple AVDD with a 1µF tantalum capacitor in parallel with a 0.1µF capacitor to AVSS. Place the 0.1µF capacitor as close as possible to the device, ideally right up against the device. Decouple IOVDD with a 1µF tantalum capacitor in parallel with a 0.1µF capacitor to DGND. All analog inputs must be decoupled to AVSS. If an external reference is used, decouple the REFINn+ and REFINn− pins to AVSS. The AD4195-4 also has two on-board LDO regulators: one that reg- ulates the AVDD supply and one that regulates the IOVDD supply. For the REGCAPA pin, it is recommended that a 0.1µF capacitor in parallel with a 1µF capacitor to AVSS be used. Similarly, for the REGCAPD pin, it is recommended that a 0.1µF capacitor in parallel with a 1µF capacitor to DGND be used. If using the AD4195-4 with bipolar supply operation, a separate plane must be used for AVSS.
analog.com Rev. 0 | 64 of 94 The AD4195-4 offers a high-resolution analog-to-digital function. Because the analog-to-digital function is provided by a Σ-Δ archi- tecture, the device is more immune to noisy environments, which makes it ideal for use in sensor measurement, and industrial and process control applications. WEIGH SCALE Figure 101 shows the AD4195-4 being used in a weigh scale application. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– terminals. Assuming a 5V excitation voltage, the full-scale output range from the transducer is 10mV when the sensitivity is 2mV/V. The excitation voltage for the bridge can be used to directly provide the reference for the ADC because the reference input range includes the supply voltage. A second advantage of using the AD4195-4 in transducer-based applications is that the bridge power-down switch can be fully utiliz- ed to minimize the power consumption of the system. The bridge power-down switch is connected in series with the low side of the bridge. In normal operation, the switch is closed, and measure- ments can be taken. In applications in which current consumption is being minimized, the AD4195-4 can be placed in standby mode, which significantly reduces the power consumed in the application. In addition, the bridge power-down switch can be opened while in standby mode, which avoids unnecessary power consumption by the front-end transducer. Note that the bridge power-down switch can be opened or closed while in standby mode (setting the STB_PDSWn bit in Table 85 to 1 ensures that the switch stays active in standby mode). Therefore, the switch can be closed while in standby mode to allow the bridge to power up and settle as the front-end circuitry may need some time to settle before the ADC core is powered up and conversions are performed. A typical procedure for reading the load cell is as follows: 1. Reset the ADC. 2. Set the CHANNEL_MAP0 register analog input to AIN5/AIN6. Assign Setup 0 to this channel through the CHANNEL_SETUP0 register. Configure Setup 0 to have a gain of 128 and select the reference source REFIN through the AFE0 register. Select the filter type through the FILTER0 register and set the output data rate through the FILTER_FS0 register. 3. Wait until RDY goes low. Read the conversion value. 4. Repeat step 3. The AD4195-4 on-chip diagnostics allow the user to check the circuit connections, monitor the power supply, reference, and LDO voltages, check all conversions for any errors, as well as monitor any read/write operations. In weigh scale applications, the circuit connections are verified using the reference detect and the burn- out currents. The REF_DIFF_MIN_ERR flag is set if the external reference REFIN is missing. The burnout currents (available in the MISC0 register) detect an open wire. As part of the conversion process, the analog input overvoltage/un- dervoltage monitors are useful to detect any excessive voltages on AINP and AINM. The power supply voltages and reference voltages are selectable as inputs to the ADC. Therefore, the user can periodically check these voltages to confirm whether they are within the system specification. Also, the user can check the LDO voltages. Finally, the CRC check, SCLK counter, and the SPI read/write checks make the interface more robust as any read/write operation that is not valid is detected. The CRC check highlights if any bits are corrupted when being transmitted between the processor and the ADC.
Figure 101. Weigh Scale Application well matched current sources, is ideally suited to these applications. input voltage span remains ratiometric to the reference voltage. compliance equals AVDD − 1.45V for the 500µA excitation current.
- Set the CHANNEL_MAP0 register analog input to AIN0/AIN1.
rate through the FILTER_FS0 register.
- Program the excitation currents to 500µA and output the
RENT_SOURCE0 and CURRENT_SOURCE1 registers.
- Wait until RDY goes low. Read the conversion value.
In the processor, implement the linearization routine for the PT100. filter is required to reject any interference. from AIN0/AIN1 for optimum system performance. Figure 102. 3-Wire RTD Application
fields are read-only (R), read/write (R/W), or write-1-to-clear (R/W1C) bits. Table 41. AD4195-4 Register Summary
Table 41. AD4195-4 Register Summary (Continued)
The operation of the serial interface is configured in this register. Table 42. Bit Names Table 43. Bit Descriptions for INTERFACE_CONFIG_A Register reset to 0 by the reset operation.
0 Address accessed is decremented by one for each data byte when accessing multibyte
1 Address accessed is incremented by one for each data byte when accessing multibyte
reset to 0 by the reset operation. The operation of the serial interface is configured in this register. Table 44. Bit Names Table 45. Bit Descriptions for INTERFACE_CONFIG_B Register 1 Single instruction mode is enabled.
This is a read only register. Table 46. Bit Names Table 47. Bit Descriptions for DEVICE_CONFIG Register uniquely identify a given product. Table 48. Bit Names Table 49. Bit Descriptions for CHIP_TYPE Register This register contains the low byte of the Product ID. Table 50. Bit Names Table 51. Bit Descriptions for PRODUCT_ID_L Register CHIP_TYPE register to identify a product. This register contains the high byte of the Product ID. Table 52. Bit Names Table 53. Bit Descriptions for PRODUCT_ID_H Register CHIP_TYPE register to identify a product.
This register identifies the product variations and device revision. Table 54. Bit Names Table 55. Bit Descriptions for CHIP_GRADE Register This register can be used to test write and read operations between the processor and the AD4195-4. Table 56. Bit Names Table 57. Bit Descriptions for SCRATCH_PAD Register Indicates the SPI interface revision. Table 58. Bit Names Table 59. Bit Descriptions for SPI_REVISION Register The low byte of the Vendor ID is stored in this register. Table 60. Bit Names
Table 61. Bit Descriptions for VENDOR_L Register The high byte of the Vendor ID is stored in this register. Table 62. Bit Names Table 63. Bit Descriptions for VENDOR_ H Register The serial interface is configured using this register. Table 64. Bit Names Table 65. Bit Descriptions for INTERFACE_CONFIG_C Register bytes of a multibyte register must be read/written in full. 1 Strict mode, multibyte registers require all bytes read/written. 4 SEND_STATUS Enables sending of synchronization pattern on SDO during every instruction phase. synchronization pattern is sent during the instruction phase. a 1 to the corresponding bit location.
Table 66. Bit Names Table 67. Bit Descriptions for INTERFACE_STATUS_A Register must be used to frame the transactions for this error check. register that is read-only is attempted. is only valid when strict register access is enabled. The STATUS register contains ADC and serial interface status information. Table 68. Bit Names Table 69. Bit Descriptions for STATUS Register The 16-bit conversion result is stored in this register when all enabled channels use a single data register. Table 70. Bit Names
Table 71. Bit Descriptions for DATA_16B Register when all enabled channels share a data register. Table 72. Bit Names Table 73. Bit Descriptions for DATA_16B_STATUS Register The 24-bit conversion result is stored in this register when all enabled channels use a single data register. Table 74. Bit Names Table 75. Bit Descriptions for DATA_24B Register when all enabled channels share a data register. Table 76. Bit Names
Table 76. Bit Names (Continued) Table 77. Bit Descriptions for DATA_24B_STATUS Register Table 78. Bit Names Table 79. Bit Descriptions for DATA_PER_CHANNELn Register Digital Filter/Control Logic/Sequencer. Table 80. Bit Names Table 81. Bit Descriptions for PIN_MUXING Register may affect the functionality of this feature. 0 Active channel number is not output to GPIO pins. 1 Active channel number is output to GPIO pins.
Table 81. Bit Descriptions for PIN_MUXING Register (Continued) 00 DIG_AUX2 Pin Disabled. High Impedance. edges. For MCLK divide by 8, the delay is 9 to 16 MCLK positive edges. 00 DIG_AUX1 Pin Disabled. High impedance. an active-low ADC Data-Ready indicator. This disables the shared RDY function on SDO. START functionality of DIG_AUX2. resetting the state of the channel sequencer. sequencer only advances to the next channel in the sequence when SYNC_IN is taken high. outputs. This can improve SPI timing at lower values of IOVDD. 0 Default Drive Strength. Recommended for higher IOVDD voltages. CS. It has no effect if RDY is output on the DIG_AUX1 pin. 0 Reset on last SCLK rising edge. set using this register. Writes to this register trigger a reset of the Digital Filter/Control Logic/Sequencer. Table 82. Bit Names
Table 83. Bit Descriptions for CLOCK_CTRL Register 00 DCLK Equals Main Clock Divide by 1. 01 DCLK Equals Main Clock Divide by 2. 10 DCLK Equals Main Clock Divide by 4. 11 DCLK Equals Main Clock Divide by 8. oscillator powers up the oscillator. 01 Internal Oscillator, Output to CLK Pin. 10 External Clock Input on CLK Pin. in their respective control registers for the bits in this register to have any effect. Table 84. Bit Names Table 85. Bit Descriptions for STANDBY_CTRL Register must remain enabled if the excitation currents remain active in standby mode.
Table 86. Bit Names Table 87. Bit Descriptions for POWER_DOWN_SW Register 0 Disable PDSW1 Switch on GPIO1 to AVSS. 1 Enable PDSW1 Switch on GPIO1 to AVSS. 0 Disable PDSW0 Switch on GPIO0 to AVSS. 1 Enable PDSW0 Switch on GPIO0 to AVSS. The mode of operation is set using this register. Writes to this register trigger a reset of the Digital Filter/Control Logic/Sequencer. Table 88. Bit Names Table 89. Bit Descriptions for ADC_CTRL Register sequences changes depending on which option is selected. function is not allowed when this feature is enabled. the data register is updated with the new conversion result once it is available. repeated in the second slot if CRC is enabled. 0 Status byte is not output.
Table 89. Bit Descriptions for ADC_CTRL Register (Continued) 1 Status byte is output. CS must be kept low for the entire data + status read. 00 Disable Continuous Read/Transmit. 01 Enable Continuous Read. This enables continuous read of the ADC data register. command 0xA5 to the SPI interface as the first byte of data after RDY goes low. INTERFACE_CONFIG_A register is not an option to exit continuous read. LDOs are also powered down. The on-chip registers do not retain their contents. though the modulator clocks continue to be provided.
measured offset coefficient is placed in the offset register of the selected channel. Select only one channel when zero-scale calibration is being performed. Digital Filter/Control Logic/Sequencer. Table 90. Bit Names Table 91. Bit Descriptions for ERROR_EN Register from the digital LDO is less than 1.6V typically. from the analog LDO is less than 1.5V typically. 9 IOUT1_COMP_ERR_EN When this bit is set, excitation current IOUT1 is continuously monitored. 8 IOUT0_COMP_ERR_EN When this bit is set, excitation current IOUT0 is continuously monitored.
7 REF_DIFF_MIN_ERR_EN When this bit is set, the differential voltage on the selected reference
REF_DIFF_MIN_ERR bit in the error register is set.
6 REF_OV_UV_ERR_EN When this bit is set, the overvoltage/undervoltage monitor on the REFINn+
pin of the channel being converted is enabled.
Table 91. Bit Descriptions for ERROR_EN Register (Continued)
5 AINM_OV_UV_ERR_EN When this bit is set, the overvoltage/undervoltage monitor on the AINM pin
of the channel being converted is enabled.
4 AINP_OV_UV_ERR_EN When this bit is set, the overvoltage/undervoltage monitor on the AINP pin
of the channel being converted is enabled.
3 ADC_CONV_ERR_EN When this bit is set, the conversions are monitored and the
1 MM_CRC_ERR_EN When this bit is set, a CRC calculation is performed on the memory map. Following this, periodic CRC checks are performed on the on-chip registers. register writes, the MM_CRC_ERR bit is set. Table 92. Bit Names Table 93. Bit Descriptions for ERROR Register
Channel 0 must always be one of the enabled channels. Certain ADC Modes (calibrations) are only performed on a single channel basis. Table 94. Bit Names Table 95. Bit Descriptions for CHANNEL_EN Register Filter/Control Logic/Sequencer. Table 96. Bit Names
Table 97. Bit Descriptions for CHANNEL_SETUP Register data registers are used (all channels must share a DATA register). all active channels. Alternatively, up to 8 channels can be configured differently. the channel (AINP input and AINM input). Writes to this register trigger a reset of the Digital Filter/Control Logic/Sequencer. Table 98. Bit Names Table 99. Bit Descriptions for CHANNEL_MAP Register
Table 99. Bit Descriptions for CHANNEL_MAP Register (Continued)
reset of the Digital Filter/Control Logic/Sequencer. Table 100. Bit Names Table 101. Bit Descriptions for MISCn Register currents should have the same value. 00 No Chopping of Excitation Currents. Excitation currents are not swapped/chopped. and the two conversions are averaged. must be performed for both polarities of chop. 00 No Chopping. No chopping is performed. averages the two conversions. This minimizes offset and offset drift. channel, the currents are only active when the channel is selected.
Filter/Control Logic/Sequencer. Table 102. Bit Names Table 103. Bit Descriptions for AFE Register 10 REFOUT, AVSS. The 2.5V REFOUT must be enabled separately in the REF_CONTROL register. differential results in 0x000000 and +Full-Scale results in 0xFFFFFF. 1001 PGA Gain = 1 Precharge Buffer.
n. In the FILTER register, the filter type is selected. Writes to this register trigger a reset of the Digital Filter/Control Logic/Sequencer. Table 104. Bit Names Table 105. Bit Descriptions for FILTER Register reasonable settling time while giving good rejection. Settings not listed are reserved. clock divide set to 2 and ADC chopping disabled). clock divide set to 2 and ADC chopping disabled). divide set to 2 and ADC chopping disabled). 0101 Post Filter for Average-By-16. The sinc filter (Sinc5 + Avg) is followed by an averaging block. performed. Settings not listed are reserved. amount of averaging. Allowed FILTER_FS values are 4, 8, 12, multiples of 4 up to 65532. are 4, 8, 12, multiples of 4 up to 256. are 4, 8, multiples of 4 up to 65532. Filter/Control Logic/Sequencer. Table 106. Bit Names
Table 107. Bit Descriptions for FILTER_FS Register recommended to place the ADC in standby or idle mode when writing to the OFFSET registers. Table 108. Bit Names Table 109. Bit Descriptions for OFFSET Register The AD4195-4 has eight gain registers, GAIN0 to GAIN7. Each GAIN register is associated with a setup, GAINn is associated with Setup n. default value is automatically overwritten if a system full-scale calibration is initiated by the user or the registers are written to. Table 110. Bit Names Table 111. Bit Descriptions for GAINn Register for its conversion using the REF_SELECT bits.
Table 112. Bit Names Table 113. Bit Descriptions for REF_CONTROL Register 0 Disable internal reference. 1 Enable internal reference and output to REFOUT. The internal bias voltage, which is equal to (AVDD + AVSS)/2, is enabled/disabled using this register. Table 114. Bit Names Table 115. Bit Descriptions for V_BIAS Register Pull-up currents of approximately 100nA can be enabled/disabled on the analog input pins using this register. Table 116. Bit Names Table 117. Bit Descriptions for I_PULLUP Register
Table 117. Bit Descriptions for I_PULLUP Register (Continued) the pin on which the current is available is selected using this register. Table 118. Bit Names Table 119. Bit Descriptions for CURRENT_SOURCE Register 00000 IOUT is Available on AIN0. 00001 IOUT is Available on AIN1. 00010 IOUT is Available on AIN2. 00011 IOUT is Available on AIN3. 00100 IOUT is Available on AIN4. 00101 IOUT is Available on AIN5. 00110 IOUT is Available on AIN6. 00111 IOUT is Available on AIN7. 01000 IOUT is Available on AIN8. 10001 IOUT is Available on GPIO0. 10010 IOUT is Available on GPIO1. 10011 IOUT is Available on GPIO2. 10100 IOUT is Available on GPIO3. being used. The internal reference can be enabled via the REF_CONTROL register.
Table 119. Bit Descriptions for CURRENT_SOURCE Register (Continued) Inputs/Outputs (GPIO0 to GPIO3) section. Table 120. Bit Names Table 121. Bit Descriptions for GPIO_MODE Register
When the GPIO pins are configured as outputs, the value on the pin is set in this register. Table 122. Bit Names Table 123. Bit Descriptions for GPIO_OUTPUT_DATA Register When the GPIO pins are configured as inputs, the value on the pin is displayed in this register. Table 124. Bit Names Table 125. Bit Descriptions for GPIO_INPUT_DATA Register
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0.05 MAX
0.02 NOM
0.203 REF
0.20 MIN
Figure 103. 32-Lead Lead Frame Chip-Scale Package [LFCSP] 4mm × 6mm Body and 0.75mm Package Height Table 126. Ordering Guide Table 127. Evaluation Boards