EVAL-AD4030-24-KTZ

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24-Bit, 2 MSPS, SAR ADC Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

► High performance ► Throughput: 2 MSPS maximum ► INL: ±0.9 ppm maximum from −40°C to +125°C ► SNR: 108.4 dB typical ► THD: −127 dB typical ► NSD: −169 dBFS/Hz typical ► Low power ► 30 mW at 2 MSPS ► 3 mW at 10 kSPS ► Easy Drive™ features reduce system complexity ► Low 1.2 μA input current for dc inputs ► Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF ► Flexible external reference voltage range: 4.096 V to 5 V ► Accurate integrated reference buffer with 2 μF bypass capacitor ► Programmable block averaging filter with up to 216 decimation ► Extended sample resolution to 30 bits ► Overrange and synchronization bits ► Flexi-SPI digital interface ► 1, 2, or 4 SDO lanes allows slower SCK ► Echo clock mode simplifies use of digital isolator ► Compatible with 1.2 V to 1.8 V logic ► 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint

APPLICATIONS

► Automatic test equipment ► Digital control loops ► Medical instrumentation ► Seismology ► Semiconductor manufacturing ► Scientific instrumentation FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD4030-24 is a 2 MSPS successive approximation register (SAR) analog-to-digital converter (ADC) with Easy Drive ™ . With a guaranteed maximum ±0.9 ppm integral nonlinearity (INL) and no missing codes at 24-bits, the AD4030-24 achieves unparalleled precision from −40°C to +125°C. Figure 1 shows the functional architecture of the AD4030-24. A low-drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4030-24 offers a typical dynamic range of 109 dB when using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decima- tion ratio can increase dynamic range up to 155.5 dB. The wide differential input and common mode ranges allow inputs to use the full ±V REF range without saturating, simplifying signal condition- ing requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4030-24. Both single- ended and differential signals are supported. The versatile Flexi-SPI serial peripheral interface (SPI) eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional DDR data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS. Echo clock mode and ADC host clock mode relax the timing requirements and simplify the use of digital isolators. The BGA package of the AD4030-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout.

analog.com Rev. 0 | 2 of 48 Signal-to-Noise-and-Distortion (SINAD) Sample Conversion Timing and Data

REVISION HISTORY

4/2022—Revision 0: Initial Version

analog.com Rev. 0 | 3 of 48 unless otherwise noted. Typical values are at TA = 25°C. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 24 Bits ANALOG INPUT Voltage Range VIN+ − VIN− −(65/64) × VREF +(65/64) × VREF V Absolute Input Voltage VIN+, VIN− to GND −(1/128) × VREF +(129/128) × VREF V Common-Mode Input Range (VIN+ + VIN−)/2 −(1/128) × VREF +(129/128) × VREF V Common-Mode Rejection Ratio (CMRR) fIN = 10 kHz 132 dB Analog Input Current Acquisition phase, T = 25°C 0.8 nA Converting any dc input at 2 MSPS 1.2 µA Analog Input Capacitance Acquisition phase 120 pF Outside acquisition phase (CPIN) 4 pF THROUGHPUT Complete Cycle 500 ns Conversion Time 264 282 300 ns Acquisition Phase1 244 260 275 ns Throughput Rate 0 2 MSPS DC ACCURACY No Missing Codes 24 Bits Integral Nonlinearity Error (INL) −0.9 ±0.1 +0.9 ppm Differential Nonlinearity Error (DNL) ±0.5 LSB Transition Noise 21 LSB rms Zero Error −90 0 +90 μV Zero Error Drift ±0.007 ppm/°C Gain Error Buffer disabled, REF = 5 V −0.004 ±0.0002 +0.004 %FS Buffer enabled, REFIN = 5 V −0.008 ±0.0006 +0.008 %FS Gain Error Temperature Drift Buffer disabled, REF = 5 V ±0.025 ppm/°C Buffer enabled, REFIN = 5 V ±0.07 ppm/°C Power Supply Sensitivity VDD_5V = 5.4 V ± 0.1 V ±0.1 ppm VDD_1.8V = 1.8 V ± 5% ±0.2 ppm Low Frequency Noise2 Bandwidth = 0.1 Hz to 10 Hz 1.3 µV p-p AC ACCURACY Dynamic Range 109 dB Noise Spectral Density (NSD) −169 dBFS/Hz Total RMS Noise 12.5 µV rms Signal-to-Noise Ratio (SNR) fIN = 1 kHz, −0.5 dBFS 105.6 108.4 dB Spurious-Free Dynamic Range (SFDR) fIN = 1 kHz, −0.5 dBFS 127 dB Total Harmonic Distortion (THD) fIN = 1 kHz, −0.5 dBFS −127 −115 dB Signal-to-Noise-and-Distortion (SINAD) RatiofIN = 1 kHz, −0.5 dBFS 105.6 108.3 dB Oversampled Dynamic Range Averaging = 2 112 dB Averaging = 256 133 dB Averaging = 65536 155.5 dB SNR VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V 106.7 dB SFDR VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V 130 dB THD VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V −130 dB

analog.com Rev. 0 | 4 of 48 Table 1. Parameter Test Conditions/Comments Min Typ Max Unit SINAD VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V 106.7 dB SNR fIN = 100 kHz, −0.5 dBFS 108.1 dB THD fIN = 100 kHz, −0.5 dBFS −113 dB SINAD fIN = 100 kHz, −0.5 dBFS 106.9 dB −3 dB Input Bandwidth 74 MHz Aperture Delay 0.7 ns Aperture Jitter 1.4 ps rms INTERNAL REFERENCE BUFFER External reference drives REFIN REFIN Voltage Range 5.3 V ≤ VDD_5V ≤ 5.5 V 4.95 5 5.05 V 4.8 V ≤ VDD_5V ≤ 5.25 V 4.5 V REFIN Bias Current −50 5 +50 nA REFIN Input Capacitance 40 pF Reference Buffer Offset Error REFIN = 5 V, TA = 25°C −100 ±25 +100 µV REFIN = 4.5 V, TA = 25°C ±25 μV REFIN = 4.096 V, TA = 25°C −100 ±25 +100 µV Reference Buffer Offset Drift ±0.3 µV/°C Power-On Settling Time 3 ms EXTERNALLY OVERDRIVEN REFERENCEExternal reference drives REF (REFIN = 0 REF Voltage Range 5.3 V ≤ VDD_5V ≤ 5.5 V 4.95 5 5.05 V 4.8 V ≤ VDD_5V ≤ 5.25 V 4.5 V REF Current fS = 2 MSPS 1.8 µA REF Input Capacitance 2 µF DIGITAL INPUTS 1.14 V ≤ VIO ≤ 1.89 V Logic Levels Input Voltage Low (VIL) −0.3 +0.35 × VIO V Input Voltage High (VIH) 0.65 × VIO VIO + 0.3 V Input Current Low (IIL) −10 +10 µA Input Current High (IIH) −10 +10 µA Input Pin Capacitance 2 pF DIGITAL OUTPUTS 1.14 V ≤ VIO ≤ 1.89 V Conversion results available immediately after completed conversion Pipeline Delay Output Voltage Low (VOL) ISINK = 2 mA 0.25 × VIO V Output Voltage High (VOH) ISOURCE = 2 mA 0.75 × VIO V POWER SUPPLIES VDD_5V REF = 5 V 5.3 5.4 5.5 V REF = 4.5 V 4.8 5 5.25 V REF = 4.096 V 4.75 5 5.25 V VDD_1.8V 1.71 1.8 1.89 V VIO3 1.14 1.89 V Standby Current VDD_5V 500 µA

1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 2 See the low frequency noise plot in Figure 24. 1/f noise is canceled internally by auto-zeroing. Noise spectral density is substantially uniform from dc to fS/2. 3 When VIO < 1.4 V, Bit IO2X must be set to 1. See the Output Driver Register section. Table 2. Digital Timing Interface guaranteed by characterization and design. 2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.

Table 6. Echo Clock Mode Timing, DDR, 1-Lane Figure 8. Echo Clock Mode Timing, DDR, 1-Lane Table 7. Host Clock Mode Timing

ing conditions for extended periods may affect product reliability. Table 9. Thermal Resistance sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 10. AD4030-24, 64-Ball CSP_BGA damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 11. Pin Configuration Table 11. Pin Function Descriptions A7 RST DI Reset Input (Active Low). Asynchronous device reset. of the output driver register must be set to 1. B1 IN+ AI Positive Analog Input. IOGND P VIO Ground. Connect to the same ground plane as all GND pins. C1 IN− AI Negative Analog Input. C7 SDO3 DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. C8 SDO1 DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 2 μF bypass capacitor inside the package. When using the internal reference buffer, do not connect REF. D7 SDO2 DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. D8 SDO0 DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. sourced by the internal oscillator. F1 NIC Not Internally Connected. These pins are not connected internally. F7, F8, G7, G8 DNC Do Not Connect to These Pins. They are internally connected to digital output drivers in high-Z mode. G1 NIC Not Internally Connected. These pins are not connected internally.

H5 CS DI Chip Select Input (Active Low). H6 SDI DI Serial Data Input. 1 AI is analog input, P is power, DI is digital input, and DO is digital output.

analog.com Rev. 0 | 18 of 48 INTEGRAL NONLINEARITY ERROR (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½LSB before the first code transition. Positive full scale is defined as a level 1½LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 37). DIFFERENTIAL NONLINEARITY ERROR (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. ZERO ERROR (ZE) Zero error is the difference between the ideal midscale voltage, 0 V, and the actual voltage producing the midscale output code, 0 LSB. GAIN ERROR (GE) ½LSB above nominal negative full scale. The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. SPURIOUS-FREE DYNAMIC RANGE (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of a full-scale input signal and the peak spurious signal. EFFECTIVE NUMBER OF BITS (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINADdB − 1.76)/6.02. ENOB is expressed in bits. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first five harmonic compo- nents to the rms value of a full-scale input signal and is expressed in decibels. DYNAMIC RANGE (DR) Dynamic range is the rms voltage of a full-scale sine wave to the total rms voltage of the noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) RATIO SINAD is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. APERTURE DELAY Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. TRANSIENT RESPONSE Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. COMMON-MODE REJECTION RATIO (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 4.5 V p-p sine wave applied to the input common-mode voltage of frequency, f. C MRR d B = 10 × log P ADC _ IN P AD C _ OU T where: PADC_IN is the common-mode power at the frequency, f, applied to the inputs. PADC_OUT is the power at the frequency, f, in the ADC output. POWER SUPPLY REJECTION RATIO (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PS RR d B = 10 × log P V DD _ I N P A DC _ O U T where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output.

details on the use of these features. representing the input voltage difference. Features section for more information. shows the frequency response of the filter for an N = 1, 2, 3, 4, 5. Figure 39. Frequency Response Examples for the Block Averaging Filter Offset Registers section for more details. 0x0000 ≤ USER_GAIN ≤ 0xFFFF. saturation of the 24-bit, 16-bit, or 30-bit output differential codes. See the Gain Registers section for more details. pattern registers is output using the normal sample cycle timing.

analog.com Rev. 0 | 26 of 48 (400 pC) and exits shutdown mode (5 pC). When exiting shutdown mode, the REF pins are accurate after 30 µs.

mary section describe the operation of the AD4030-24 SPI. Figure 47. AD4030-24 Multilane SPI clock output for these clocking modes. of the user registers of the AD4030-24. maximum frequency of the CNV clock is 2 MSPS. ► SDO0 through SDO3 (outputs). Data lanes to the host controller. Table 13. BUSY_SCKOUT Pin Behavior vs. Clocking Mode signal from the internal oscillator.

1. Perform a read back from a dummy register address 0x3FFF, to

enter the register configuration mode.

1. Read back from or write to the desired user register addresses.
2. Exit the register configuration mode by writing 0x01 to register

register updates to take effect.

bulk read starting at a given address. Figure 48. Stream Mode Bulk Register Read Back Operation

into the output shift register.

1. The quiet zone immediately before the rising edge of CNV is

SCK on the SPI and ease the timing requirements for the interface. N+1. If not, then sample N is overwritten with sample N+1. Figure 49. Example Timing for Data Transfer Zones

(see Table 16 for register descriptions). bit field of the modes register (see the Modes Register section). rising edge of the CNV pulse for the last sample in the block. Figure 50. Typical Sample Cycle for SPI Clocking Mode

coming from the SDO lanes to reconstruct the original sample word. Data Clocking Requirements and Timing section. Table 14. AD4030-24 Supported Data Output Modes

1 SDO0 SPI SDR only 24 or 32

2 SDO0, SDO1 SPI SDR only 24 or 32

4 SDO0, SDO1, SDO2, SDO3SPI SDR only 24 or 32

analog.com Rev. 0 | 37 of 48 The following layout guidelines are recommended to achieve maxi- mum performance of the AD4030-24: ►The AD4030-24 contains internal 1 μF bypass capacitors for VDD_5V and VDD_1.8V, and VIO contains an internal 0.2 μF capacitor, so no external bypass capacitors are required. This saves board space, bill of materials count, and reduces layout sensitivity. ►It is recommended to have all the analog signals flow in from the left side of the AD4030-24 and all the digital signals to flow in and out from the right side of the AD4030-24 because this helps isolate analog signals from digital signals. ►Use a solid ground plane under the AD4030-24 and connect all the analog ground (GND) pins and digital ground (IOGND) pins to the shared ground plane to avoid formation of ground loops. ►Traces routed to either the REFIN pin or REF pins must be isolated and shielded from other signals. Avoid routing signals beneath the reference trace (REFIN or REF). The REF pins are connected to an internal 2 µF capacitor, eliminating the need to place a decoupling capacitor on the output of the external reference buffer. If a noise reduction filter is placed between the output of the reference (or buffer) and the chosen reference input, it must be placed as close as possible to the AD4030-24.

Table 16. AD4030-24 Register Summary

Interface configuration settings. Table 17. Bit Descriptions for INTERFACE_CONFIG_A 0: Address accessed is decremented by one for each data byte when streaming. Additional interface configuration settings. Table 18. Bit Descriptions for INTERFACE_CONFIG_B 0: Streaming mode is enabled. The address decrements as successive data bytes are received. 1: Single instruction mode is enabled.

Table 19. Bit Descriptions for DEVICE_CONFIG uniquely identify a given product. Table 20. Bit Descriptions for CHIP_TYPE Table 21. Bit Descriptions for PRODUCT_ID_L High byte of the product ID.

Table 22. Bit Descriptions for PRODUCT_ID_H Identifies product variations and device revisions. Table 23. Bit Descriptions for CHIP_GRADE This register can be used to test writes and reads. Table 24. Bit Descriptions for SCRATCH_PAD Table 25. Bit Descriptions for SPI_REVISION

Table 26. Bit Descriptions for VENDOR_L Table 27. Bit Descriptions for VENDOR_H Defines the length of the loop when streaming data. Table 28. Bit Descriptions for STREAM_MODE Status bits are set to 1 to indicate an active condition. The status bits can be cleared by writing a 1 to the corresponding bit location.

Table 29. Bit Descriptions for INTERFACE_STATUS_A 4 CLOCK_COUNT_ERR 0 = No error. 1 = Incorrect Number of Clocks Detected in a Transaction. Write 1 to clear. Table 30. Bit Descriptions for EXIT_CFG_MD Table 31. Bit Descriptions for AVG 0x11 through 0x1F = invalid.

Table 32. Bit Descriptions for OFFSET_LB [7:0] USER_OFFSET[7:0] 24-Bit Offset. Twos complement (signed).

1 L S B =

Table 33. Bit Descriptions for OFFSET_MB [7:0] USER_OFFSET[15:8] 24-Bit Offset. Twos complement (signed).

1 L SB =

Table 34. Bit Descriptions for OFFSET_HB [7:0] USER_OFFSET[23:16] 24-Bit Offset. Twos complement (signed).

1 LS B =

Table 35. Bit Descriptions for GAIN_LB

Table 36. Bit Descriptions for GAIN_HB Table 37. Bit Descriptions for MODES 1 = DDR (only valid for echo clock mode and host clock mode). 000 = 24-bit differential data. 001 = 16-bit differential data + 8-bit common-mode data. 010 = 24-bit differential data + 8-bit common-mode data. 011 = 30-bit averaged differential data + OR bit + SYNC bit. 100 = 32-bit test data pattern (TEST_DATA_PAT). Table 38. Bit Descriptions for OSCILLATOR AD4630-24 based on the data word size, number of active SDO lanes, and data rate mode (SDR or DDR). 00 = no divide (divide by 1).

Table 39. Bit Descriptions for IO 1 = double output driver strength. 0 = normal output driver strength. Table 40. Bit Descriptions for TEST_PAT_BYTE0 Table 41. Bit Descriptions for TEST_PAT_BYTE1 Table 42. Bit Descriptions for TEST_PAT_BYTE2

Table 43. Bit Descriptions for TEST_PAT_BYTE3 Table 44. Bit Descriptions for DIG_DIAG Table 45. Bit Descriptions for DIG_ERR

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 57. 64-Ball Chip Scale Package Ball Grid Array [CSP_BGA] EVAL-AD4030-24-KTZ Evaluation Kit. EVAL-AD4030-24FMCZ Evaluation Board.