AD3530 AD | Alldatasheet
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8-Channel, 16-Bit Voltage Output DACs, On-Chip Reference, SPI Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►16-bit resolution, ±3 LSB16 INL, ±1 LSB16 DNL ►TUE: ±0.22% of FSR maximum ►Offset error: ±1.6mV maximum ►Gain error: ±0.26% of FSR maximum ►Guaranteed sourcing current of 50mA ►Ultra-low headroom: 25mV at 20mA load ►2.5V internal voltage reference, 5ppm/°C, typical ►62nV/√Hz noise spectral density (external reference) ►115nV/√Hz noise spectral density (internal reference) ►Output voltage, current, and die temperature monitors ►50MHz SPI write and read ►2.7V to 5.5V power supply range ►1.2V or 1.8V compatible digital interface ►Operating temperature range: −40°C to +125°C ►Small package: 2.1mm × 2.2mm, 25-ball WLCSP
APPLICATIONS
►Optical transceivers ►Test and measurement ►Industrial automation ►Data acquisition systems GENERAL DESCRIPTION The AD3530/AD3530R are low power, 8-channel, 16-bit, buffered voltage output, digital-to-analog converters (DACs) that include software-programmable gain controls that result in full-scale output spans of 2.5V or 5V for reference voltages of 2.5V. The devices op- erate from single, 2.7V to 5.5V supply ranges and are guaranteed monotonic by design. The AD3530R also offers a 2.5V, 5ppm/°C internal reference that is disabled by default. The devices include integrated multiplexers that allow monitor- ing of output voltages, currents, and internal die temperature. The AD3530/AD3530R are available in 2.1mm × 2.2mm, 25-ball WLCSP packages. The devices incorporate power-on reset (POR) circuits that ensure that the DACs output power up to and present at 32kΩ to ground until a valid write is executed. The DACs also contain power-down modes that reduce the current consumption down to 670μA, typical. The serial peripheral interface (SPI) and MICROWIRE®-compatible, 4-wire serial interface operates on logic levels as low as 1.08V up to 1.98V and clock rates up to 50MHz. Table 1. Device Family List
8 SPI Internal/ExternalAD3530R
8 SPI External AD3530
Figure 1. Functional Block Diagram
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REVISION HISTORY
1/2025—Revision 0: Initial Version
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ELECTRICAL CHARACTERISTICS
All specifications are TJ = −40°C to +125°C and typical at TA = 25°C, unless otherwise noted. Table 2. Electrical Characteristics
Table 2. Electrical Characteristics (Continued)
1 VDD/2 V Range = 0 to 2 × VREF
5.5 V Range = 0 to 2 × VREF
2 The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. 3 Voltage reference temperature coefficient is calculated as per the box method. See the Terminology section for further information. 4 The peak voltage glitch seen on the VOUTn channels when a different channel is monitored through MUX_OUT_SELECT(SEL). 5 Interface inactive. All channels in operating mode 0 with outputs unloaded. 6 Interface inactive. All channels in either operating mode 1, 2 or 3. +125°C, typical at TA = 25°C, unless otherwise noted. Table 3. AC Specifications 1 See the Terminology section. Measured using internal reference and range = 0 to VREF, unless otherwise noted. 2 Digitally generated sine wave (fOUT) at 1kHz.
All input signals are specified with rise time (tR) = fall time (tF) = 1ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL + VINH)/2. Table 4. SPI Interface Timing Specifications 1 Only applicable for stream mode functionality. Figure 2. Serial Read and Write Operation
Table 6. Absolute Maximum Ratings 1 Configured as the reference input pin. ing conditions for extended periods may affect product reliability. Table 7. Thermal Resistance
1 Simulation values on JEDEC 2S2P board with 4 thermal vias, still air (0m/sec
damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 5. WLCSP Pin Configuration Table 8. Pin Function Descriptions with a 0.1µF capacitor to GND. C3 IOVDD DI Digital Power Supply. The voltage on the IOVDD pin is specified in the Table 2 section. GND S Ground Reference Point for All Circuitry on the Device. E2 VOUT7 AO Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation. E3 VOUT6 AO Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation. E4 VOUT5 AO Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation. D4 VOUT4 AO Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation. E5 SDI DI Serial Data Input. Logic input. Provides data to be written to the device and is clocked into the register on the rising edge of SCLK. D5 CSB DI Active-Low Control Input. This is the frame synchronization signal for the input data. on the falling edge of SCLK and is valid on the rising edge of SCLK. B5 SCLK DI Serial Clock Input. Data transfers at rates of up to 50MHz for write and read operations. B4 VOUT0 AO Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation. A4 VOUT1 AO Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation. A3 VOUT2 AO Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation. A2 VOUT3 AO Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation. 1 AO is analog output pin, AI/O is analog input or output pin, S is supply pin, DI is the digital input pin, and DO is the digital input pin.
analog.com Rev. 0 | 19 of 45 Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a meas- urement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured with Code 256 loaded in the DAC register. It can be negative or positive. Offset Error Drift The offset error drift is a measurement of the relative variation of the offset with temperature. It is expressed in ppm/°C. Total offset at a given temperature is calculated as Deviation at T = Deviation at 25° C TC × T − 25 × V R ANG E 10 6 Full-Scale and Zero-Scale Error These errors measure the deviation from the ideal value at full scale and zero scale, at 25°C. The error is expressed as % of full-scale range (FSR). Full-Scale and Zero-Scale Error Drift These parameters measure the variation of the zero-scale and full-scale voltage as a function of the temperature, relative to the ideal zero-scale and full-scale voltages. They are expressed in ppm/°C. The total deviation over temperature is calculated using the same equation as offset error drift. DC PSRR and AC PSRR PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in the supplies for midscale output of the DAC. For DC PSRR, it is measured in mV/V and VDD is varied by ±10%. While for AC PSRR, it is measured in dB and a ±200mV p-p AC sweep signal is injected on VDD. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a given step change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV × sec and is measured when the digital input code is changed by 1 LSB. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. Digital feedthrough is specified in nV × sec and measured with a full-scale code change on the data bus, which means from all 0s to all 1s and vice versa. Output Noise Spectral Density Noise spectral density is a measurement of the internally generated random noise. Noise is measured at the DAC output when it is loaded with the midscale code and center frequency set to 10kHz. It is measured in nV/Hz . Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and the attenuat- ed version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as shown in the following equation: TC = V REF _ M A X − V REF _ MI N V REF _ NO M × TEMP _ RANGE × 10 6 (1) where: VREF_MAX is the maximum reference output measured over the total temperature range. VREF_MIN is the minimum reference output measured over the total temperature range. VREF_NOM is the nominal reference output voltage, 2.5V. TEMP_RANGE is the specified temperature range, −40°C to +125°C. DC Crosstalk DC crosstalk is the DC change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA.
AD3530R have 5ppm/°C 2.5V on-chip references. simplified block diagram of a DAC channel is shown in Figure 59. in parallel with 200pF to GND. Figure 59. DAC Channel Block Diagram
2 N × G
VOUTn is the output voltage seen at the selected DAC channel n. into the DAC register (0 to 65535 for the AD3530/AD3530R). N is the DAC resolution in bits. Table 9. AD3530/AD3530R Operating Modes
0 Normal operation0 0
register settings or the read and write capability of those registers. Control 0 Register section for more details. configuring the SEL bits on the Multiplexer Input Select 0 Register. MUX_OUT_SELECT(SEL) value should not change.
analog.com Rev. 0 | 21 of 45 where: VMEAS is the measured voltage output of the selected channel. MUX_OUT is the voltage output on the MUX_OUT pin in volts. The transfer function when using current output monitor: I ME AS = M U X _ O U T × 40 m A / V (4) where: IMEAS is the measured current at the output of the selected channel. MUX_OUT is the voltage output on the MUX_OUT pin in volts. The internal die temperature can also be monitored through the MUX_OUT pin by setting the MUX_OUT_SELECT(SEL) to 0x19. The transfer function used to derive the measured temperature with internal reference enabled is given by the following equation: T ME AS = MU X _ OU T − 0 . 44 where: TMEAS is the measured internal die temperature in °C. MUX_OUT is the voltage at the MUX_OUT pin in volts. The integrated multiplexer has a buffered output capable of provid- ing of ±5mA current. The errors of monitoring the VOUTn and IOUTn, where n is the channel number, are typically ±5mV and ±2mA, respectively. DAC CORE FUNCTIONS Each DAC channel has its own Input Register and DAC Register, as shown in Figure 59. Both registers are accessible through the serial interface. The DAC register stores digital code equivalent to the DAC output voltage while the input register acts as a temporary staging register before being passed on the DAC Register. With the LDAC function, one or more DAC registers could be updated in parallel with the data held in the input register. The DAC registers can be written to directly, in which case the corresponding output updates immediately without the need for a hardware or software LDAC. Directly writing to the DAC register does not affect the data stored in the input register. Writing to the MULTI_INPUT_CH register allows one or more input registers to be updated in a single write operation. The MULTI_IN- PUT_SEL_0 register determines which input register will be updat- ed with the data written to the multiple input register. See the Multiple Input Select 0 Register section for additional information. Similarly, writing to the MULTI_DAC_CH register allows one or more DAC registers to be updated in a single write operation. MULTI_DAC_INPUT_SEL_0 determines which DAC register will be updated with the data written to the multiple DAC register. See the Multiple DAC Select 0 Register section for more information. To ensure that the DAC update is successful, DAC register updates should only occur once every 640ns. Refer to tL2 and tL3 from Table 5. An error flag will also be asserted when a DAC update write is unsuccessful which can be check by reading the UPDATE_ERR bit on the Status Control Register. LDAC Function The LDAC function is used to initiate the transfer of the contents of select input registers to the corresponding DAC registers, thereby updating one or more VOUT pins at the same time. The LDAC function can be executed by hardware through the LDACB pin or by software through SW_LDAC_TRIG_A or SW_LDAC_TRIG_B registers. Both hardware and software LDAC perform the same function. Hardware LDAC The AD3530/AD3530R have active low LDACB pins that are falling edge sensitive. If the LDACB signal is brought low, the selected in- put register contents are transferred to corresponding DAC register. If LDACB is held low when writing to the device, the input registers appear transparent, and when an input register is written to, the DAC register is updated with the contents of the input register at the same time. When LDACB is held high, DAC codes can be written to any input registers without affecting the DAC output. Refer to Figure The Hardware LDAC Enable 0 Register is used to determine the DAC channels to be updated from the corresponding input registers when LDACB is active or asserted. By default, all DAC channels are selected and the HLD_EN_CH_n bitfields contain a 1. A 0 set on a HLD_EN_CH_n bitfield disables the hardware LDAC feature for the target DAC channel. Software LDAC The software LDAC function is synonymous to an LDACB falling edge. It provides a way to initiate a transfer of content between selected input registers to DAC registers through the serial interface via writing 1 to the SLD_TRIG_A bit on the Software LDAC Trigger
0 Register or to the SLD_TRIG_B bit on the Software LDAC Trigger
0 Register. The Software LDAC Enable 0 Register is used to determine the DAC channels to be updated from the corresponding input registers when a software LDAC is performed. By default, all DAC channels are selected and the SLD_EN_CH_n bitfields contain a 1. A 0 set in a SLD_EN_CH_n bitfield disables the software LDAC feature for the target DAC channel. POWER-ON RESET On power-up the input and DAC data registers of every DAC channel are loaded with a zero code. Meanwhile, the POR circuit ensures that the DAC output amplifiers are powered down (see Mode 3 in the Modes of Operation section) until the output operat- ing mode for the channel is changed. All registers are reset to their default values.
series resistance (ESR) and low effective series inductance (ESL). routing of the digital lines straight away from the analog functions. Figure 69. Evaluation Board Layout continuous to minimize ground resistance. parts of the board by using a digital ground. amplifier of the DAC acts like a resistor instead of an ideal switch. voltage would be around 4.963V. DAC_CHn registers considering several factors such as single vs.
SW_LDAC_EN_0(SLD_EN_CH_n) bitfields with the same data. Figure 76. Option 6 Example: Write to Multi_Input_Ch Register with a Soft-
Table 10. AD3530/AD3530R Register Summary
0 RESERVED 0x00 R/W
Table 10. AD3530/AD3530R Register Summary (Continued) 1 See the Multibyte Registers section for more details.
Table 11. Bit Descriptions for INTERFACE_CONFIG_A reset to their default values. 0: Address is decremented by one when streaming. 1: Address is incremented by one when streaming. 4 SDO_ENABLE SDO Pin Enable. reset to their default values. Table 12. Bit Descriptions for INTERFACE_CONFIG_B 1: Single instruction mode is enabled.
Table 13. Bit Descriptions for DEVICE_CONFIG uniquely identify a given product. Table 14. Bit Descriptions for CHIP_TYPE Table 15. Bit Descriptions for PRODUCT_ID_L High byte of the product ID.
Table 16. Bit Descriptions for PRODUCT_ID_H Table 17. Bit Descriptions for CHIP_GRADE Table 18. Bit Descriptions for SCRATCH_PAD Table 19. Bit Descriptions for SPI_REVISION
Table 20. Bit Descriptions for VENDOR_L Table 21. Bit Descriptions for VENDOR_H Table 22. Bit Descriptions for STREAM_MODE upper/lower limits of memory. Table 23. Bit Descriptions for TRANSFER_CONFIG
Table 23. Bit Descriptions for TRANSFER_CONFIG (Continued) Table 24. Bit Descriptions for INTERFACE_CONFIG_C multibyte register must be read/written in full. 0: Normal mode; no access restrictions. 1: Strict mode; multibyte registers require all bytes accessed. [1:0] CRC_ENABLEB Inverted CRC Enable. This must be written with the inverted value of the CRC_ENABLE. Status bits are set to 1 to indicate an active condition. They may be cleared by writing a 1 to the corresponding bit location. Table 25. Bit Descriptions for INTERFACE_STATUS_A transaction before the completion of digital initialization. device calculates and checks the CRC and finds the CRC value is incorrect.
Table 25. Bit Descriptions for INTERFACE_STATUS_A (Continued) strict register access is enabled. Table 26. Bit Descriptions for OUTPUT_OPERATING_MODE_0 01: Powered down: 1 kOhm output impedance. 10: Powered down: 7.7 kOhm output impedance. 11: Powered down: 32 kOhm output impedance. 01: Powered down: 1 kOhm output impedance. 10: Powered down: 7.7 kOhm output impedance. 11: Powered down: 32 kOhm output impedance. 01: Powered down: 1 kOhm output impedance. 10: Powered down: 7.7 kOhm output impedance. 11: Powered down: 32 kOhm output impedance. 01: Powered down: 1 kOhm output impedance. 10: Powered down: 7.7 kOhm output impedance. 11: Powered down: 32 kOhm output impedance.
Table 27. Bit Descriptions for OUTPUT_OPERATING_MODE_1 01: Powered down: 1kΩ output impedance. 10: Powered down: 7.7kΩ output impedance. 11: Powered down: 32kΩ output impedance. 01: Powered down: 1kΩ output impedance. 10: Powered down: 7.7kΩ output impedance. 11: Powered down: 32kΩ output impedance. 01: Powered down: 1kΩ output impedance. 10: Powered down: 7.7kΩ output impedance. 11: Powered down: 32kΩ output impedance. 01: Powered down: 1kΩ output impedance. 10: Powered down: 7.7kΩ output impedance. 11: Powered down: 32kΩ output impedance. Table 28. Bit Descriptions for OUTPUT_CONTROL_0 0: Range 0. Output will range from 0V to VREF. 1: Range 1. Output will range from 0V to 2 × VREF.
Table 29. Bit Descriptions for REFERENCE_CONTROL_0 0: Select 0. VREF pin is an input pin, and an external reference should be provided through this pin. Table 30. Bit Descriptions for MUX_OUT_SELECT_0 0x0: Powered down. MUX_OUT pin is powered down. An 80kΩ impedance can be seen at the MUX_OUT pin. 0x1: VOUT0. A voltage representation of VOUT0 can monitored on MUX_OUT pin. 0x2: IOUT0 (source mode). A voltage representation of IOUT0 (source mode) can monitored on MUX_OUT pin. 0x3: IOUT0 (sink mode). A voltage representation of IOUT0 (sink mode) can monitored on MUX_OUT pin. 0x4: VOUT1. A voltage representation of VOUT1 can monitored on MUX_OUT pin. 0x5: IOUT1 (source mode). A voltage representation of IOUT1 (source mode) can monitored on MUX_OUT pin. 0x6: IOUT1 (sink mode). A voltage representation of IOUT1 (sink mode) can monitored on MUX_OUT pin. 0x7: VOUT2. A voltage representation of VOUT2 can monitored on MUX_OUT pin. 0x8: IOUT2 (source mode). A voltage representation of IOUT2 (source mode) can monitored on MUX_OUT pin. 0x9: IOUT2 (sink mode). A voltage representation of IOUT2 (sink mode) can monitored on MUX_OUT pin. 0xA: VOUT3. A voltage representation of VOUT3 can monitored on MUX_OUT pin. 0xB: IOUT3 (source mode). A voltage representation of IOUT3 (source mode) can monitored on MUX_OUT pin. 0xC: IOUT3 (sink mode). A voltage representation of IOUT3 (sink mode) can monitored on MUX_OUT pin. 0xD: VOUT4. A voltage representation of VOUT4 can monitored on MUX_OUT pin. 0xE: IOUT4 (source mode). A voltage representation of IOUT4 (source mode) can monitored on MUX_OUT pin. 0xF: IOUT4 (sink mode). A voltage representation of IOUT4 (sink mode) can monitored on MUX_OUT pin. 0x10: VOUT5. A voltage representation of VOUT5 can monitored on MUX_OUT pin. 0x11: IOUT5 (source mode). A voltage representation of IOUT5 (source mode) can monitored on MUX_OUT pin. 0x12: IOUT5 (sink mode). A voltage representation of IOUT5 (sink mode) can monitored on MUX_OUT pin. 0x13: VOUT6. A voltage representation of VOUT6 can monitored on MUX_OUT pin. 0x14: IOUT6 (source mode). A voltage representation of IOUT6 (source mode) can monitored on MUX_OUT pin. 0x15: IOUT6 (sink mode). A voltage representation of IOUT6 (sink mode) can monitored on MUX_OUT pin. 0x16: VOUT7. A voltage representation of VOUT7 can monitored on MUX_OUT pin. 0x17: IOUT7 (source mode). A voltage representation of IOUT7 (source mode) can monitored on MUX_OUT pin. 0x18: IOUT7 (sink mode). A voltage representation of IOUT7 (sink mode) can monitored on MUX_OUT pin. 0x19: Die temperature. A voltage representation of internal die temperature can monitored on MUX_OUT pin. 0x1A: AGND. MUX_OUT pin internally tied to AGND.
Event flags due to start up sequence, interface, reset, and update can be read. Write 1 to clear. Table 31. Bit Descriptions for STATUS_CONTROL
3 UPDATE_ERR
0: Error 0. All updates successful. 1: Error 1. Overlapping updates attempted. 0: Warning 0. Reset warning flag cleared. 1: Warning 1. Reset event occurred. 0: Error 0. No interface error. 1: Error 1. Interface error. Table 32. Bit Descriptions for HW_LDAC_EN_0 0: HLD En 0. Disable hardware LDAC on Channel 7. 1: HLD En 1. Enable hardware LDAC on Channel 7. 0: HLD En 0. Disable hardware LDAC on Channel 6. 1: HLD En 1. Enable hardware LDAC on Channel 6. 0: HLD En 0. Disable hardware LDAC on Channel 5. 1: HLD En 1. Enable hardware LDAC on Channel 5. 0: HLD En 0. Disable hardware LDAC on Channel 4.
Table 32. Bit Descriptions for HW_LDAC_EN_0 (Continued) 1: HLD En1. Enable hardware LDAC on Channel 4. 0: HLD En 0. Disable hardware LDAC on Channel 3. 1: HLD En 1. Enable hardware LDAC on Channel 3. 0: HLD En 0. Disable hardware LDAC on Channel 2. 1: HLD En 1. Enable hardware LDAC on Channel 2. 0: HLD En 0. Disable hardware LDAC on Channel 1. 1: HLD En 1. Enable hardware LDAC on Channel 1. 0: HLD En 0. Disable hardware LDAC on Channel 0. 1: HLD En 1. Enable hardware LDAC on Channel 0. Table 33. Bit Descriptions for SW_LDAC_EN_0 0: SLD En 0. Disable software LDAC on Channel 7. 1: SLD En 1. Enable software LDAC on Channel 7. 0: SLD En 0. Disable software LDAC on Channel 6. 1: SLD En 1. Enable software LDAC on Channel 6. 0: SLD En 0. Disable software LDAC on Channel 5. 1: SLD En 1. Enable software LDAC on Channel 5. 0: SLD En 0. Disable software LDAC on Channel 4. 1: SLD En 1. Enable software LDAC on Channel 4. 0: SLD En 0. Disable software LDAC on Channel 3. 1: SLD En 1. Enable software LDAC on Channel 3. 0: SLD En 0. Disable software LDAC on Channel 2. 1: SLD En 1. Enable software LDAC on Channel 2. 0: SLD En 0. Disable software LDAC on Channel 1. 1: SLD En 1. Enable software LDAC on Channel 1.
Table 33. Bit Descriptions for SW_LDAC_EN_0 (Continued) 0: SLD En 0. Disable software LDAC on Channel 0. 1: SLD En 1. Enable software LDAC on Channel 0. 16-bit data defines the voltage of VOUTn pin, where n is the channel number. Table 34. Bit Descriptions for DAC_CHn Data written to this register also writes all DAC_CHn selected in MULTI_DAC_SEL_0. Table 35. Bit Descriptions for MULTI_DAC_CH return the latest data written. Select which DAC_CHn will be written when a write operation is executed on MULTI_DAC_CH. Only applies DAC_CH0 to DAC_CH7.
Table 36. Bit Descriptions for MULTI_DAC_SEL_0 same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH7. 0: MD Sel 0. Deselect DAC_CH7 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH7 for MULTI_DAC_CH operation. same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH6. 0: MD Sel 0. Deselect DAC_CH6 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH6 for MULTI_DAC_CH operation. same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH5. 0: MD Sel 0. Deselect DAC_CH5 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH5 for MULTI_DAC_CH operation. same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH4. 0: MD Sel 0. Deselect DAC_CH4 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH4 for MULTI_DAC_CH operation. same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH3. 0: MD Sel 0. Deselect DAC_CH3 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH3 for MULTI_DAC_CH operation. same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH2. 0: MD Sel 0. Deselect DAC_CH2 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH2 for MULTI_DAC_CH operation. same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH1. 0: MD Sel 0. Deselect DAC_CH1 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH1 for MULTI_DAC_CH operation. same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH0. 0: MD Sel 0. Deselect DAC_CH0 for MULTI_DAC_CH operation. 1: MD Sel 1. Select DAC_CH0 for MULTI_DAC_CH operation. Initiates transfer of INPUT_CHn to DAC_CHn. Only takes effect on enabled channels identified by SW_LDAC_EN_0.
Table 37. Bit Descriptions for SW_LDAC_TRIG_A number as enabled by SW_LDAC_EN_0. Writing 0 will have no effect. Table 38. Bit Descriptions for MULTI_INPUT_CH Select which INPUT_CHn will be written when a write operation is executed on MULTI_INPUT_CH. Only applies INPUT_CH0 to INPUT_CH7. Table 39. Bit Descriptions for MULTI_INPUT_SEL_0 the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH7. 0: MI Sel 0. Deselect INPUT_CH7 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH7 for MULTI_INPUT_CH operation. the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH6. 0: MI Sel 0. Deselect INPUT_CH6 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH6 for MULTI_INPUT_CH operation. the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH5. 0: MI Sel 0. Deselect INPUT_CH5 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH5 for MULTI_INPUT_CH operation. the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH4. 0: MI Sel 0. Deselect INPUT_CH4 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH4 for MULTI_INPUT_CH operation. the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH3.
Table 39. Bit Descriptions for MULTI_INPUT_SEL_0 (Continued) 0: MI Sel 0. Deselect INPUT_CH3 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH3 for MULTI_INPUT_CH operation. the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH2. 0: MI Sel 0. Deselect INPUT_CH2 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH2 for MULTI_INPUT_CH operation. the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH1. 0: MI Sel 0. Deselect INPUT_CH1 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH1 for MULTI_INPUT_CH operation. the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH0. 0: MI Sel 0. Deselect INPUT_CH0 for MULTI_INPUT_CH operation. 1: MI Sel 1. Select INPUT_CH0 for MULTI_INPUT_CH operation. Table 40. Bit Descriptions for SW_LDAC_TRIG_0 as enabled by SW_LDAC_EN_0. Writing 0 has no effect. Table 41. Bit Descriptions for INPUT_CHn
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1.60 REF
Figure 77. 25-Ball Wafer Level Chip Scale Package [WLCSP]