EVAL-AD1871EBZ

EVAL-AD1871EBZ AD | Alldatasheet

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD1871 REV. 0 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Stereo Audio, 24-Bit, 96 kHz, Multibit /H9018-/H9004 ADC FUNCTIONAL BLOCK DIAGRAM DATA PORT MCLK RESET CLATCH/(M/S) CCLK/(256/512) CIN/(DF1) FILTER ENGINEAD1871 LRCLK BCLK DOUT DIN COUT/(DF0) CASC XCTRL MULTIBIT /H9018-/H9004 MODULATOR ANALOG INPUT BUFFER DECIMATOR MULTIBIT /H9018-/H9004 MODULATOR ANALOG INPUT BUFFER DECIMATOR SPI PORT CLOCK DIVIDER VINLP VINLN VREF VINRP VINRN CAPLN CAPLP AVDD DVDD ODVDD CAPRN CAPRP AGND DGND

FEATURES

5.0 V Stereo Audio ADC

with 3.3 V Tolerant Digital Interface Supports 96 kHz Sample Rates Supports 16-/20-/24-Bit Word Lengths Multibit Sigma-Delta Modulators with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor 105 dB (Typ) Dynamic Range Supports 256/512 and 768 /H11547 f S Master Clocks Flexible Serial Data Port Allows Right-Justified, Left-Justified, I 2S Compatible and DSP Serial Port Modes Cascadable (up to Four Devices) from a Single DSP SPORT Device Control via SPI Compatible Serial Port or Optional Control Pins On-Chip Reference 28-Lead SSOP Package

APPLICATIONS

Digital Audio Recorders, Including CD-R, MD, DVD-R, DAT, HDD Home Theater Systems Automotive Audio Systems Multimedia PRODUCT OVERVIEW The AD1871 is a stereo audio ADC intended for digital audio applications requiring high performance analog-to-digital conversion. It features two 24-bit conversion channels each with programmable gain amplifier (PGA), multibit sigma-delta modulator, and decimation filters. Each channel provides 105 db of dynamic range, making the AD1871 suitable for applications such as digital audio recorders and m ixing consoles. Each of the AD1871’s input channels (left and right) can be configured as either differential or single-ended (two inputs muxed with internal single-ended-to-differential conversion). The input PGA features a gain range of 0 dB to 12 dB in steps of 3 dB. The Σ-∆ modulator features a proprietary multibit architecture that realizes optimum performance over an audio bandwidth with standard audio sampling rates of 32 kHz up to 96 kHz. The decimation filter response features very low pass- band ripple and excellent stop-band attenuation. The AD1871’s audio data interface supports all common interface formats such as I 2S, left-justified, right-justified as well as other modes that allow for convenient connection to general-purpose digital signal processors (DSPs). The AD1871 also features an SPI compatible serial control port that allows for convenient control of device parameters and functionality such as sample word-width, PGA settings, interface modes, and so on. The AD1871 operates from a single 5 V power supply—with an optional digital interfacing capability of 3.3 V. It is housed in a 28-lead SSOP package and is characterized for operation over the temperature range –40 °C to +105°C.

–2– REV. 0 TABLE OF CONTENTS

REV. 0 –3– AD1871–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Input Voltage High (V Master Mode, Data I2S Justified ANALOG PERFORMANCE Parameter Min Typ Max Unit Conditions RESOLUTION 24 Bits DIFFERENTIAL INPUT PGA/MUX Enabled Dynamic Range (20 Hz to 20 kHz, –60 dB Input) Unweighted 98 103 dB A-Weighted 100 105 dB Signal-to-Noise Ratio 106 dB Total Harmonic Distortion + Noise –85 dB Input = –0.5 dBFS (THD+N) –103 dB Input = –20 dBFS Multibit Modulator Only Modulator Output @ 5.6448 MHz Dynamic Range (A-Weighted) 102 dB SINGLE-ENDED INPUT PGA/MUX Enabled Dynamic Range (20 Hz to 20 kHz, –60 dB Input) Unweighted 103 dB A-Weighted 105 dB Signal-to-Noise Ratio 106 dB Total Harmonic Distortion + Noise –85 dB Input = –0.5 dBFS (THD+N) –103 dB Input = –20 dBFS DIFFERENTIAL INPUT (BYPASS) PGA/MUX Disabled Dynamic Range (20 Hz to 20 kHz, –60 dB Input) Unweighted 103 dB A-Weighted 106 dB Signal-to-Noise Ratio 106 dB Total Harmonic Distortion + Noise –86 dB Input = –0.5 dBFS (THD+N) –104 dB Input = –20 dBFS DIFFERENTIAL INPUT (fS = 96 kHz) PGA/MUX Enabled; AMC = 1 Dynamic Range (20 Hz to 20 kHz, –60 dB Input) Unweighted 103 dB A-Weighted 106 dB Signal-to-Noise Ratio 106 dB Total Harmonic Distortion + Noise –87 dB Input = –0.5 dBFS (THD+N) –104 dB Input = –20 dBFS Analog Inputs Differential Input Range ( ± Full Scale) –2.828 +2.828 V Input Impedance (PGA/MUX) 8 k W Differential Input Impedance (ByPass) 40 k W Differential Input Impedance (PGA/MUX) 4 k W Single Ended VREF 2.138 2.25 2.363 V DC Accuracy Gain Error –10 % Interchannel Gain Mismatch –0.2 –0.01 +0.2 dB Gain Drift 100 ppm/ ∞C Crosstalk (EIAJ Method) –100 dB

Figure 1. MCLK/ RESET Timing

Figure 2. Master Data Interface Timing

Figure 3. Slave Data Interface Timing

Figure 7. Control Interface Timing Specifications subject to change without notice.

REV. 0 AD1871 –9– ABSOLUTE MAXIMUM RATINGS Min Typ Max Unit DVDD to DGND and ODVDD to DGND 0 6 V AVDD to AGND 0 6 V Digital Inputs DGND – 0.3 DVDD + 0.3 V Analog Inputs AGND – 0.3 AVDD + 0.3 V AGND to DGND –0.3 +0.3 V Reference Voltage Indefinite Short Circuit to Ground Soldering (10 sec) 300 ∞C ORDERING GUIDE Package Package Model Temperature Description Option AD1871YRS –40 ∞C to +105∞C SSOP RS-28 AD1871YRS-REEL –40 ∞C to +105∞C SSOP RS-28 in 13 ” Reel (1500 pieces) EVAL-AD1871EB Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1871 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATION TOP VIEW (Not to Scale) AD1871 VREF CAPLP CAPLN VINLP VINLN AVDD XCTRL MCLK CCLK/( 256/512) COUT/(DF0) CIN/(DF1) DGND DVDD CLATCH/(M/S) AGND CAPRP CAPRN VINRP VINRN AGND CASC LRCLK BCLK DOUT DIN DGND ODVDD RESET

–10– REV. 0 PIN FUNCTION DESCRIPTIONS Pin Input/ No. Output Mnemonic Description 1I MCLK Master Clock. The master clock input determines the sample rate of the device. MCLK can be 256, 512, or 768 times the sampling frequency. 2I CCLK1 Control Port Bit Clock—clock signal for control port (SPI) interface. This pin is recon- figured in the External Control Mode (Pin XCTRL is high), see below. 3 I/O COUT 1, 2 Control Port Data Out—serial data output from the control port (SPI) interface (in read- back). This pin is reconfigured in the External Control Mode (Pin XCTRL is high), see below; or in Modulator Mode (Bit MME of Control Register II is set), see below. 4I CIN 1 Control Port Data Input—serial data input for control port (SPI) interface. This pin is reconfigured in the External Control Mode (Pin XCTRL is high), see below. 5I CLATCH 1 Control Port Frame Sync—frame sync (framing signal) for control port (SPI) interface. This pin is reconfigured in the External Control Mode (Pin XCTRL is high), see below. 6I DVDD 5 V Digital Core Supply 7I DGND Digital Ground 8I XCTRL External Control Enable. This pin is used to select the Control Mode for the device. When XCTRL is low, control is via the SPI compatible control port (Pins CCLK, CLATCH, CIN, and COUT). When XCTRL is enabled (high), control of several device functions is possible by hardware pin strapping (Pins 256/512, M/S, DF1, and DF0). In External Control Mode, all other functions are in default state (please refer to the Control Register Descriptions and External Control section). 9I AVDD 5 V Analog Supply

10 I VINLN Left Channel, Negative Input (via MUX/PGA)

11 I VINLP Left Channel, Positive Input (via MUX/PGA)

12 I/O CAPLN Left External Filter Capacitor (Negative Input to Modulator)

13 I/O CAPLP Left External Filter Capacitor (Positive Input to Modulator)

14 O VREF

Reference Voltage Output. It is recommended to connect a capacitor combination of 10 mF in parallel with 0.1 mF between VREF and AGND (Pin 15). (See Layout Recommendations.)

15 I AGND Analog Ground

16 I/O CAPRP Right External Filter Capacitor (Positive Input to Modulator)

17 I/O CAPRN Right External Filter Capacitor (Negative Input to Modulator)

18 I VINRP Right Channel, Positive Input (via MUX/PGA)

19 I VINRN Right Channel, Negative Input (via MUX/PGA)

20 I AGND Analog Ground

21 I CASC Cascade Enable. This pin enables cascading of up to four AD1871 devices to a single DSP serial port (see Cascading section).

22 I DGND Digital Ground

23 I ODVDD

Digital Interface Supply. The digital interface can operate from 3.3 V to 5.0 V (nominal).

24 I RESET Reset

25 I/O DIN 2 Serial Data Input. Serial data input pin, only valid when the device is configured in Cas- cade Mode (Pin CASC is high). This pin is reconfigured in Modulator Mode (Bit MME of Control Register II is set), see below.

26 O DOUT

2 Audio Serial Data Output. This pin is reconfigured in Modulator Mode (Bit MME of Control Register II is set), see below.

27 I/O BCLK

2 Audio Serial Bit Clock. The bit clock is the audio data serial clock and determines the rate of audio data transfer. This pin is reconfigured in Modulator Mode (Bit MME of Control Register II is set), see below. 28 I/O LRCLK 2 Left/Right Clock. This clock, also known as the word clock, determines the sampling rate. It is an output or input depending on the status of Master/Slave. This pin is reconfigured in Modulator Mode (Bit MME of Control Register II is set), see below. NOTES 1External Control Mode (See pg 11) 2Modulator Mode (See pg 11)

REV. 0 AD1871 –11– Pin Function Redefinition in External Control Mode Pin Input/ No. Output Mnemonic Description 2I 256/512 Clock Rate Select. This pin is used to select between an MCLK of 256 /H11003 fS (pin low) or 512 /H11003 fS (pin high). 3I DF0 Data Format Select 0. This pin is used as the low bit (DF0) of the data format selection (see section on External Control). 4I DF1 Data Format Select 1. This pin is used as the high bit (DF1) of the data format selection (see section on External Control). 5I M/S Master/Slave Select. This pin is used to select between the Master (pin low) or Slave (pin high) Modes. Pin Function Redefinition in Modulator Mode Pin Input/ No. Output Mnemonic Description 3O MODCLK This pin provides a clock output that allows the user to decode the left and right channel modulator outputs. It is similar to a left/right clock but runs (nominally) at 5.6448 MHz and gates a 4-bit modulator output word in each phase (see section on Modulator Mode).

25 O D3 Bit 3 of the Modulator Output Word

26 O D2 Bit 2 of the Modulator Output Word

27 O D1 Bit 1 of the Modulator Output Word

28 O D0 Bit 0 of the Modulator Output Word

–12– REV. 0 TERMINOLOGY Dynamic Range The ratio of a full-scale input signal to the integrated input noise in the pass band (20 Hz to 20 kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and is equal to (S/[THD+N]) + 60 dB. Note that spurious harmonics are below the noise with a –60 dB input, so the noise level establishes the dynamic range. The dynamic range is specified with and without an A-Weight filter applied. Signal to (Total Harmonic Distortion + Noise) (S/[THD+N]) The ratio of the root-mean-square (rms) value of the fundamen- tal input signal to the rms sum of all other spectral components in the pass band, expressed in decibels (dB). Pass Band The region of the frequency spectrum unaffected by the attenu- ation of the digital decimator’s filter. Pass-Band Ripple The peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. Stop Band The region of the frequency spectrum attenuated by the digital decimator’s filter to the degree specified by stop-band attenuation. Gain Error With a near full-scale input, the ratio of the actual output to the expected output, expressed as a percentage. Interchannel Gain Mismatch With identical near full-scale inputs, the ratio of the outputs of the two stereo channels, expressed in decibels. Gain Drift Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per ∞C. Crosstalk (EIAJ Method) Ratio of response on one channel with a grounded input to a full-scale 1 kHz sine-wave input on the other channel, expressed in decibels. Power Supply Rejection With no analog input, signal present at the output when a 300 mV p-p signal is applied to power supply pins, expressed in decibels of full scale. Group Delay Intuitively, the time interval required for an input pulse to appear at the converter’s output, expressed in milliseconds (ms). More precisely, the derivative of radian phase with respect to radian frequency at a given frequency. GLOSSARY ADC—Analog-to-Digital Converter DSP—Digital Signal Processor IMCLK—Internal master clock signal, used to clock the deci- mating filter section. (Its frequency must be 256 ¥ f S.) MCLK—External master clock signal applied to the AD1871. Its frequency can be 256, 512, or 768 ¥ fS. MCLK is divided internally to give an IMCLK frequency that must be 256 ¥ fS. MODCLK—This is the /H9018-/H9004 modulator clock that determines the sample rate of the modulator. Ideally, it should not exceed the lower of 6.144 MHz or 128 ¥ f S. The MODCLK is derived from the IMCLK by a divider that can be selected as /2 or /4. MUX—Multiplexer PGA—Programmable Gain Amplifier

REV. 0 –13–REV. 0 Typical Performance Characteristics–AD1871 FILTER RESPONSES FREQUENCY – NORMALIZED TO fS –20 –160 01 5 5 MAGNITUDE – dB –80 –100 –120 –140 –40 –60 TPC 1. Sinc Filter Response (AMC = 0) FREQUENCY – NORMALIZED TO fS –20 –160 01 5 5 MAGNITUDE – dB –80 –100 –120 –140 –40 –60 TPC 2. First Half-Band Filter Response FREQUENCY – NORMALIZED TO fS –20 –160 01 5 5 MAGNITUDE – dB –80 –100 –120 –140 –40 –60 TPC 3. Comb Compensation Filter Response FREQUENCY – NORMALIZED TO fS –20 –160 01 5 5 MAGNITUDE – dB –80 –100 –120 –140 –40 –60 TPC 4. Second Half-Band Filter Response FREQUENCY – NORMALIZED TO fS MAGNITUDE – dB –50 –100 –150 51 01 5 TPC 5. Composite Filter Response (AMC = 0) FREQUENCY – NORMALIZED TO fS MAGNITUDE – dB –50 –100 –150 0.5 1.0 1.5 2.0 TPC 6. Composite Filter Response (Pass Band Section) (AMC = 0)

–14– REV. 0 DEVICE PERFORMANCE CURVES FREQUENCY – Hz –10 –15 –20 –25 –30 51 0 1 5 2 0 MAGNITUDE – dB TPC 7. High-Pass Filter Response, f S = 48 kHz FREQUENCY – Hz MAGNITUDE – dB –10 –15 –20 –25 –30 51 0 1 5 2 0 TPC 8. High-Pass Filter Response, f S = 96 kHz kHz –60 –120 –20 –40 –80 –100 –140 –160 –180 202 dBFS 468 1 0 1 2 14 16 18 TPC 9. 1 kHz Tone at –0.5 dBFS, (32 k-Point FFT), f S = 48 kHz kHz –60 –120 –20 –40 –80 –100 –140 –160 –180 202 dBFS 468 1 0 12 14 16 18 TPC 10. 1 kHz Tone at –20 dBFS, (32 k-Point FFT), f S = 48 kHz kHz –60 –120 –20 –40 –80 –100 –140 –160 –180 202 dBFS 468 1 0 1 2 1 41 61 8 TPC 11. 1 kHz Tone at –60 dBFS, (32 k-Point FFT), fS = 48 kHz dBr –40 –70 –20 –30 –50 –60 –80 –90 –100 dB TPC 12. THD+N vs. Input Amplitude at 1 kHz, f S = 48 kHz

REV. 0 AD1871 –15– kHz –70 –60 –80 –90 –100 –110 202 dBFS 468 1 0 1 2 1 41 61 8 TPC 13. THD+N vs. Input Frequency at –0.5 dBFS, f S = 48 kHz kHz –90 –105 –120 202 dB 468 1 0 12 14 16 18 –95 –100 –110 –115 TPC 14. Channel Separation vs. Frequency at –0.5 dBFS, f S = 48 kHz FREQUENCY–MHz dB –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 TPC 15. FFT of Modulator Output at –0.5 dBFS, f S = 6.144 MHz

trolled using the MCD1–MCD0 Bits of Control Register III. Figure 8. Clocking Scheme to Modulator and Filter Engine feedback to the two integrator stages.

12.288 MHz, the default divider setting (/2) gives a modulator clock

from the normalized frequency response plot shown in TPC 6. Figure 9. Modulator Block Diagram

0000 Control Register I

0001 Control Register II

0010 Control Register III

0011 Peak Reading Register I

0100 Peak Reading Register II

Figure 18. Cascade Mode Data Interface Timing Figure 19. Cascade Mode Control Port Timing

Figure 20. Writing to Register Using Control Port Figure 21. Reading from Register Using Control Port

9 PRE Peak Reading Enable (0 = Disabled (Default); 1 = Enabled)

8 HPE High-Pass Filter Enable (0 = Disabled (Default); 1 = Enabled)

6 AMC ADC Modulator Clock (1 = 64 ¥ fS; 0 = 128 ¥ fS (Default))

high-pass filtering, and peak hold. giving five separate and independent gain settings on each channel. sponding to the bit settings in AG x2–ADx0.

–22– REV. 0 Table VI. Control Register II (Address 0001b) 15–12 11 10 9 876 5 43 21 0 0001 0 0 MME DF1 DF0 WW1 WW0 M/S MUR MUL 9–8 Reserved

7 MME Modulator Mode Enable (0 = Normal Mode (Default), 1 = Mod Mode)

6–5 DF1–DF0 Data Format (See Table VIII) 4–3 WW1–WW0 Word Width (See Table VII)

2 M/S Master/Slave Select (0 = Master Mode (Default); 1 = Slave Mode)

1 MUR Mute Control, Right Channel (0 = Disabled (Default); 1 = Enabled)

0 MUL Mute Control, Left Channel (0 = Disabled (Default); 1 = Enabled)

Table VII. Word-Width Settings WW1 WW0 Word Width (No. of Bits) 00 24 (Default) 01 2 0 10 1 6

11 Reserved

The AD1871’s serial data interface can be configured from a choice of popular interface formats, including I 2S, left-justified, right-justified, or DSP Modes. Bits DF1–DF0 are programmed to select the interface format (mode) as shown in Table VIII. Table VIII. Data Interface Format Settings * DF1 DF0 Interface Mode 00I 2S (Default)

01 Right-Justified

10 DSP

11 Left-Justified

*Please refer to the Serial Data Interface section in the Functional Description for more details on the various interface modes. Modulator Mode Enable The AD1871 defaults to the conversion of the analog audio to linear, PCM-encoded digital outputs. Modulator Mode allows the user to bypass the digital decimation filter section and access the multibit sigma-delta modulator outputs directly. When in this mode, certain pins are redefined (see Modulator Mode) and the modulator output (at a nominal rate of 128 /H11003 f S) is available on the modulator data pins (D[0–3]). To enable the Modu- lator Mode, set the MME Bit to high. Modulator Clock The modulator clock can be chosen to be either 128 ¥ fS or 64 ¥ fS. The AMC Bit (Bit 6) is used to select the modulator’s clock rate. When AMC is set to 0 (default), the modulator clock is 128 ¥ fS. Otherwise, if set to 1, the modulator clock is 64 ¥ fS. This bit is normally set depending on whether the desired sampling frequency is 48 kHz or 96 kHz and is also influenced by the selected MCLK frequency. Please refer to the Functional Description section for more information on MCLK selection and sampling rates. Power-Down Power-down of the active clock signals within the AD1871 is effected by writing a Logic 1 to Bit 7 (PD). In Power-Down Mode, digital activity is suspended and analog sections are powered down, with the exception of the reference. High-Pass Filter The AD1871’s digital filtering engine allows the insertion of a high-pass filter (HPF) to effectively block dc signals from the output digital waveform. Setting Bit 8 (HPE) enables the high-pass filter. For more details of the HPF, refer to the Functional Description section. Peak Reading Enable The AD1871 has two readback registers that can be enabled to store the peak readings of the left and right channel ADC results. To enable the peak readings to be captured, the Peak Reading Enable Bit (PRE), Bit 9, must be set to Logic 1. When set to Logic 0, the peak reading capture is disabled. Control Register II Control Register II contains bit settings for control of left/right channel muting, data sample word width, data interface format, and direct modulator bitstream output. Mute Control The left and right data channels can be muted to digital zero by setting the MUL and MUR Bits (Bits 0 and 1), respectively. If a channel is muted, its output data stream will remain at digital zero, regardless of the amplitude of the input signal. Setting the bit to 1 mutes the channel while setting the bit to 0 restores normal operation. Master/Slave Select The AD1871 can operate as either a slave device or a master device. In Slave Mode, the controller must provide the LRCLK and BCLK to determine the sample rate and serial bit rate. In Master Mode, the AD1871 provides the LRCLK and BCLK as outputs that are applied to the controller. The AD1871 defaults to Master Mode (M/S is low) on reset. Word Width The AD1871 allows the output sample word width to be selected from 16, 20, and 24 bits wide. Compact disc (CD) compatibility may require 16 bits, while many modern digital audio formats require 24-bit sample resolution. Bits WW1–WW0 are programmed to select the word width. Table VII details the Control Register Bit settings corresponding to the various word width selections.

REV. 0 AD1871 –23– Single-Ended Mode Enable The Single-Ended Mode Enable Bits (SEL and SER for left and right channels, respectively), when set to 1, are used to configure single-ended input on VINxP and VINxN (input is selected by state of MXL and MXR). In this mode, single-ended inputs taken from either VINxP or VINxN (selected using the Mux Select Bits—MXL and MXR) are internally converted to a differential format to be applied to the modulator section (see Table XII). Table XII. Differential/Single-Ended Select SEL SER Input Setting 0X Left Channel Input Æ Differential 1X Left Channel Input Æ Single-Ended X0 Right Channel Input Æ Differential X1 Right Channel Input Æ Single-Ended Master Clock Divider The master clock divider allows the division of the external MCLK frequency to a more suitable internal master clock frequency (IMCLK). IMCLK must be 256 ¥ f S; therefore, if the available MCLK is not at 256 ¥ fS but is a multiple of this, the MCD allows conversion of MCLK to a suitable IMCLK at 256 ¥ fS (see Table XIII). Table XIII. Master Clock Divider Settings MCD1 MCD0 MCLK Division

00 IMCLK = MCLK (/1)

01 IMCLK = MCLK/2

10 IMCLK = MCLK/3

11 IMCLK = MCLK (/1)

Table IX. Control Register III (Address 0010b) 15–12 11 10 9 8 7 6 5 4 3 2 1 0 0010 0 0 MCD1 MCD0 SEL SER MEL MXL MER MXR 9–8 Reserved (Should Be Programmed to 0) 7–6 MCD1–MCD0 Master Clock Divider (See Table XIII)

5 SEL Single-Ended Enable, Left Channel (0 = Differential

(Default); 1 = Single-Ended)

4 SER Single-Ended Enable, Right Channel (0 = Differential (Default); 1 = Single-Ended)

3 MEL Mux/PGA Disable, Left Channel (0 = Enabled (Default); 1 = Disabled)

2 MXL Mux Select, Left Channel (0 = VINLP Selected (Default); 1 = VINLN Selected)

1 MER Mux/PGA Disable, Right Channel (0 = Enabled (Default); 1 = Disabled)

0 MXR Mux Select, Right Channel (0 = VINRP Selected (Default); 1 = VINRN Selected)

Control Register III contains bit settings for configuration of the analog input section (both left and right channels). Mux Enable The Mux Enable Left (MEL) and Mux Enable Right (MER) are used to enable the analog buffers. When these bits are set to 1, the analog input buffers are powered down and input signals must be applied directly to the modulator inputs via the CAPxP and CAPxN pins. (see Figure 23). When MEL and MER are set to 0 (default condition after reset), the analog input section is enabled, (see Table X). Table X. Mux Control Settings MEL MER Input Setting 0X Left Channel Analog Buffer Enabled 1X Left Channel Analog Buffer Disabled X0 Right Channel Analog Buffer Enabled X1 Right Channel Analog Buffer Disabled Mux Select The Mux Select Bits (MXL and MXR for left and right channels, respectively) are used to select the input from VINxP or VINxN when the input is configured as single-ended. When MXx is set to 0, the input is taken from VINxP. When MXx is set to 1, the input is taken from VINxN, (see Table XI). Table XI. Mux Select Settings * MXL MXR Input Setting 0X Left Channel Input from VINLP 1X Left Channel Input from VINLN X0 Right Channel Input from VINRP X1 Right Channel Input from VINRN *Mux select settings are only valid when single-ended operation is enabled; SEL and SER are set to 1.

reading per channel is stored in the appropriate peak register. updated by subsequent conversions. A Peak Reading Register read cycle is detailed in Figure 21. Pin high as shown in Figure 22. Figure 22. External Control Configuration and BCLK signals are outputs from the AD1871. LRCK and BCLK signals are inputs to the AD1871. pin is set high, the device operates with an MCLK that is 512 ¥ fS. Control Register II. See Table VIII. (see Modulator Mode Timing in Figure 6). S and generates a single-bit output steam.

REV. 0 AD1871 –27– OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 0.25 0.09 0.95 0.75 0.55 8/H11543 4/H11543 0/H11543 0.05 MIN 1.85 1.75 1.65

2.00 MAX

0.38 0.22 SEATING PLANE 0.65 BSC 0.10 COPLANARITY 28 15 141 10.50 10.20 9.90 PIN 1 5.60 5.30 5.00 8.20 7.80 7.40 COMPLIANT TO JEDEC STANDARDS MO-150AH

–28– C02644–0–8/02(0) PRINTED IN U.S.A.