EVAL-2ED3146MC12L-SIC

2ED314XMC12L INFINEON | Alldatasheet

Document overview

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Technical content

Features

• Dual-channel isolated gate driver
• For use with 600 V/650 V/1200 V/1700 V/2300 V IGBTs, Si and SiC MOSFETs
• Up to 6.5 A typical peak output current
• 39 ns propagation delay with 5 ns channel-to-channel delay mismatch (skew)
• 35 V absolute maximum output supply voltage
• High common-mode transient immunity CMTI > 200 kV/µs
• Active shutdown and short circuit clamping
• Galvanically isolated coreless transformer gate driver
• 3.3 V and 5 V input supply voltage
• 8 mm input-to-output and 3.3 mm channel-to-channel creepage and clearance
• Safety certification - UL 1577 (File 311313) with VISO,test = 6840 V (rms) for 1 s, VISO = 5700 V (rms) for 60 s - Reinforced insulation according to IEC 60747-17 (planned) with VIORM = 1767 V (peak) Potential applications
• EV charging
• Energy storage systems
• Solar inverters
• Server and telecom switched mode power supplies (SMPS)
• UPS-systems
• AC and brushless DC motor drives
• Commercial air-conditioning (CAC)
• High voltage DC-DC converter and DC-AC inverter Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.

Description

The EiceDRIVER™ 2ED314xMC12L is a family of dual-channel isolated gate driver ICs, designed to drive Si MOSFETs, IGBTs and SiC MOSFETs. All products are available in a 14-pin DSO package with 8 mm input-to-output creepage and provide reinforced isolation. All variants offer dead-time control (DTC) functionality and independent channel operation. This allows the operation as dual-channel low-side driver, dual-channel high-side driver or half-bridge gate driver with a configurable dead-time. With excellent common-mode transient immunity (CMTI), low part-to-part propagation delay mismatch and fast signal propagation, the products are best suited for use in fast-switching applications. Logic input Floating Gate Driver ChA Floating Gate Driver ChB Input to output reinforced isolation Channel to channel functional isolation INA INB VCC1 GND1 DIS/EN DT N.C. VCC1 VCC2A OUTA VEE2A VCC2B OUTB VEE2B PWM1 PWM2 VDD GPIOx LV GND RDT HV GND HV BUS Typical application diagram using bootstrap biasing EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet Please read the sections "Important notice" and "Warnings" at the end of this document 1.00 www.infineon.com/gdisolated 2024-06-12

Table 1 Ordering information Product type Typical UVLO (VUVLOL2/VUVLOH2) Typical output current source/sink Functionality UL 1577 certification (single isolation) IEC 60747-17 certification (reinforced isolation) Package marking 2ED3140MC12L 8.5 V / 9.3 V 6 A / 6.5 A DISABLE E311313 planned 3140MC12 2ED3141MC12L 11 V / 12 V 6 A / 6.5 A DISABLE E311313 planned 3141MC12 2ED3142MC12L 12.5 V / 13.6 V 6 A / 6.5 A DISABLE E311313 planned 3142MC12 2ED3143MC12L 14.7 V / 16 V 6 A / 6.5 A DISABLE E311313 planned 3143MC12 2ED3144MC12L 8.5 V / 9.3 V 6 A / 6.5 A ENABLE E311313 planned 3144MC12 2ED3145MC12L 11 V / 12 V 6 A / 6.5 A ENABLE E311313 planned 3145MC12 2ED3146MC12L 12.5 V / 13.6 V 6 A / 6.5 A ENABLE E311313 planned 3146MC12 2ED3147MC12L 14.7 V / 16 V 6 A / 6.5 A ENABLE E311313 planned 3147MC12 Table 2 Related evaluation boards Board name Gate driver Power transistor Short description EVAL-2ED3146MC12L-SIC 2ED3146MC12L IMZA120R020M1H Half bridge board with the 2ED3146MC12L gate driver and paired with CoolSiC™ in PG-TO-247-4 package EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 2 1.00 2024-06-12

EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Table of contents Datasheet 3 1.00 2024-06-12

EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Table of contents Datasheet 4 1.00 2024-06-12

1 Block diagram reference

RX & Shoot through protection Active shut- down VCC2A VCC2A OUTA VEE2A UVLO RX & Shoot through protection Active shut- down VCC2ATX 7N.C. GND1 5DIS / EN GND1 2INB 6DT 8VCC1 Input to output reinforced isolation Channel to channel functional isolation OTP OTP Figure 2 Block diagram

2 Pin configuration and description

Pin No. Name Function

1 INA Input signal channel A

2 INB Input signal channel B

3,8 VCC1 Positive power supply input side

4 GND1 Ground reference input side

5 DIS DISABLE input channel A and B (high active)

5 EN ENABLE input channel A and B (high active)

6 DT Dead-time control

7 N.C. No internal connection

9 VEE2B Ground reference output channel B

10 OUTB Gate driver output channel B

11 VCC2B Positive power supply output channel B

12 VEE2A Ground reference output channel A

13 OUTA Gate driver output channel A

14 VCC2A Positive power supply output channel A

EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 5 1.00 2024-06-12

N.C. VCC1 VCC2B OUTB VEE2B Figure 3 DSO-14-71 (top view) Pin description

• VCC1: Input supply voltage. Connect to 3.3 V or 5 V and decouple with a capacitor to GND1. Use a low ESR and ESL capacitor placed as close as possible to the device
• GND1: Input ground. All the input side signals, VCC1, IN+ and IN- are referenced to this ground
• INA: Non-inverted control signal for output channel A. An internal filter provides robustness against noise at INA
• INB: Non-inverted control signal for output channel B. An internal filter provides robustness against noise at INB
• DIS (2ED3140-2ED3143): Disable input pin. When at logic high, it switches OUTA and OUTB off, at logic low the output levels are controlled by their individual input pins
• EN (2ED3144-2ED3147): Enable input pin. When at low, it switches OUTA and OUTB off, at logic high the output levels are controlled by their individual input pins
• DT: Dead-time control. The feature is active if the pin is connected to GND1 via a resistor, inactive if tied to VCC1 or left open. It is not recommended to connect capacitive loads to this pin. The configured dead-time should be reasonably smaller than the minimum pulse width
• VCC2A: Channel A positive power supply rail. Connect a decoupling capacitor from this pin to VEE2A. Use low ESR and ESL capacitors placed as close as possible to the device
• VEE2A: Channel A output ground. VCC2A and OUTA are referenced to this ground. In case of a bipolar supply (positive and negative voltage referred to the IGBT emitter or MOSFET source), this pin should be connected to the negative supply voltage
• OUTA: Channel A output pin used to charge and discharge the gate of the external transistor (IGBT or MOSFET). During the on-state this output is connected to VCC2A and during the off-state to VEE2A. This output is controlled by INA and will be turned off by an UVLO or OTP event
• VCC2B: Channel B positive power supply rail. Connect a decoupling capacitor from this pin to VEE2B. Use low ESR and ESL capacitors placed as close as possible to the device
• VEE2B: Channel B output ground. VCC2B and OUTB are referenced to this ground. In case of a bipolar supply (positive and negative voltage referred to the IGBT emitter or MOSFET source), this pin should be connected to the negative supply voltage
• OUTB: Channel B output pin used to charge and discharge the gate of the external transistor (IGBT or MOSFET). During the on-state this output is connected to VCC2A and during the off-state to VEE2B. This output is controlled by INB and will be turned off by an UVLO or OTP event EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet

Datasheet 6 1.00 2024-06-12

3 Electrical characteristics and parameters

3.1 Absolute Maximum Ratings

Table 4 Absolute Maximum Ratings Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Operating the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Device reliability may be affected by exposure to absolute-maximum-rated conditions for extended periods of time. Parameter Symbol Values Unit Note or condition Min. Typ. Max. Power supply input side voltage VVCC1 -0.3 17 V VVCC1 - VGND1 Power supply output side voltage VVCC2 -0.3 35 V VVCC2A - VVEE2A, VVCC2B - VVEE2B Gate driver output voltage VOUT VVEE2A/B - 0.3 VVCC2A/B + 0.3 V Logic input voltages (INA, INB, DIS/EN) VIN -0.3 17 V Dynamic logic input voltages (INA, INB, DIS/EN) VINdyn -5 17 V 1) tIN < 50 ns Dead time control (DT) VDT -0.3 VVCC1 + 0.3 V Input to output offset voltage VOFFSET 2300 V 2) VOFFSET = |VVEE2A/B - VGND1| ESD robustness - human body model |VESD,HBM| 2 kV 3) ESD robustness - charged device model ESD,CDM TC1000 4) Junction temperature TJ -40 150 °C Storage temperature TStg -65 150 °C PG-DSO-14-71 Thermal characteristics Power dissipation (input side) PD,IN 66 mW 5) TA = 85 °C Power dissipation (output side) PD,OUT 900 mW 6) 7) TA = 85 °C, equally distribute to the output channels Thermal resistance junction-case (top) RthJC 46 K/W Thermal resistance junction ambient RthJA25 69 K/W 8) TA = 25 °C, 2s2p - no vias, PD = 900 mW Thermal resistance junction ambient RthJA85 65 K/W 8) TA = 85 °C, 2s2p - no vias, PD = 900 mW Thermal resistance junction board RthJB 27 K/W 9) TA = 85 °C, 2s2p - no vias, PD = 450 mW Characterization parameter junction-top ΨthJT 12 K/W 10) (table continues...) EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 7 1.00 2024-06-12

Table 4 (continued) Absolute Maximum Ratings Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Operating the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Device reliability may be affected by exposure to absolute-maximum-rated conditions for extended periods of time. Parameter Symbol Values Unit Note or condition Min. Typ. Max. Characterization parameter junction-board ΨthJB25 23 K/W 10) TA = 25 °C 1) Parameter is not subject to production test - verified by design/characterization 2) for functional operation only 3) According to ANSI/ESDA/JEDEC-JS-001-2017 (discharging a 100 pF capacitor through a 1.5 kΩ series resistor). 4) According to ANSI/ESDA/JEDEC-JS-002-2014 (TC = test condition in volt) 5) IC input-side power dissipation is derated linearly with 14 mW/°C above 145 °C 6) IC output-side power dissipation is derated linearly with 14 mW/°C above 85 °C 7) For both channels in total 8) 2s2p high-K board, as specified in JESD51-7, in an environment described in JESD51-2 9) 2s2p high-K board, as specified in JESD51-7, in an environment described in JESD51-8 with a ring cold plate fixture to control the PCB temperature 10) Estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)

3.2 Recommended operating conditions

Table 5 Recommended operating conditions Parameter Symbol Values Unit Note or condition Min. Typ. Max. Power supply input side voltage VVCC1 3 16.5 V VVCC1 - VGND1 Power supply output side voltage VVCC2 9.6 32 V VVCC2A/B - VVEE2A/B, 2ED3140 & 2ED3144 Power supply output side voltage VVCC2 12.35 32 V VVCC2A/B - VVEE2A/B, 2ED3141 & 2ED3145 Power supply output side voltage VVCC2 14 32 V VVCC2A/B - VVEE2A/B, 2ED3142 & 2ED3146 Power supply output side voltage VVCC2 16.45 32 V VVCC2A/B - VVEE2A/B, 2ED3143 & 2ED3147 Logic input voltages (INA, INB, DIS/EN) VIN 0 5.5 V Dead time control (DT) VDT 0 VVCC1 V Ambient temperature TA -40 125 °C – Junction temperature TJ -40 150 °C – EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 8 1.00 2024-06-12

3.3 Electrical characteristics

The electrical characteristics include the spread of values over supply voltages and temperatures within the recommended operating conditions. Electrical characteristics are tested in production at TA = 25 °C. Typical values represent the median values measured at VVCC1 = 3.3 V, VVCC2A/B - VVEE2A/B = 15 V, and TA = 25 °C. Minimum and maximum values in characteristics are verified by characterization/design. This is valid for all electrical characteristics unless specified otherwise.

3.3.1 Power supply

Parameter Symbol Values Unit Note or condition Min. Typ. Max. UVLO threshold input side (on) VUVLOH1 2.85 3 V VVCC1 - VGND1 UVLO threshold input side (off) VUVLOL1 2.55 2.7 V VVCC1 - VGND1 UVLO hysteresis input side VHYS1 0.1 0.15 0.2 V VUVLOH1 - VUVLOL1 Quiescent current input side IQ1 1.67 2.12 mA INA = Low, INB = Low, DT = VCC1 Quiescent current output side, ON state IQ2,ON 1.35 mA 1) INA = High, INB = Low or INA = Low, INB = High, VVCC2A/B - VVEE2A/B < 18 V Quiescent current output side, OFF state IQ2,OFF 1.0 mA 1) INA = Low, INB = Low, VVCC2A/B - VVEE2A/B < 18 V 2ED3140 / 2ED3144 UVLO threshold output side (on) VUVLOH2 9.3 9.6 V VVCC2A/B - VVEE2A/B UVLO threshold output side (off) VUVLOL2 8.25 8.55 V VVCC2A/B - VVEE2A/B UVLO hysteresis output side VHYS2 0.75 V VUVLOH2 - VUVLOL2 2ED3141 / 2ED3145 UVLO threshold output side (on) VUVLOH2 12 12.35 V VVCC2A/B - VVEE2A/B UVLO threshold output side (off) VUVLOL2 10.7 11.05 V VVCC2A/B - VVEE2A/B UVLO hysteresis output side VHYS2 0.95 V VUVLOH2 - VUVLOL2 2ED3142 / 2ED3146 UVLO threshold output side (on) VUVLOH2 13.6 14 V VVCC2A/B - VVEE2A/B UVLO threshold output side (off) VUVLOL2 12.15 12.55 V VVCC2A/B - VVEE2A/B UVLO hysteresis output side VHYS2 1.05 V VUVLOH2 - VUVLOL2 2ED3143 / 2ED3147 UVLO threshold output side (on) VUVLOH2 16 16.45 V VVCC2A/B - VVEE2A/B UVLO threshold output side (off) VUVLOL2 14.30 14.75 V VVCC2A/B - VVEE2A/B UVLO hysteresis output side VHYS2 1.25 V VUVLOH2 - VUVLOL2 1) Per channel EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 9 1.00 2024-06-12

3.3.2 Logic input

Parameter Symbol Values Unit Note or condition Min. Typ. Max. INA,INB, DIS / EN low input threshold voltage VIN,L 0.9 1.2 1.6 V INA, INB, DIS / EN high input threshold voltage VIN,H 1.73 2.0 2.36 V INA, INB, DIS / EN low/high hysteresis VIN,HYS 0.38 0.8 1.2 V INA, INB, DIS / EN input current IIN 22 27 μA VVCC1 = 3.3 V, VIN <= VVCC1 INA, INB, DIS / EN pull down resistor RIN,PD 150 kΩ –

3.3.3 Gate driver

Parameter Symbol Values Unit Note or condition Min. Typ. Max. High level output peak current IOUTH 3.5 6 A 1) VVCC2A/B - VVEE2A/B = 15 V, INA/B = High, CL = 100 nF High level output on resistance RDSON,H 0.3 0.9 2.2 Ω IOUTH = 0.1 A Low level output peak current IOUTL 3.5 6.5 A 1) VVCC2A/B - VVEE2A/B = 15 V, INA/B = Low, CL = 100 nF Low level output on resistance RDSON,L 0.2 0.5 1.1 Ω IOUTL = 0.1 A Short circuit clamp voltage between OUTA/B and VCC2A/B VCLP_OUTH 1.0 V VOUTA/B - VVCC2A/B, IOUTA/B = -500 mA, t < 10 µs, INA/B = High Clamp voltage between VEE2A/B and OUTA/B VCLP_OUTL 1.0 V VVEE2A/B-VOUTA/B, IOUTA/B = -500 mA, t < 10 µs, INA/B = Low 1) Parameter is not subject to production test - verified by design/characterization

3.3.4 Dead-time and shoot-through protection

Table 9 Dead-time and shoot-through protection Parameter Symbol Values Unit Note or condition Min. Typ. Max. Dead-time tDT 85 100 115 ns 1) RDT = 10 kΩ Dead-time tDT 255 300 345 ns 1) RDT = 30 kΩ Dead-time tDT 800 950 1100 ns 1) 2) RDT = 100 kΩ Dead-time to resistor value ratio KDT_R 8 10 12 ns/ kΩ 1.2kΩ ≤ RDT ≤ 100kΩ, tDT = KDT_R x RDT + MDT_R (table continues...) EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 10 1.00 2024-06-12

Table 9 (continued) Dead-time and shoot-through protection Parameter Symbol Values Unit Note or condition Min. Typ. Max. Dead-time offset MDT_R 0 ns tDT = KDT_R x RDT + MDT_R Dead-time resistor range RDT 1.2 100 kΩ Ch-to-ch dead-time matching ΔtDT ,Ch-Ch 10 ns RDT = 10 kΩ, ΔtDT ,Ch-Ch = |tDT ,A-B - tDT ,B-A| Ch-to-ch dead-time matching ΔtDT ,Ch-Ch 14 ns RDT = 30 kΩ, ΔtDT ,Ch-Ch = |tDT ,A-B - tDT ,B-A| Ch-to-ch dead-time matching ΔtDT ,Ch-Ch 40 ns 2) RDT = 100 kΩ, ΔtDT ,Ch-Ch = |tDT ,A- B - tDT ,B-A| Part-to-part dead-time matching ΔtDT ,P-P 20 ns RDT = 10 kΩ Part-to-part dead-time matching ΔtDT ,P-P 55 ns RDT = 30 kΩ Part-to-part dead-time matching ΔtDT ,P-P 105 ns 2) RDT = 100 kΩ 1) Input filter time not included 2) Parameter is not subject to production test - verified by design/characterization

3.3.5 Dynamic characteristics

Table 10 Dynamic characteristics Parameter Symbol Values Unit Note or condition Min. Typ. Max. Input to output propagation delay ON tPDON 30 39 50 ns VVCC2A/B - VVEE2A/B = 15 V, CL = 100 pF, valid for INA, INB and DIS/ EN, VDT = VVCC1 Input to output propagation delay OFF tPDOFF 30 39 50 ns VVCC2A/B - VVEE2A/B = 15 V, CL = 100 pF, valid for INA, INB and DIS/ EN, VDT = VVCC1 Input to output propagation delay distortion |tPDISTO| 0 5 ns 1) |tPDOFF - tPDON| Input to output, part to part turn- on skew tSKEW_ON,P-P 6 ns 1) CL = 100 pF, VDT = VVCC1 Input to output, part to part turn- off skew tSKEW_OFF,P- P 8 ns 1) CL = 100 pF, VDT = VVCC1 Input to output, channel to channel turn-on skew tSKEW_ON,Ch- Ch 5 ns VDT = VVCC1, tSKEW_ON,Ch-Ch = | tPDON,A - tPDON,B| Input to output, channel to channel turn-off skew tSKEW_OFF,Ch -Ch 5 ns VDT = VVCC1; tSKEW_OFF,Ch-Ch = | tPDOFF,A - tPDOFF,B| Input pulse suppression time (filter time) tINFL T 10 17 25 ns 2) Input to output, channel to channel skew plus tSKEW+ 5 ns max {|tPDOFF,A - tPDON,B|,|tPDOFF,B - tPDON,A|}, VDT = VVCC1 (table continues...) EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 11 1.00 2024-06-12

Table 10 (continued) Dynamic characteristics Parameter Symbol Values Unit Note or condition Min. Typ. Max. Rise time tRISE 20 ns VVCC2A/B - VVEE2A/B = 15 V, CL = 1 nF, valid for all parts, except 2ED3143 and 2ED3147 Rise time tRISE 20 ns VVCC2A/B - VVEE2A/B = 18 V, CL = 1 nF, valid for 2ED3143 and 2ED3147 Fall time tFALL 20 ns VVCC2A/B - VVEE2A/B = 15 V, CL = 1 nF, valid for all parts, except 2ED3143 and 2ED3147 Fall time tFALL 20 ns VVCC2A/B - VVEE2A/B = 18 V, CL = 1 nF, valid for 2ED3143 and 2ED3147 Input-side start-up time tSTART ,VCC1 3.5 5 μs 3) INA/B = High, DT = VCC1, DIS = low / EN = high, VVCC2A/B > VUVLOH2, CL = 100pF Input-side deactivation time tSTOP ,VCC1 600 750 ns 3) INA/B = High, DT = VCC1, DIS = low / EN = high, VVCC2A/B > VUVLOH2, CL = 100pF Output-side start-up time tSTART ,VCC2 5 10 μs 3) INA/B = High, DIS = Low / EN = High, DT = VCC1, VVCC1 > VUVLOH1, CL = 100pF Output-side deactivation time tSTOP ,VCC2 0.5 1 μs 3) INA/B = High, DIS = Low / EN = High, DT = VCC1, VVCC1 > VUVLOH1, CL = 100pF High-level common-mode transient immunity |CMH| 200 kV/µs 3) VCM = 1500 V, INA/B tied to VCC1, DT = VCC1 Low-level common-mode transient immunity |CML| 200 kV/µs 3) VCM = 1500 V, INA/B tied to GND1, DT = VCC1 Dynamic common-mode transient immunity |CMDYN| 200 kV/µs 3) VCM = 1500 V, INA/B = 10 MHz square wave, DT = VCC1 1) value at same ambient and operating conditions. 2) Valid for INA, INB and DIS/EN, VDT = VVCC1. The pulse is generated outside the DT window; shorter pulses will not propagate to the output. 3) Parameter is not subject to production test - verified by design/characterization

3.3.6 Active shut down

Parameter Symbol Values Unit Note or condition Min. Typ. Max. Active shut down voltage VACTSD 1.8 V VOUTA/B - VVEE2A/B, IOUTL = 500 mA, VCC2A/B open EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 12 1.00 2024-06-12

3.3.7 Overtemperature protection

Table 12 Overtemperature protection Parameter Symbol Values Unit Note or condition Min. Typ. Max. Overtemperature protection level TOTPOFF 150 160 175 °C 1) Overtemperature protection release level TOTPREL 130 140 150 °C 1) Overtemperature protection hysteresis TOTPHYS 20 °C 1) 1) Parameter is not subject to production test - verified by design/characterization EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 13 1.00 2024-06-12

4 Insulation characteristics (IEC 60747-17, UL 1577) for DSO-14-71 package

This coupler is suitable for rated insulation only within the given safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Table 13 Insulation specification for DSO-14-71 package Description Symbol Characteristic Unit Safety limiting values Maximum ambient safety temperature TS 150 °C Maximum input-side power dissipation at TA = 25°C1) PSI 66 mW Maximum output-side power dissipation at TA = 25°C2) PSO 1600 mW Package specific insulation characteristics External clearance CLR > 8 mm Channel-to-channel clearance CLRCh-Ch > 3.3 mm External creepage CPG > 8 mm Channel-to-channel creepage CPGCh-Ch > 3.3 mm Comparative tracking index CTI > 400 – Isolation capacitance CIO 2 pF Reinforced insulation according to IEC 60747-17 (planned) Installation classification per IEC 60664-1, Table F.1 for rated mains voltage ≤ 150 V (rms) for rated mains voltage ≤ 300 V (rms) for rated mains voltage ≤ 600 V (rms) for rated mains voltage ≤1000 V (rms) I-IV I-IV I-III I-II Climatic classification 40/125/21 – Pollution degree (IEC 60664-1) 2 – Apparent charge, method a Vpd(ini),a = VIOTM, Vpd(m) = 1.6 × VIORM, tini = 1 min, tm = 10 s qpd < 5 pC Apparent charge, method b Vpd(ini),b = VIOTM × 1.2, Vpd(m) = 1.875 × VIORM, tini = 1 s, tm = 1 s qpd < 5 pC Isolation resistance at TA,max; VIO = 500 VDC, TA = 125 °C RIO > 1011 Ω Isolation resistance at TS; VIO = 500 VDC, TS = 150°C RIO_S > 109 Ω Maximum rated transient isolation voltage VIOTM 8000 V (peak) Maximum repetitive isolation voltage VIORM 1767 V (peak) Maximum working isolation voltage VIOWM 1249 V (rms) Impulse voltage VIMP 8000 V (peak) Maximum surge isolation voltage for reinforced isolation; VTEST ≥ VIMP × 1.3 VIOSM 11000 V (peak) Recognized under UL 1577 (File 311313) Insulation withstand voltage (60 s) VISO 5700 V (rms) Insulation test voltage (1 s) VISO, TEST 6840 V (rms) 1) IC input-side power dissipation is derated linearly at 14 mW/°C above 145 °C 2) IC output-side power dissipation is derated linearly at 12.6 mW/°C above 25 °C EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 14 1.00 2024-06-12

5 Typical characteristics

Unless otherwise noted,the measurements are done with VVCC1 = 3.3 V, 100 nF capacitor connected between VCC1 and GND1, 4.7 μF capacitor between VCC2A/B and VEE2A/B. Table 14 Figure 4 IQ1 vs. temperature Figure 5 IQ1 vs. frequency @ TA = 25°C Figure 6 IQ2,ON vs. temperature Figure 7 IQ2,OFF vs. temperature (table continues...) EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 15 1.00 2024-06-12

Table 14 (continued) Figure 8 IQ2 vs. frequency @ Cload = 100pF & TA = 25°C Figure 9 VUVLOH1 and VUVLOL1 vs. temperature Figure 10 VUVLOH2 and VUVLOL2 (2ED3146MC12L) vs. temperature (table continues...) EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 16 1.00 2024-06-12

Table 14 (continued) Figure 11 IOUTH vs. temperature Figure 12 RDSON,H vs. temperature Figure 13 IOUTL vs. temperature Figure 14 RDSON,L vs. temperature (lines are overlapping) (table continues...) EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 17 1.00 2024-06-12

Table 14 (continued) Figure 15 tPDON & tPDOFF vs. temperature Figure 16 tSKEW_ON,Ch-Ch & tSKEW_OFF,Ch-Ch vs. temperature Figure 17 tSKEW+ vs. temperature Figure 18 |tPDISTO| vs. temperature (table continues...) EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 18 1.00 2024-06-12

Table 14 (continued) Figure 19 tRISE & tfall vs. temperature @ CLOAD = 1 nF Figure 20 tRISE & tfall vs. CLOAD Figure 21 tDT vs. temperature @ RDT = 10kΩ Figure 22 tDT vs. temperature @ RDT = 30kΩ (table continues...) EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 19 1.00 2024-06-12

Table 14 (continued) Figure 23 tDT vs. temperature @ RDT = 100kΩ Figure 24 tDT vs. RDT EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 20 1.00 2024-06-12

6 Parameter measurement

6.1 CMTI measurement setup

+ V CM - ISOLATION BARRIER 15 V VEE2A VCC2B DIS DT Figure 25 Static CMTI test circuit The figure above shows the test setup for static common mode transient immunity GND1 INA INB VCC1 5 V C 1 C 2 VEE2 OUTA OUTB VCC2A C 3 C 4 + V CM - ISOLATION BARRIER 15 V VEE2A VCC2B DIS DT Figure 26 Dynamic CMTI test circuit The figure above shows the test setup for dynamic common mode transient immunity

6.2 Undervoltage lockout (UVLO)

The following diagram shows the behavior of the channel outputs under UVLO conditions. In order to measure the thresholds, INA and INB are held at logic high and then the power supply voltages VVCC1 and VVCC2x are ramped down EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 21 1.00 2024-06-12

and up. When the voltages decrease below the VUVLOLx levels, the channels turn off, allowing the threshold to be measured. Increasing the voltages, once they go above the VUVLOHx, the channel turn on, again allowing the thresholds to be measured. All these thresholds are measured using slow ramps on all supplies. V UVLOH2 V UVLOL2 V UVLOH1 V UVLOL1 INx VCC1 VCC2x-VEE2x OUTx tSTART,VCC1 tSTART,VCC2tSTOP,VCC1 tSTOP,VCC2 Figure 27 UVLO behavior

6.3 Propagation delay, rise and fall time

The following diagrams show the propagation delays tPDON and tPDOFF for the INA and INB, as well as DIS, including the rise time, tRISE, and fall time, tFALL. INA/B OUTA/B tPDON 10% tPDOFF 20% 80% tRISE tFALL 90% V IN,H V IN,L DIS (low) Figure 28 Propagation delay for DIS variants INA/B (high) OUTA/B tPDON 10% tPDOFF 20% 80% tRISE tFALL 90% V DIS,L V DIS,H DIS Figure 29 Propagation delay for the DIS pin The following diagrams show the propagation delays tPDON and tPDOFF for the INA and INB, as well as EN, including the rise time, tRISE, and fall time, tFALL. EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 22 1.00 2024-06-12

10% tPDOFF 20% 80% tRISE tFALL 90% V IN,H V IN,L EN (high) Figure 30 Propagation delay for EN variants INA/B (high) OUTA/B tPDON 10% tPDOFF 20% 80% tRISE tFALL 90% V EN,H V EN,L EN Figure 31 Propagation delay for the EN pin

6.4 Deadtime matching, skew and skew+

The channel-to-channel deadtime matching ΔtDT ,Ch-Ch is defined as the absolute difference between the deatimes generated by the falling edges of the 2 channels INA and INB. INA INB OUTA OUTB t DT,A-B 90% 10% 90% 10% t DT,B-A Δt DT, Ch-Ch = |t DT,A-B - t DT,B-A | Figure 32 Channel-to-channel deadtime matching The next figure illustrates the channel-to-channel turn-on skew tSKEW_ON,CH-Ch and the channel-to-channel turn-off skew tSKEW_OFF,CH-Ch. These parameters highlights the mismatch in propagation delay between the two channels when simultaneous pulses with the same edge are applied to the two channels, and are relevant when paralleling gate drivers. EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 23 1.00 2024-06-12

10% OUTB t SKEW_ON,Ch-Ch 10% t SKEW_OFF,Ch-Ch 90% 90% OUTA OUTB INB INA INB Figure 33 Input to output, channel-to-channel skew for rising and falling edges The last figure in this chapter illustrates the channel-to-channel skew+ tSKEW+,Ch-Ch. The parameter describes the variation between the turn-on and turn-off propagation delays of separate channels in a half-bridge. This is relevant when driving the channels drivers complimentary and helps define the minimum deadtime required for safe operation. OUTB 10% INB INA 90% OUTA t SKEW+ V IN,L V IN,H OUTA 10% INB INA 90% OUTB t SKEW+ V IN,L V IN,H Figure 34 Input to output, channel-to-channel skew+ for rising and falling edges All skew parameters are valid when the channels and gate drivers are operated under the same bias and temperature conditions. EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 24 1.00 2024-06-12

7 Functional description

7.1 Input side functional blocks

The input side of the gate driver contains several blocks, which ensure the interfacing to the microcontroller, as well as the data transmission across the isolation barrier. INA GND1 VCC1

3 UVLO

7N.C. GND1 5DIS / EN GND1 2INB 6DT 8VCC1 Input to output reinforced isolation TX TX Figure 35 Input side block diagram The following blocks are available:

• Input supply undervoltage lockout
• Input signal filters
• Pulldown resistors
• Deadtime control

7.1.1 Input supply undervoltage lockout (UVLO)

The UVLO block on the input chip monitors the voltage between the VCC1 and the GND1 pins and ensures that there is enough voltage between these pins for the internal circuitry to operate correctly. As long as the voltage between these two pins is below VUVLOL1, no turn-on signals coming on the INA or INBpins are sent across the isolation barrier, and the channels are by default turned off. In order to allow turn-on signals to cross the isolation barrier, the voltage between the VCC1 and the GND1 pins must exceed the VUVLOH1 threshold and stay above VUVLOL1, otherwise the communication across the isolation barrier is disabled and the channels are turned off. Although the UVLO ensures that the voltage between the VCC1 and GND1 pins is large enough, it does not provide protection against dynamic disturbances coming across the supply lines, which can propagate to the internal circuits of the device. EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 25 1.00 2024-06-12

t STOP ,VCC1 t START,VCC1 90%*V VCC2A/B 10%*V VCC2A/B INA/B VCC1 VCC2A/B OUTA/B Figure 36 Input side UVLO behavior

7.1.2 Input signal filters

Every pulse at INA, INB or DIS/EN, shorter than the input pulse suppression time tINFL T, will be filtered and will not be transmitted to the output chip. Longer pulses will be sent to the output with the shown propagation delay tPDON and tPDOFF. This aids the design and an external RC filter for noise suppression will not be needed in most cases. INx OUTx t INx <t INFLT t INx >t INFLT t PDON t PDOFF t INFLT t INFLT Figure 37 Input filter behavior

7.1.3 Pulldown resistors

Each of the digital input pins has a pulldown resistor attached to it. This ensures that in case the pin is desoldered from the board, it is pulled to a safe state, with the channels disabled. This is valid for INA, INB, as well as the variants with EN pins. The variants with DIS pins allow a simpler driving, as well as lower current consumption, since by default the driver is active. But it is highly recommended not to leave this pin floating, and if not actively driven by the microcontroller, it should be connected to GND1.

7.1.4 Deadtime control

The Deadtime control block implements the non-overlapping between the two channels, depending on the state of the DT pin. The following states and behaviors are defined:

• DT connected to GND1: A minimal (<10 ns) shoot-through protection between the channels is implemented EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet

Datasheet 26 1.00 2024-06-12

• DT connected to VCC1 or left floating: The two channels behave as independent drivers
• DT is connected through a resistors to GND1: A deadtime is implemented between the falling edge of a channel and the rising edge of the other channel, according to the equation: tDT = KDT_R x RDT+MDT_R Note that in case of DT pin disconnection during operation, the device will not transition automatically to independent driver mode. INA INB OUTA OUTB A B C D E F t DT t DT t DT t DT t DT t DT Figure 38 Deadtime special pulses When a resistor is connected to the DT pin, the following behaviors are defined:
• A & B: when complementary signals appear at the input pins at the same time, the deadtime will be generated at the falling edge of the turned off channel, and only after it has expired, the turn-on of the other channel will be triggered
• C: if the turn-on signal on one channel has appeared after a time greater that tDT from the turn-off of the other channel, the deadtime is not visible at the output of the two channels
• D: if a channel receives a turn-on command when the other channel is already on, both channels are turned immediately off, until the condition at the input dissapears
• E & F: when exiting condition D, a deadtime will be generated from the turn-off command of one channel, until the other channel is turned on It is not recommended to connect capacitors to the DT pin. EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet

Datasheet 27 1.00 2024-06-12

7.2 Output side functional blocks

The output side of the device contains 2 identical ICs, each driving one of the output channels. Each IC has the following blocks:

• Output side undervoltage lockout (UVLO)
• Short-circuit clamping
• Active shutdown
• Overtemperature protection (OTP) VCC2x OUTx VEE2x UVLO RX Shoot through protection Active shut- down VCC2x OTP Figure 39 Output side block diagram

7.2.1 Output side undervoltage lockout (UVLO)

The UVLO block on the output chip monitors the voltage between the VCC2A/B and the VEE2A/B pins and ensures that there is sufficient voltage between these pins to drive the connected switch properly. As long as the voltage between these two pins is below VUVLOL2, no turn on signals coming across the isolation barrier will change the output state, and the channels are by default turned off. In order to allow the turn-on of the channels, the voltage between the VCC2A/B and the VEE2A/B pins must exceed the VUVLOH2 threshold and stay above VUVLOL2, otherwise the channels will automatically be turned off, regardless of the state of the input pins. Since the charge required to turn-on the power switch connected to the channel is provided by the buffer capacitor connected between the VCC2A/B and VEE2A/B, this capacitor must be dimensioned so that during or after the turn-on event, the voltage between these two pins does not drop below VUVLOL2, as this will automatically trigger the turn off of the driver. OUTA/B INA/B VCC2A/B VCC1 V UVLOH2 V UVLOL2 t STOP ,VCC2A/Bt START,VCC2A/B 90%*V VCC2A/B 10%*V VCC2A/B Figure 40 Output side UVLO behavior EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 28 1.00 2024-06-12

7.2.2 Short-circuit clamping

During short circuit, the gate voltage of the power transistor tends to rise because of the feedback via the Miller capacitance. In this situation, the IC internally clamps the voltage on the OUTA/B pins and limits the voltage to a value slightly higher than the supply voltage VVCC2A/B. A maximum current of 500 mA may be fed back to the supply through this path for 10 μs. If higher currents are expected or tighter clamping is desired, external Schottky diodes should be added between the OUTA/B and VCC2A/B pins.

7.2.3 Active Shutdown

The active shutdown function is a protection feature of the driver. It is designed to avoid a turn-on of the power switch due to a floating gate. The active shut-down feature ensures a safe IGBT , Si or SiC MOSFET off-state in case the output chip is not connected to the power supply or an undervoltage lockout is in effect. The IGBT , Si or SiC MOSFET gate is clamped via the OUTA/B-pin to VEE2A/B. In case of a missing or collapsing power supply at the VCC2A/B pin, the output section of the driver operates in the active shutdown mode. In this case, the driver uses the floating voltage of the connected gate to supply this internal circuit. This solution is by far stronger than using the external resistor placed between the gate and the source pins of the power switch. At the same time, in case of fast dV/dt events on the switch that would generate miller current that could bias the gate, even when the gate driver is not powered on, the active shutdown circuit will use the voltage to self power and actively pull the gate low. The active shut-down feature functions in a similar manner across all the variants.

7.2.4 Overtemperature protection

The overtemperature protection shuts down the output of the gate driver IC and protects the application when the junction temperature of the IC exceeds the threshold temperature, TOTPOFF. The output is then kept off until the temperature reaches the safe level of TOTPREL. At this moment, the output is turned on again, if the turn-on command is again sent. It must be noted that, although the overtemperature protection feature attempts to protect the device, operating the driver above TJ may potentially damage the driver permanently. EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 29 1.00 2024-06-12

8 Application information

Note: Infineon is providing this information as a courtesy only and without acknowledging any legal obligation. Information in the following application chapters is not part of the Infineon component specification, and Infineon does not warrant its accuracy or completeness. Infineon’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Typical application

This section describes how the gate drivers can be used in the application. The figures below show examples of application implementations. GND1 INA INB VCC1 OUTA VCC2A VEE2A +5 V SGND INA +18 V 3R3 4µ7 100n 0 V OUTB +18 V 4µ7 0 V INB VCC2B VEE2B DIS DT 3R3 3R3 3R3 3R3 3R3 Figure 41 Independent dual channel operation with unipolar biasing using SiC switches In order to operate the driver as two independent channels, the DT pin needs to be connected to the input supply pin VCC1. This way, the driver does not impose any deadtime between the INA and INB signals. This operating mode can be used when dealing with space restrictions or in very cost-sensitive applications. Also shown in the figure above is the usage of unipolar power supplies, where VEE2A/B pin should be connected directly to the source or emitter of the power transistor. This biasing strategy can be used when switches without parasitic turn-on are used, or at lower dV/dt of the switching node. When different turn-on and turn-off speeds are desired, a diode and an additional series resistor can be added in parallel to the already existing gate resistor. In the picture, the equivalent discharging resistor is roughly half of the charging resistor. A Schottky diode should be used for such an implementation and it's voltage drop must be taken into consideration. GND1 INA INB VCC1 OUTA VCC2A VEE2A +5 V SGND INA +18 V 3R3 4µ7 100n -5 V 4µ7 0 V OUTB +18 V 3R3 4µ7 -5 V 4µ7 0 V INB VCC2B VEE2B EN DT 10KΩ EN Figure 42 Half-bridge operation with bipolar biasing using SiC switches The device can also be operated in half-bridge mode, by connecting a resistor between the DT and the GND1 pins. When this is done, the driver implements a dead-time between the falling edge of one channel and the rising edge of the other channel. Note that also the dead-time distortion |tDTD| must be taken into account. Also shown in the picture is the usage of a bipolar driving supply. In this case a virtual ground is realized using two capacitors connected in series from VCC2A/B to VEE2A/B, with the middle point connected to the source or emitter of the driven switch. EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 30 1.00 2024-06-12

8.2 Power supply recommendations

The 2ED314xMC12L gate drivers support a wide range of voltages on the input and the output side. The devices can operate with unipolar as well as bipolar power supply voltages on the output side for reliable and safe operation in the application. To ensure that the gate driver operates correctly, it is necessary to place appropriate decoupling capacitors on the power supply pins. On the input side, it is recommended to place a low ESR, surface mount, multilayer ceramic capacitor of 100 nF between the VCC1 pin and GND1 pin. This capacitor should be placed as close as possible to the pins. The decoupling capacitors on the output side, in addition to decoupling any disturbance on the power supply, also store the necessary energy to deliver the peak currents required for turning on and off the power transistor. Therefore, these capacitors should be dimensioned appropriately to limit the voltage drop during the power transistor turn-on and off. When using a unipolar power supply, a low ESR, surface mount, multilayer ceramic capacitor of at least 4.7 µF should be placed between the VCC2A/B pin and the VEE2A/B pin in the close proximity of the pins. In case of a bipolar power supply, it is recommended to use at least 4.7 µF ceramic capacitors between VCC2A/B and virtual ground(source or emitter potential of power transistor) and also between VEE2A/B pin and virtual ground. Depending on the gate charge of the power transistor and the peak source and sink gate currents, a higher capacitance may be necessary to limit the voltage drop during power transistor turn-on and turn-off. Finally, a 100 nF decoupling capacitor is recommended between VCC2A/B and VEE2A/B pins ensuring a short path between them to decouple any high frequency noise. When selecting the capacitors, it is important to take into account the capacitance drop of ceramic capacitors in relation to the applied DC voltage.

8.3 Gate resistor selection

The gate resistor is a key component in the gate drive circuit . The gate resistor limits the source and the sink current of the gate driver thereby exercising control over the switching speed of the associated power transistor during both turn-on and turn-off operations. As such, the careful selection of an appropriate gate resistor represents a vital consideration in the design process. Some important considerations for selection of the gate resistance are:

• Optimize the switching losses
• Limit the overshoots and oscillations of the drain source voltage of the collector emitter voltage of the power transistor during turn-off
• Limit the overshoot and oscillations of the drain current or collector current during turn-on
• Damp the oscillations of the gate source or gate emitter voltage due to parasitic inductances and capacitances in the gate loop As a starting point the gate driver selection, the gate resistor used in the datasheet of the power transistor for the characterization of the turn-on and turn-off losses can be used. The power supply conditions are rarely the same as the supply conditions that are used in power transistor data sheets. Therefore, an adaptation of the power transistor datasheet values is required to obtain a starting point for the optimization of the final gate resistor. The method which is proposed here uses the same peak gate current value for both the actual application and the power transistor datasheet. The peak gate current as per power transistor datasheet equals to: IG, pk = ΔVGS RG, datasheet + RG, int = ΔVGS RG, application + RG, int with ΔVGS = VVCC2 − VVEE2 (1) Solving this equation for RG leads to: EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet

Datasheet 31 1.00 2024-06-12

RG = ΔVGS IG, pk − RG, int (2) This method results in a starting point for the gate resistor selection. Further evaluations, such as EMI measurements, are required for the final dimensioning of the gate resistors as they have to be adjusted to work with the circuitry inductance, margins and allowed dV/dt transients. While dimensioning the components for gate resistances, it is necessary to take into account the average power dissipation in these resistors due to the switching of the power transistor as explained in the losses-based external gate resistor selection, as well as the pulse power capability of the component.

8.4 Deadtime resistor selection

The choice of the deadtime resistor must take into account the minimum pulse width which can occur during the operation. If the minimum pulse width has values similar to the deadtime, excessive diode conduction can occur, with loss of efficiency and potential device damage in the case of SiC switches. Therefore it is recommended to keep the deadtime reasonably smaller than the minimum pulse width, taking into account of course rise and fall time, as well as channel propagation delay.

8.5 Power dissipation estimation

8.5.1 Gate driver

The gate driver input side losses are dominated by the quiescent losses, which are calculated by: PQ1 = VVCC1 ⋅ IQ1 (3) The gate driver output side losses for each channel consist of the quiescent current losses PQ2A/B at nominal switching frequency and no load, the sourcing losses Psource,A/B and the sinking losses Psink,A/B POUT, A/B = PQ2, A/B + Psource, A/B + Psink, A/B (4) The quiescent losses on the output side PQ2,A/B can be calculated as: PQ2, A/B = VVCC2A/B − VVEE2A/B ⋅ IQ2 (5) The turn-on, Psource,A/B, and turn-off, Psink,A/B, losses can be estimated using the resistive voltage divider between the internal resistance of the gate driver output stage, RDSON,H or RDSON,L, and external gate resistor, RG,ext, with the application related gate charge, QG, the total gate driving voltage, VVCC2A/B - VVEE2A/B, and switching frequency, fsw: Psource, A/B = 1 2QG ⋅ fsw ⋅ VVCC2A/B− VVEE2A/B ⋅ RDSON,H RDSON, H + RG,ext, ON + RG,int Psink, A/B = 1 2QG ⋅ fsw ⋅ VVCC2A/B − VVEE2A/B ⋅ RDSON,L RDSON,L + RG,ext, OFF + RG,int (6) Additionally, external components that surround the gate driver can heat up the IC. The mere calculation of losses and the theoretical junction temperature alone are not sufficient for a proven gate driver circuit design. A verification EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 32 1.00 2024-06-12

by measurement is needed to avoid unexpected effects in the application. The identification of hotspots is possible, for example, by using an infrared camera.

8.5.2 External gate resistor

The losses in the gate resistor for turn-on, RG,ext,ON and the gate resistor for turn-off, RG,ext,OFF can estimated using the same resistive voltage divider formed by the resistances in the source and the sink path of the gate current as: Psource, ext = 1 2QG ⋅ fsw ⋅ VVCC2− VVEE2 ⋅ RG,ext, ON RDSON, H + RG,ext, ON + RG,int Psink, ext = 1 2QG ⋅ fsw ⋅ VVCC2 − VVEE2 ⋅ RDSON,L RDSON,L + RG,ext, OFF + RG,int (7)

8.6 Layout guidelines

Having a well-designed PCB layout is crucial to achieve optimal performance of the gate driver. Subsequently, this will ensure that the entire power electronic converter is operating at its best. Creating a well-designed PCB layout requires a certain level of attention and consideration to specific key factors. The following key points should be considered while designing the PCB layout using 2ED314xMC12L gate drivers:

• The low ESR, low ESL type decoupling capacitor on the input side, must be placed close to the VCC1 and GND1 pins and then connected to the pins such that the decoupling loop is as short as possible. Similarly, the decoupling capacitors on the output side should be placed close to the VCC2A/B and VEE2A/B pins and connected to the pins with a short connection
• It is crucial to minimize the physical area of the gate current loop that carries the current for charging and discharging the gate of the power transistor. The gate loop contain traces with high dv/dt and di/dt and having a short loop minimizes noise from the turn-on and off of the gates. Furthermore, a short loop also minimizes the stray inductance of the gate loop which improves the switching performance. To accomplish a short gate loop, the gate driver should be positioned near the power transistor, and the decoupling capacitors that store the energy for high peak currents should be located in close proximity to the gate driver
• In order to reduce the stray inductance of the gate loop even further, wide traces can be used for the traces in the gate loop. Furthermore, the forward path and the return path of the currents can be routed parallel to each other on the same PCB layer or overlapping each other on adjacent PCB layer to achieve the least amount of stray inductance
• In case of a unipolar power supply, the VEE2A/B pin of the gate driver should be connected to the Kelvin source/ emitter pin of the power transistor, if available. If the Kelvin pin is not available then the connection to the source/emitter should be as short as possible, starting from the device pin, in order to avoid the high current from the power transistor flowing in the gate loop
• The area below the body of the gate driver package should be kept free of any traces to ensure the integrity of the safety isolation between the input and output side
• It is recommended that the input signals of the gate driver connected to the INA and INB pins are kept away from any noisy traces. Although the 2ED314xMC12L comes with an integrated input filter that can filter high frequency noise on the input signal, an external RC filter with a small time constant can be placed close to these pins for enhanced filtering. Additionally, a ground plane is recommended below the input signal traces for shielding the signals from noise
• The gate driver IC experiences power dissipation during system operation as explained in the previous chapters. This heat generated in the device will be dissipated mostly via the PCB. It is recommended to maximize the copper area connected to the VEE2A/B pins, in order to effectively dissipate the heat from the gate driver on to the PCB EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet

Datasheet 33 1.00 2024-06-12

9 Related products

Note: Please consider the gate driver IC power dissipation and insulation requirements for the selected power switch and operating condition. Product group Product name Description TRENCHSTOP™ IGBT Discrete IKWH40N65WR6 650 V, 40 A IGBT with anti-parallel diode in TO-247-3-HCC IHW30N160R5 1600 V, 30 A IGBT Discrete with anti-parallel diode in TO-247 IKW15N120CS7 1200 V IGBT7 S7, 15 A IGBT with anti-parallel diode in TO247 IKQ75N120CS7 1200 V IGBT7 S7, 75 A IGBT with anti-parallel diode in TO247-3 CoolSiC™ SiC MOSFET Discrete IMBF170R1K0M1 1700 V, 1000 mΩ SiC MOSFET in TO-263-7 with extended creepage IMZA120R040M1H 1200 V, 40 mΩ SiC MOSFET in TO247-4 package IMZA120R014M1H 1200 V, 14 mΩ SiC MOSFET in TO247-4 package IMBG120R030M1H 1200 V, 30 mΩ SiC MOSFET in TO-263-7 package IMYH200R012M1H 2000 V, 12 mΩ SiC MOSFET in TO-247-PLUS with high creepage and clearance CoolSiC™ SiC MOSFET Module FS33MR12W1M1H_B11 EasyPACK™ 1B 1200 V, 33 mΩ sixpack module FF17MR12W1M1H_B11 EasyDUAL™ 1B 1200 V, 17 mΩ half-bridge module FF4MR12W2M1H_B11 EasyDUAL™ 2B 1200 V, 4 mΩ half-bridge module F4-17MR12W1M1H_B11 EasyPACK™ 1B 1200 V, 17 mΩ fourpack module TRENCHSTOP™ IGBT Modules F4-100R17N3E4 EconoPACK™ 3 1700 V, 100 A fourpack IGBT module F4-200R17N3E4 EconoPACK™ 3 1700 V, 200 A fourpack IGBT module FP10R12W1T7_B11 EasyPIM™ 1B 1200 V, 10 A three phase input rectifier PIM IGBT module FS100R12W2T7_B11 EasyPACK™ 2B 1200 V, 100 A sixpack IGBT module FP150R12KT4_B11 EconoPIM™ 3 1200V three-phase PIM IGBT module FS200R12KT4R_B11 EconoPACK™ 3 1200 V, 200 A sixpack IGBT module EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 34 1.00 2024-06-12

Figure 43 PG-DSO-14-71 (300 mil) outline Figure 44 PG-DSO-14-71 (300 mil) recommended footprint EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 35 1.00 2024-06-12

Revision history

v1.00 2024-06-12 • Initial official release EiceDRIVER™ 2ED314xMC12L (2ED-X3 Compact) Datasheet Datasheet 36 1.00 2024-06-12

All referenced product or service names and trademarks are the property of their respective owners. Edition 2024-06-12 Published by Infineon Technologies AG

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© 2024 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-ngj1689156282272 Important notice The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. Warnings Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.