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18V Enery Storage and Management Unit for SSD Application Evaluation Board EV5512-V-00A Rev.1.1 www.MonolithicPower.com 1 6/4/2015 MPS Proprietary Information. Patent Prot ect. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. The Future of Analog IC Technology
DESCRIPTION
EV5512-V-00A Evaluation Board is designed to demonstrate the capabilities of MP5512. MP5512 is one front end power storage and management IC for SSD application. MP5512 supports input hot-swap, input reverse current protection, input power failure indication and high efficient power backup for SSD data backup in case of input power failure. MP5512’s built-in boost mode converter charges storage bulk capacitor to a programmed voltage when system is powered up, and in case of input power failure, MP5512 flags the power failure, disconnects input power and transfers the energy from storage capacitor to SSD system’s DCDC switches via built-in buck mode converter to support SSD system data backup. MP5512 is available in QFN28-4x5mm package. ELECTRICAL SPECIFICATION Parameter Symbol Value Units Input Voltage V IN 12 V Storage Voltage V STRG 35 V Input Pfail Threshold V PFI 6.1 V Bus Backup Voltage V RLS 7.8 V Bus Backup Max Load I RELEASE 3 A
FEATURES
Wide 4V to 18V Operating Input Range Programmable up to 40V Storage Voltage Up to 4.5A Input Current Limit Input Reverse Current Protection Adjustable Slew Rate for VB Start-up Rising 14m Ω MOSFET for Input Hot-swap High Efficiency Power Backup with Internal 140mΩ and 110mΩ Power Switches Input Failure Indicator and Input Early Warning for VIN Programmable Input Current Limit and Current Monitor Stable Work with 0.1 μF Input Capacitor for Hot-swap Thermal Protection Available in a QFN28 (4mm×5mm) Package
APPLICATIONS
Solid-State Drives Hard-Disk Drives All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. EV5512-V-00A EVALUATION BOARD (L x W x H) 6.35cm x 6.35cm x 1.4cm Board Number MPS IC Number EV5512-V-00A MP5512GV VSTRG Release VS 5V/div. VB 5V/div. IB 2A/div. PFI 5V/div.
EV5512-V-00A – ENERGY STORAGE AND MANAGEMENT FOR SSD EV BOARD EV5512-V-00A Rev.1.1 www.MonolithicPower.com 2 6/4/2015 MPS Proprietary Information. Patent Prot ect. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. EVALUATION BOARD SCHEMATIC CST BSTSW VBO STRGSTRG FBS RTEST WARN PFI PGB PGND AGND ILIM DVDT TPOR VCC ICH ENCH EN DET FBB VB VIN 169k 22uF C2B 20k AGND PGND 10nF AGND 1uF 10uHL1 430k 10k AGND 4.75k AGND PGND 10nF AGND NS AGND 1uF AGND 200k 100k 15k 0.1uF PGND AGND NSR9 4.7uF C4A PGND 100k R14 100k R13 100kR12 100kR11 100kR10 150uF C4B PGND VCC 100k R15 0.1uF C2A PGND DFLS240 NS PGND NS VCC VIN VB VS Note: 1) Schottky diode D1 is required in all applications.
EV5512-V-00A – ENERGY STORAGE AND MANAGEMENT FOR SSD EV BOARD EV5512-V-00A Rev.1.1 www.MonolithicPower.com 3 6/4/2015 MPS Proprietary Information. Patent Prot ect. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. EV5512-V-00A BILL OF MATERIALS Qty Ref Value Description Package Manufacturer Part Number 2 C1, C2A 0.1 μF Ceramic Cap., 25V, X7R 0603 Murata GRM188R71E104KA01D 1 C2B 22 μF Ceramic Cap., 25V, X7R 1206 Murata GRM31ER71E226KE15L 2 C3, C5 1 μF Ceramic Cap., 10V, X5R 0402 Murata GRM155R61A105KE15D 1 C4A 4.7 μF Ceramic Cap., 50V, X7R 1206 Murata GRM31CR71H475KA12L 1 C4B 150 μF Electrolytic Cap., 50V DIP JiangHai CD284 2 C6, C8 10nF Ceramic Cap., 50V, X7R 0402 Murata GRM155R71H103KA88D
0 C7 NS
1 D1 DFLS240L Schottky Diode, 40V, 2A PowerDI123 Diodes DFLS240L-7
0 D2, D3 NS
1 L1 10 μH Inductor, I SAT=4.9A, 41mΩ SMD Coilcraft XAL5050-103ME R1, R10, R11, R12, R13, R14, R15 100kΩ Film Res., 1% 0402 Yageo RC0402FR07100KL 1 R2 15k Ω Film Res., 1% 0402 Yageo RC0402FR0715KL 1 R3 169k Ω Film Res., 1% 0402 Yageo RC0402FR07169KL 1 R4 20k Ω Film Res., 1% 0402 Yageo RC0402FR0720KL 1 R5 430k Ω Film Res., 1% 0402 Yageo RC0402FR07430KL 1 R6 10k Ω Film Res., 1% 0402 Yageo RC0402FR0710KL 1 R7 4.75k Ω Film Res., 1% 0402 Yageo RC0402FR074K75L 1 R8 200k Ω Film Res., 1% 0402 Yageo RC0402FR07200KL
0 R9 NS
1 U1 MP5512 Energy Storage and
Management Unit QFN28 4x5 MPS MP5512GV
EV5512-V-00A – ENERGY STORAGE AND MANAGEMENT FOR SSD EV BOARD EV5512-V-00A Rev.1.1 www.MonolithicPower.com 4 6/4/2015 MPS Proprietary Information. Patent Prot ect. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. EVB TEST RESULTS Performance waveforms are tested on the evaluation board. VIN = 12V, VSTRG = 35V, VPFI = 6.1V, VRLS = 7.8V(2), L = 10µH, TA = 25ºC, POUT = 20W, unless otherwise noted. VIN Power On ENCH Power On EN Power On VSTRG Release VSTRG Release VSTRG ReleaseVSTRG Release VSTRG Release VSTRG Release VIN 10V/div. VB 10V/div. VS 20V/div. VS 5V/div. IL 500mA/div. PFI 5V/div. VB 5V/div. IB 2A/div. PFI 5V/div. VS 5V/div. VB 5V/div. IB 2A/div. PFI 5V/div. VS 5V/div. VB 5V/div. IB 2A/div. PFI 5V/div. VS 5V/div. VB 5V/div. IB 2A/div. PFI 5V/div. VS 5V/div. VB 5V/div. IB 2A/div. PFI 5V/div. VS 5V/div. VB 5V/div. IB 2A/div. PFI 5V/div. EN 5V/div. VB 10V/div. VS 20V/div. IL 500mA/div. PFI 5V/div. ENCH 5V/div. VB 10V/div. VS 20V/div. IL 500mA/div. PFI 5V/div. Note: 2) V RLS voltage varies a little with different VSTRG voltage because the internal RAMP voltage on FBB changes with duty cycle. 7.8V voltage is estimated based on 30V VSTRG condition.
EV5512-V-00A – ENERGY STORAGE AND MANAGEMENT FOR SSD EV BOARD NOTICE: The information in this document is subject to change wi thout notice. Users should warra nt and guarantee that third party Intellectual Property rights are not infringed upon w hen integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. EV5512-V-00A Rev.1.1 www.MonolithicPower.com 6 6/4/2015 MPS Proprietary Information. Patent Prot ect. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. QUICK START GUIDE The board layout accommodates most commonly used components. 1, Connect the positive and negative terminals of the load to VB and GND pins, respectively. 2, Preset power supply to 12V, then turn off power supply. 3, Connect power supply terminals to: VIN and GND on board. 4, Turn on power supply after making connections, MP5512 will charge the storage capacitor to 35V. 5, In order to observe the power release performance, following two methods can be applied: Turn off the power supply. Short VIN to GND. Note: make sure bench power supply have output current limiting when such test. 6, To use the enable function, apply a digital input to the EN pin. Drive EN higher than 1.2V to turn on the regulator or less than 0.4V to turn it off. 7, Use R1 and R2 to set power fail indicate voltage: PFI R1 R2V (0.8V 99%) R2 And after power fail, bus voltage VB regulation can be set through R3 and R4: )2()4 31( RAMP REFFBBRLS VVR Where, VRAMP is buck FBB internal compensation ramp voltage, and can be estimated as: SW STRGRAMP 10)1( Where, VFBS-REF is 0.8V typically. D is the buck duty cycle, and FSW is the switching frequency. Similarly, R5 and R6 can be chosen for storage voltage setting: STRG R5 R6V0 . 8 V R6