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GaAs, pHEMT, MMIC, Single Positive Supply, DC to 7.5 GHz, 1 W Power Amplifier Data Sheet HMC637BPM5E Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
P1dB output power: 28 dBm typical Gain: 15.5 dB typical Output IP3: 39 dBm typical Self biased at VDD = 12 V at 345 mA typical Optional bias control on VGG1 for IDQ adjustment Optional bias control on VGG2 for IP2 and IP3 optimization 50 Ω matched input/output 32-lead, 5 mm × 5 mm LFCSP package: 25 mm2
APPLICATIONS
18 NIC
19 NIC
20 GND
21 RFOUT/VDD
22 GND
23 NIC
24 GND
25 GND
26 NIC
27 NIC
28 NIC
29 ACG2
30 ACG1
31 NIC
32 GND
Figure 1. GENERAL DESCRIPTION The HMC637BPM5E is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic high electron mobility transistor (pHEMT), cascode distributed power amplifier. The device is self biased in normal operation and features optional bias control for quiescent current (IDQ) adjustment and for second-order intercept (IP2) and third-order intercept (IP3) optimization. The amplifier operates from dc to 7.5 GHz, providing 15.5 dB of small signal gain, 28 dBm output power at 1 dB gain compression, a typical output IP3 of 39 dBm, and a 3.5 dB noise figure, while requiring 345 mA from a 12 V supply voltage (VDD). Gain flatness is excellent from dc to 7.5 GHz at ±0.5 dB typical, making the HMC637BPM5E ideal for military, space, and test equipment applications. The HMC637BPM5E also features inputs/outputs (I/Os) that are internally matched to 50 Ω, housed in a RoHS-compliant, 5 mm × 5 mm, premolded cavity, lead frame chip scale package (LFCSP), making the device compatible with high volume, surface-mount technology (SMT) assembly equipment.
Rev. 0 | Page 2 of 21 TABLE OF CONTENTS
REVISION HISTORY
5/2018—Revision 0: Initial Version
Rev. 0 | Page 3 of 21 SPECIFICATIONS FREQUENCY RANGE = DC TO 7.5 GHz TA = 25°C, VDD = 12 V, IDQ = 345 mA, VGG1 = GND, VGG2 = open, for nominal self biased operation, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE DC 7.5 GHz GAIN 12.5 15.5 dB Gain Flatness ±0.5 dB Gain Variation over Temperature ±0.015 dB/°C NOISE FIGURE 3.5 dB RETURN LOSS Input 15 dB Output 15 dB OUTPUT Output Power for 1 dB Compression P1dB 25 28 dBm Saturated Output Power PSAT 30.5 dBm Output Third-Order Intercept IP3 39 dBm Measurement taken at output power (POUT)/ tone = 10 dBm SUPPLY Current IDQ 345 mA For the external bias condition, adjust the gate bias voltage (VGG1) between −2 V up to +0.5 V to achieve the desired quiescent current (IDQ) Voltage VDD 8 12 13 V
1 Million Hour Mean Time to Failure
1 When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the specification is listed. and Function Descriptions section. PCB thermal design is required. JC is the junction to case thermal resistance. Table 3. Thermal Resistance
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with 36 thermal vias. See JEDEC JESD51.
- EXPOSED PAD. THE EXPOSED PAD MUST BE
- NIC = NOT INTERNALLY CONNECTED.
Figure 2. Pin Configuration Table 4. Pin Function Descriptions GND Ground. These pins and the exposed pad must be connected to RF/dc ground. the gain response. External capacitors are required (see Figure 69). See Figure 7 for the interface schematic. NIC Not Internally Connected. These pins must be connected to RF/dc ground. 5 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. drain current. External capacitors are required (see Figure 69). See Figure 8 for the interface schematic. Figure 4 and Figure 5 for the interface schematics. 21 RFOUT/VDD RF Output for the Amplifier (RFOUT). Drain Bias Voltage (VDD). Connect the dc bias (VDD) network to provide the drain current, IDD (see Figure 69). See Figure 5 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
transmission line interconnecting the drains of the upper FETs. Figure 68. Simplified Schematic of the Cascode Distributed Amplifier simplified schematic of this architecture is shown in Figure 68. performance is more apparent at lower operating frequencies. into a 50 Ω system with no required impedance matching circuitry. choke through which dc bias is applied. selections limit the lowest frequency of operation.
200 MHz, allowing the flattest possible gain response to be
obtained over various frequencies. exceed the absolute maximum ratings.
Rev. 0 | Page 18 of 21 APPLICATIONS INFORMATION Capacitive bypassing is required for VDD and VGG1, as shown in the typical application circuit in Figure 69. Both the RFIN and RFOUT/VDD pins are dc-coupled. Use of an external dc blocking capacitor at RFIN is recommended. Use of an external RF choke plus a dc blocking capacitor (for example, a bias tee) at RFOUT/ VDD is required. For wideband applications, ensure that the frequency responses of the external biasing and blocking components are adequate for use across the entire frequency range of the application. The HMC637BPM5E operates in either self biased or externally biased mode. To operate in self biased mode, ground the VGG1 pin and leave VGG2 open. For the externally biased configuration, adjust VGG1 within −2 V to +0.5 V to set the target drain current and adjust VGG2 from 4 V to 6 V for IP2 and IP3 control. The recommended bias sequence during power-up for self biased operation is as follows: 1. Connect GND. 2. Set VDD to 12 V . 3. Apply the RF signal. The recommended bias sequence during power-down for self biased operation is as follows : 1. Turn off the RFIN signal. 2. Set VDD t o 0 V. The recommended bias sequence during power-up for externally biased operation is as follows: 1. Connect GND. 2. Set VGG1 t o − 2 V. 3. Set VDD to 12 V . 4. Increase VGG1 to achieve the desired quiescent current (IDQ). 5. Apply the RF signal. 6. When using the IP2/IP3 control function, apply a voltage from 4 V to 6 V until the desired performance is obtained. The recommended bias sequence during power-down for externally biased operation is as follows: 1. Turn off the RFIN signal. 2. Remove the VGG2 voltage. 3. Decrease VGG1 to −2 V to achieve a typical IDQ of 0 mA. 4. Set VDD t o 0 V. 5. Set VGG1 t o 0 V. Adhere to the values shown in the Absolute Maximum Ratings section. Unless otherwise noted, all measurements and data shown were taken using the typical application circuit (see Figure 69), and biased per the conditions in this section. The bias conditions described in this section are the operating points recommended to optimize the overall device performance. Operation using other bias conditions may result in performance that differs from what is shown in the Typical Performance Characteristic section. To obtain the best performance while avoiding damage to the device, follow the recommended biasing sequences described in this section.
can be used if the device is to be operated below 200 MHz.
21 RFOUT
- DRAIN BIAS (VDD) MUST BE APPLIED THROUGH AN ETERNAL BIAS TEE CONNECTED
AT THE RFOUT/VDD PIN AND AN EXTERNAL DC BLOCK MUST BE CONNECTED AT THE RFIN PIN.
- OPTIONAL CAPACITORS MUST BE USED IF THE DEVICE IS OPERATED BELOW 200MHz.
Figure 69. Typical Application Circuit
of a heat sink on the bottom side of the PCB is recommended. Analog Devices, Inc., upon request. Figure 70. Evaluation PCB Table 5. Bill of Materials for the Evaluation PCB EV1HMC637BPM5 (600-01711-00)
3.50 REF
0.035 NOM
0.203 REF
0.60 REF
Figure 71. 32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV] 1 All parts are RoHS Compliant. 2 When ordering the evaluation board only, reference the model number, EV1HMC637BPM5. 3 See the Absolute Maximum Ratings section for additional information. 4 The lead finish of the HMC637BPM5E and the HMC637BPM5ETR is nickel palladium gold (NiPdAu). registered trademarks are the property of their respective owners.