HMC232A AD | Alldatasheet
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 12
Technical content
GaAs, SPDT Switch, Nonreflective,
100 MHz to 12 GHz
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 2022 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Nonreflective 50 Ω design Low insertion loss 1.5 dB typical to 6 GHz 2.5 dB typical to 12 GHz High isolation 50 dB typical to 6 GHz 45 dB typical to 12 GHz High input linearity P0.1dB: 28 dBm typical at VCTRL = −5 V P1dB: 30 dBm typical at VCTRL = −5 V IP3: 48 dBm High power handling 30 dBm insertion loss path 27 dBm hot switching Negative control voltage: −7 V to −3 V ESD rating: 250 V (Class 1A) HBM No low frequency spurious 24-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Telecommunication infrastructure FUNCTIONAL BLOCK DIAGRAM F igure 1. GENERAL DESCRIPTION The HMC232A is a nonreflective, SPDT, RF switch manufactured in the gallium arsenide (GaAs) process. The HMC232A operates from 100 MHz to 12 GHz with better than 1.5 dB insertion loss and 50 dB of isolation at 6 GHz and better than 2.5 dB insertion loss and 45 dB of isolation at 12 GHz. The HMC232A has a nonreflective design, and the RF ports are internally terminated to 50 Ω. The HMC232A switch operates using complementary negative control voltage logic lines of −7 V to −3 V and requires no bias supply. The HMC232A comes in a 24-lead, 4 mm × 4 mm LFCSP and operates from −40°C to +85°C. 13NIC GND RFC GND NIC NIC NIC NIC B A NIC NIC GND RF1 GND NIC
12 NIC
22 RF2
23 GND
24 NIC
50Ω 50Ω PACKAGE BASE GND 25187-001
Rev. B | Page 2 of 12 TABLE OF CONTENTS
REVISION HISTORY
10/2022—Rev. 01.0818 to Rev. B This Hittite Microwave Products data sheet has been re formatted to meet the styles and standards of Analog Devices, Inc. Changes to Features Section, Figure 1, and General Description Added Thermal Resistance Section, Table 3; Renumbered Sequentially, Power Derating Curve Section, Figure 2; Renumbered Sequentially, Electrostatic Discharge (ESD) Added Theory of Operation Section, RF Input and Output Added Applications Information Section, Layout Considerations Section, Board Layout Section, Figure 19, and
Rev. B | Page 3 of 12 SPECIFICATIONS ELECTRICAL SPECIFICATIONS Digital control input voltage (VCTRL) = 0 V or −7 V to −3 V , and TC = 25°C in a 50 Ω system, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE 100 1 2,000 MHz INSERTION LOSS Between RFC and RF1 or RFC and RF2 (On) 100 M Hz to 3 GHz 1. 4 1.7 dB 100 M Hz to 6 GHz 1. 5 1.8 dB 100 M Hz to 9 GHz 2. 0 2.3 dB 100 M Hz to 12 GHz 2 .5 3.1 dB RETURN LOSS Between RFC and RF1 or RFC and RF2 (On) 100 M Hz to 6 GHz 18 dB
100 M Hz to 9 GHz 14 dB
100 M Hz to 12 GHz 12 dB
RF1 or RF2 (Off ) 100 M Hz to 12 GHz 14 dB ISOLATION Between RFC and RF1 or RCF and RF2 (Off ) 100 M Hz to 3 GHz 52 57 dB
100 M Hz to 6 GHz 45 50 dB
100 M Hz to 9 GHz 42 47 dB
100 M Hz to 12 GHz 40 45 dB
Rise Time and Fall Time tRISE, tFALL 10% to 90% of RF output 6 ns On Time and Off Time tON, tOFF 50% of triggered VCTRL to 90% of RF output 25 ns INPUT LINEARITY1 5 00 MHz to 12 GHz Input Compression 0.1 dB P0.1dB VCTRL = −3 V 22 d Bm VCTRL = −5 V 28 d Bm 1 dB P1dB VCTRL = −3 V 26 d Bm VCTRL = −5 V 30 d Bm Intermodulation Distortion Input Third-Order Intercept IIP3 VCTRL = −3 V to −7 V, two tone input power = 10 dBm each tone, Δfrequency = 1 MHz 48 d Bm DIGITAL CONTROL INPUTS A and B pins Voltage Low VINL −0.2 0 V High VINH −7 −3 V Current Low IINL 0.2 µ A High IINH 2 0 µ A RECOMMENDED OPERATING CONDITIONS RF Input Power PIN VCTRL = −5 V, frequency = 500 MHz to 12 GHz, TC = 85°C Insertion Loss Path R F signal is applied to RFC or through connected RF1 or RF2 30 dBm Terminated Path R F signal is applied to the terminated RF1 or RF2 23 dBm Hot Switching R F signal is present at RFC while switching between RF1 and RF2 27 dBm TC −4 0 +8 5 °C 1 For input linearity performance vs. frequency, see Figure 11 through Figure 18.
500 MHz to 12 GHz at TC = 85°C)
1 For power derating vs. frequency, see Figure 2. PCB thermal design is required. Table 3. Thermal Resistance ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 4. HMC232A, 24-Lead LFCSP
which path is in the isolation state (see Table 6). the RF potential is equal to 0 V . external matching networks are not required. internal 50 Ω termination resistor. recommended on the supply lines to filter high frequency noise.
- Power up the digital control inputs. The relative order of
the digital control inputs is not important.
- Apply an RF input signal to RFC, RF1, or RF2.
Table 6. Control Voltage Truth Table
Figure 22. Typical Application Circuit Table 7. Evaluation Board Bill of Materials
Rev. B | Page 12 of 12 OUTLINE DIMENSIONS F igure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.85 mm Package Height (CP-24-16) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option HMC232ALP4E −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16 HMC232ALP4ETR −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16 EV1HMC232ALP4 E valuation Board 1 All models are RoHS compliant parts. 0.50 BSC 0.50 0.40 0.30 COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-8 BOTTOM VIEWTOP VIEW SIDE VIEW 4.10 4.00 SQ 3.90 0.90 0.85 0.80
0.05 MAX
0.02 NOM
0.20 REF
0.08 712 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 09-10-2018-C 0.30 0.25 0.18
0.20 MIN
2.80 2.70 SQ 2.60 EXPOSED PAD PKG-004926/004942 SEATING PLANE PI N 1 IN D ICATO R AR E A OP TIO N S (SEE DETAIL A) DETAIL A (JEDEC 95) PIN 1 INDICATOR AREA ©2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D25187-10/22(B)