EV1380QI

EV1380QI ENPIRION | Alldatasheet

Document overview

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Technical content

Features

• High efficiency, up to 94%.
• Output voltage tracks VDDQ +/- 1%
• Nominal 1.5MHz operating frequency with ability to synchronize to an external clock source or serve as the primary source.
• Programmable soft-star t time. Soft Shutdown.
• Master/slave configuration for parallel operation.
• Thermal shutdown, over current, short circuit, and under-voltage protection.
• RoHS compliant, MSL level 3, 260C reflow. Application
• Bus Termination: DDR2, DDR3, & QDR™ memory VTTVDDQ COUTCIN VOUT ENABLE AGND VREF VDDQ AVIN PGND PGND EV1380 CSS RA VCNTRL VFB RB RC RD SW RPD FQADJ RFS CA SCHOTTKY CAVIN Figure 2: Typical Application Schematic (VDDQ is the memory core voltage; VTT is memory termination voltage that tracks VDDQ)

©Enpirion 2010 all rights reserved, E&OE 2 www.enpirion.com Ordering Information Pin Assignments (Top View) NC NC NC NC NC NC(SW) NC(SW) VDDQOK FQADJ EN_PB VSENSE VREF EAOUT VFB POK AGND1 AVIN1 ENABLE M/S S_OUT NC VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT NC SW SW PGND PGND PGND PGND PGND PGND PGND 15 68 Part Number Temp Rating (°C) Package EV1380QI -40 to +85 68-pin QFN T&R EV1380QI-E QFN Evaluation Board Figure 3: Pin Out Diagram (Top View) NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. Pin Description PIN NAME FUNCTION 1-15, 25, 46-47, 64-68 NC NO CONNECT: These pins must be soldered to PCB but not be electrically connected to each other or to any external signal, voltage, or ground. These pins may be connected internally. Failure to follow this guideline may result in device damage. 16-24 VOUT Regulated converter output. Connect to the load, and place output filter capacitor(s) between these pins and PGND pins 28-31. 26-27 SW These pins are internally connected to the common switching node of the internal MOSFETs. The anode of a schottky diode needs to be connected to these pins. The cathode of the diode needs to be connected to VDDQ. 28-34 PGND Input/Output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT and PVIN descriptions for more details. 35-43 VDDQ In DDR applications the input to this pin is the DDR core voltage. This is the input power supply to the power train which will be divided by two to create an output voltage that tracks with the input voltage applied to this pin. Place input filter capacitor(s) between these pins and PGND pins 32-34. 44 AGND2 Ground for the gate driver supply. Connect to the ground plane with a via. 45, 52 AVIN2, AVIN1 Analog input voltage for the controller circuits. Each of these pins needs to be separately connected to the 3.3V input supply. Decouple with a capacitor to AGND1. 48 S_IN Digital Input. Depending on the M/S pin, this pin accepts either an input clock to phase lock the internal switching frequency or a S_OUT signal from another Enpirion device. Leave this pin floating if it is not used.

©Enpirion 2010 all rights reserved, E&OE 3 www.enpirion.com PIN NAME FUNCTION 49 S_OUT Digital Output. Depending on the M/S pin, either a clock signal synchronous with the internal switching frequency or the PWM signal is output on this pin. Leave this pin floating if it is not used. 50 M/S This is a Ternary Input put. Floating the pin disables parallel operation. A low level configures the device as Master and a High level configures the device as a slave. 51 ENABLE This is the Device Enable pin. Tie this pin to VDDQ with a 10kΩ resistor. 53 AGND This is the quiet ground for the control circuits. Connect to the ground plane with a via. 54 POK POK is a logical AND of VDDQOK and the internally generated POK of the EV1380. POK is an open drain logic output that requires an external pull-up resistor. POK is logic high when VOUT is within -10% to +10% of VOUT nominal. This pin guarantees a logic low even when the EV1380 is completely un-powered. This pin can sink a maximum 4mA. The pull-up resistor may be connected to a power supply other than AVIN or VDDQ but the voltage should be <3.6Volts. 55 VFB This is the External Feedback input pin. A resistor divider connects from the output to AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward capacitor is required across the upper resistor.) The output voltage regulates so as to make the VFB node voltage = VREF. 56 EAOUT Optional Error Amplifier output. Allows for customization of the control loop. 57 VREF External voltage reference input. A resistor divider connects from VDDQ to AGND. The mid-point of the resistor divider is connected to VREF. The resistor divider has to be chosen to make the voltage applied to this pin ~0.4*VDDQ. An optional capacitor (for soft start) may be connected from VREF to AGND. 58 VSENSE Connect this pin to VOUT. 59 EN_PB This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support start-up under a pre-biased load. This pin is pulled high internally. 60 FQADJ Tie this pin to AGND through a 13kΩ resistor.

61 VDDQOK This is an active high input pin that indicates the externally supplied VDDQ has

reached its POK level. This pin should be tied to the VDDQ regulator POK output, or let float if unused. 62-63 NC(SW) NO CONNECT: These pins are internally connected to the common switching node of the internal MOSFETs. They must be soldered to PCB but not be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in device damage.

69 PGND Device thermal pad to be connected to the system GND plane for heatsinking

purposes. See Layout Recommendations section.

©Enpirion 2010 all rights reserved, E&OE 4 www.enpirion.com Absolute Maximum Ratings PARAMETER SYMBOL MIN MAX UNITS Input Supply Voltage: AVIN1, AVIN2 VIN -0.5 4.0 V Voltages on: EN, EN_PB, VDDQOK -0.5 VIN V Voltages on: VFB, VREF, EAOUT, M_S, S_IN, S_OUT, VDDQ, VOUT, VSENSE, FQADJ -0.5 2.7 V Voltage on: POK 3.6 V Voltage on: SW -0.5 VDDQ+0.5 V Storage Temperature Range TSTG -65 150 °C Maximum Operating Junction Temperature TJ-ABS Max 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C ESD Rating (based on Human Body Model) – VREF pin 1500 V ESD Rating (based on Human Body Model) – All other pins 2000 V ESD Rating (based on CDM) 500 V Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS Input Voltage Range: AVIN1, AVIN2 3.07 3.53 V Input Voltage Range: VDDQ 1.16 1.65* V Input Voltage Range: VREF VEXTREF 0.5 0.5 V EN_PB, VDDQOK, M/S, S_IN, EN 0 AVIN V Operating Ambient Temperature TA - 40 +85 °C Operating Junction Temperature TJ - 40 +125 °C *: For DDR2 applications with VDDQ=1.8V, contact Enpirion applications support. Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) θJA 16 °C/W Thermal Resistance: Junction to Case (0 LFM) θJC 1.5 °C/W Thermal Shutdown TSD 150 °C Thermal Shutdown Hysteresis TSDH 20 °C Note 1: Based on a 2oz. copper board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards.

©Enpirion 2010 all rights reserved, E&OE 5 www.enpirion.com

Electrical Characteristics

NOTE: AVIN1, AVIN2 = 3.3V, over operating temperature range unless otherwise noted. Typical values are at TA = 25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Power Supply Voltage VDDQ 1.16 1.65 V Controller Supply Voltage AVIN 3.07 3.3 3.53 V Output Voltage Accuracy – Initial ΔV OUT VOUT =1/2 VDDQ (e.g. @ VDDQ = 1.500V), 0.1% input and output resistor dividers) 0.740 0.760 V VFB Pin Voltage VVFB 3.07V ≤ AVIN ≤ 3.53V, VDDQ = 1.5V, 0A ≤ ILOAD ≤ 8A 591 600 609 mV VFB Pin Input Leakage Current IVFB VFB pin input leakage current -5 5 nA Shut-Down Supply Current IS Power Supply current with Enable=0 450 μA Under Voltage Lock-out – AVIN Rising V UVLOR Voltage above which UVLO is not asserted 2.2 V Under Voltage Lock-out – AVIN Falling V UVLOF Voltage below which UVLO is asserted 2.05 V Peak-to-Peak Ripple RPP VDDQ = 1.5V, VOUT = 0.75V, IOUT = 8A, COUT = 3x100 µF (1206) <10 mV Maximum Continuous Output Sourcing Current I OUT_Max_SRC Maximum load current. See Note 1. 8 A Maximum Continuous Output Sinking Current I OUT_Max_SNK Maximum load current. See Note 1. 8 A Over Current Trip Level IOCPH Sourcing. VDDQ = 1.5V 18 A Switching Frequency FSW R FQADJ = 13kOhms 1.5 MHz External SYNC Clock Frequency Lock Range F PLL_LOCK SYNC clock input frequency range RFQADJ = 13kOhms 1.25 1.75 MHz S_IN Clock Amplitude – Low VS_IN_LO SYNC Clock Logic Level 0.4 V S_IN Clock Amplitude – High V S_IN_HI SYNC Clock Logic Level 1.8 2.5 V S_IN Clock Duty Cycle (PLL) DC S_INPLL M_S Pin Float or Low 20 80 % S_IN Clock Duty Cycle (PWM) DC S_INPWM M_S Pin High 50 % Pre-Bias Level VPB Allowable pre-bias as a fraction of programmed output voltage. 0 40 % VOUT Range for POK = High VDDQ rising Range of output voltage as a fraction of programmed value when P OK is asserted 92±3 110±3 % VOUT Range for POK = High VDDQ falling Range of output voltage as a fraction of programmed value when P OK is asserted 90±3 % POK Deglitch Delay Falling edge deglitch delay after output crossing 90% level 64 Clock cycles VPOK Logic Low level With 4mA current sink into POK pin 0.7 1 V

©Enpirion 2010 all rights reserved, E&OE 6 www.enpirion.com PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VPOK Logic high level AVIN V POK Current Sink Capability 3.07V ≤ AVIN ≤ 3.53V 4 mA VTT Tracking VDDQ VDDQ – 2*VTT VDDQ > 1V, VDDQ Rate of change at 1V/ms -25 +25 mV Enable Pin Current IEN Tied to VDDQ through a 10kΩ 50 μA Logic Low Threshold VB-LOW ENABLE, S_IN, VDDQOK 0.4 V Logic High Threshold VB-HIGH ENABLE, S_IN, VDDQOK 1.8 V S_OUT Low Level VS_OUT_LOW 0.4 V S_OUT High Level VS_OUT_HIGH 2.0 V M/S Pin Logic Low Threshold V T-LOW Threshold voltage for Logic Low 0.4 V M/S Pin Logic High Threshold V T-HIGH Threshold voltage for Logic High (internally pulled high; can be left floating to achieve logic high) 2.0 2.7 V M/S Pin Input Current IITERN The ternary pin has 100kΩ to AGND and another 100kΩ to an internal 2.5V supply. If connecting to AVIN recommend using a series resistor. See Figure 7. See Figure μA Current Balance ΔIOUT With 2 converters in parallel, the difference between any two parts. AVIN<50mV, R TRACE< 2 mΩ +/-10 % Note 1: Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.

©Enpirion 2010 all rights reserved, E&OE 7 www.enpirion.com Typical Performance Characteristics Load Current Efficiency (%) Efficiency AVIN = 3.3V, VDDQ = 1.5V VOUT = VDDQ * 0.5 20MHz BW Limit 500 MHz BW Output Ripple: AVIN = 3.3V, VDDQ = 1.16V, VOUT = VDDQ*0.5, Iout = 8A, CIN = 2x47μF (0805), Output Ripple: AVIN = 3.3V, VDDQ = 1.16V, VOUT = VDDQ*0.5, Iout = 8A, CIN = 2x47μF (0805), COUT = 4x100μF (1206) COUT = 2x47μF (1206) 20MHz BW Limit 500 MHz BW Output Ripple: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Iout = 8A, CIN = 2x47μF (0805), Output Ripple: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Iout = 8A, CIN = 2x47μF (0805), COUT = 4x100μF (1206) COUT = 4x100μF (1206)

©Enpirion 2010 all rights reserved, E&OE 8 www.enpirion.com Load Transient Response: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Ch.1: VOUT, Ch.2: ILOAD 0↔~4A, Ch.3: IVDDQ CIN = 2x47μF (0805), COUT = 4x100μF (1206) Load Transient Response: AVIN = 3.3V, VDDQ = 1.215V, VOUT = VDDQ*0.5, Ch.1: VOUT, Ch.2: ILOAD 0↔~4A, Ch.3: IVDDQ CIN = 2x47μF (0805), COUT = 4x100μF (1206) Power Up/Down at No Load: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Ch.1: VOUT, Ch.2: VDDQOK, Ch.3: VDDQ, Ch. 4: POK CIN = 2x47μF (0805), COUT = 4x100μF (1206) Power Up/Down into a ~94mΩ Load: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Ch.1: VOUT, Ch.2: VDDQOK, Ch.3: VDDQ, Ch. 4: POK CIN = 2x47μF (0805), COUT = 4x100μF (1206)

©Enpirion 2010 all rights reserved, E&OE 9 www.enpirion.com Functional Block Diagram (+) (-) Error Amp VOUT HS-Drive LS-Drive UVLO Thermal Limit Current Limit Soft Start Pre-bias PLL / Sawtooth Generator (+) (-) PWM Comp VDDQ ENABLE Compensation Network Bandgap Reference PGND VFB EAOUT S_OUT VREF Over Voltage power Good Logic POK S_IN EAOUT EN_PB Digital I/OM_S To PLL NC(SW) AVIN AVIN VSENSE EV1380QI FQADJ S_DELAY AVINAGND VDDB VDDQOK VDDQ Figure 4: Functional Block Diagram Functional Description grammable Typically two power sources are required to Synchronous Buck Converter The EV1380 is a synchronous, pro Buck power supply with integrated power MOSFET switches and integrated inductor. The switching supply uses voltage mode control and a low noise PWM topology. operate this device. The first power source (AVIN) is for the contro ller with a nominal input voltage range of 3.07-3.53V. The second supply (VDDQ) is the supply that is tracked - the recommended operating range is 1.16 to 1.65V. With the right choice of input and output

©Enpirion 2010 all rights reserved, E&OE 10 www.enpirion.com dividers, the output volt age of the EV1380 will produce an Output Voltage which tracks to ½ VDDQ. The EV1380 can continuously source or sink currents up to 8A. The 1.5MHz nominal switching frequency enables small-size input and output capacitors. oft-Start and Soft-SS hutdown te with the ON, VDDQ rts start up into a pre- le pre-bias is in the range t a logical ‘0,’ the DC/DC converter connected ndle d 0. 45*VDDQ < VOUT < t is driven The EV1380 is expected to opera controller power supply (AVIN) ramped up and down at a relatively slow rate (~1V/mS), and ENABLE ti ed to VDDQ through a 10kΩ resistor. It is also acceptable for VDDQ to be dynamically scaled within a small voltage range. If, however, VDDQ should ramp up at a high rate, a capacitor connected between VREF and AGND provides the soft-start function to limit in-rush current. The soft-start time constant is determined by the input voltage divider and the so ft-start capacitor. See figure 5. Pre-Bias Start-up The EV1380 suppo biased load. Allowab of 0% to 40% of the programmed output voltage. The Pre-Bias f eature is controlled by the EN_PB pin. For the pre-Bias feature to function properly, VDDQ must be stable; Enable must be toggled; and a pre-bias must be present at the output. Phase-Lock Operation: With M_S pin floating or a internal switching clock of the can be phase-locked to a clock signal applied to S_IN. When a clock signal is present at S_IN, an activity detector recognizes the presence of the clock si gnal and the internal oscillator phase locks to the external clock. The external clock could be the system clock or the output of another EV1380. A delayed version of the phase locked clock is output at S_OUT. The clock frequency should be within 1.25MHz to 1.75MHz for guaranteed phase-lock. Two EV1380 devices on a system board may be daisy chained with appropriate phase delays to reduce or eliminate input ripple as well as avoid beat frequency components. Master / Slave (Parallel) Operation: Up to two EV1380 devices may be in a Master / Slave configuration to ha larger load currents. The Master device’s switching clock may be phase-locked to an external clock source or another EV1380. The device is placed in Master mode by pulling the M_S pin low or in Slave mode by pulling M_S pin high. When this pin is in Float state, parallel operation is not possible. In Master mode, the internal PWM signal is output on the S_OUT pin. The PWM signal at S_OUT is delayed relative to the Master device’s internal PWM signal. This PWM signal from the Master is fed to the Slave device at its S_IN input. The Slave device acts like an extension of the power FETs in the Master. The inductor in the slave prevents crow-bar currents from Master to slave due to timing delays. Enpirion does not recommend paralleling more than 2 EV1380’s. POK Operation The internal POK signal is asserted when VDDQ > 0.3V an 0.55*VDDQ, indicating VOUT is tracking VDDQ. This assertion range assumes typical VDDQ slew rates associated with VDDQ POL regulators. For typical VDDQ POL regulators, the VDDQ ramp rate will range from 0.5 V/mSec to 2 V/mSec. Within this range of slew rates, the speed of the POK circuit, the loop bandwidth, and the delay caused by the soft- start capacitor on the VREF pin will not significantly affect the measured POK threshold. For much fa ster VDDQ ramp rates, hot-plug slew rates for example, the speed and latency of the elem ents will cause the measured VOUT voltage where POK is valid to be higher than the actual threshold. The internal EV1380 PO K is AND’ed with the DDQOK input. The VDDQOK inpuV by the upstream VDDQ regulator’s POK output. Normally the VDDQOK input indicates that VDDQ has settled to the required level. If VDDQ is dynamically switched, VDDQOK is expected to mask the EV1380 POK during the voltage transition. POK is not guaranteed to be valid when VDDQ < 300mV. The POK signal is asserted high when rising VOUT

©Enpirion 2010 all rights reserved, E&OE 12 www.enpirion.com Although the EV1380 int egrates most of the compensation network, a phase lead capacitor and a resistor are required in parallel with the upper resistor R a of the external feedback the s. For more information, network as shown in Figure 6. For the 1.5V VDDQ example stated above, C A = 120pF. The compensation is opt imized for use with 3x100μF or 4x100 μF 1206, X5R ceramic output capacitors. In exceptional cases, modifications to compensation might be required. The EV1380’s compensation can be modified for specific application contact Enpirion App lications Engineering support. VTT RA CA RB VFB back and Compensation Network n Figure 6: External Feed Enable Operatio The ENABLE pin should be tied to VDDQ ower applied, t he device automatically starts t-start, provided the AVIN d with X5R or X7R or equivalent through an 0201 resistor. With the device input p to operate with a sof voltage is above the upper UVLO high threshold of ~2.2 volts. Input Capacitor Selection The EV1380 requires between 80uF and 100uF of input capacitanc e. Low ESR ceramic capacitors are requir e dielectric formulation. Y5V dielectric formulations must not be used because these dielectrics lose capacitance with frequency, temperature and bias voltage. In some applications, lower value ceramic capacitors maybe needed in parallel with the larger capacitors in order to provide high frequency decoupling. Recommended Input Capacitors Description MFG P/N 47uF, 10V, X5R, 1206 Taiyo Yuden LMK316BJ476ML-T 47uF, 4V, X5R, 0805 Murata GRM21BR60G476M 100uF, 6.3V, , 1206 X5R Mu GRM31CR60J107Mrata Output Capacito ection 380 has optimi th capacita 300 − or equivalent r Sel The EV1 been zed for use wi an output nce of 400µF. Low ESR with X5R orceramic capacitors are required X7R dielectric formulation. Y5V dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. Recommended Output Capacitors Description MFG P/N 47uF, 10V, X5R, 1206 Taiyo Yuden LMK316BJ476ML-T 47uF, 6.3V, X5R, 1206 Taiyo Yuden Murata JMK316BJ476 GRM31CR60J ML-T 476ME19L 100u F, 6.3V, X5R, 1206 Murata GRM31CR60J107M Output ripple voltag rimarily determined by gate outp ac ito Hz sw e, denote , is c ly e is ut cap itching frequency output p the aggre r impedance. At the 1.5M cimpedan d as Z omprised main of effective series resistance, ESR, and effective series inductance, ESL: Z = ESR + ESL. Placing multiple capacitors in parallel reduces the impedance and hence will result in lower ripple voltage. nTotal Z Z Z Z... 2 1 + + + = Typical Rippl 1 1 1 e Voltages Output Capacitor Configuration Typical Output Ripple (mVp-p) VDDQ = 1.5V, VOUT = 0.75V 3 x 100 uF <10mV Ω= × Ω⋅ = VDDQRA 10 8 000 , 40 ) in (value Ω = ⎛⋅ = k R VR R FB AB nominal 0.6V is value. calculated than lower value standard A RC A A closest to down C Round ) F/ in /R (C A A

©Enpirion 2010 all rights reserved, E&OE 13 www.enpirion.com Ternary Pins M_S is a Ternary pin. This pin can assume ree states – Ath low a floa evice operation trolled by the state of the pin. The pins may be pulled to ating without any special care. M state, a high state and t state. D is con ground or left flo However when pulling hi gh, it is recommended that this pin is tied to VIN with a series resistor. Using the equations in Fi gure 7, the resistor value may be optimized to reduce the current drawn by the pin. 2.5V 100k Figure 7: Selection of to C ns IN M_S (Master/Slave) Pin States EXT to V R onnect Ternary Pi _S Pin Function Low This is Master ase locked to S_IN external clock. S_OUT outputs a delayed version of internal PWM signal mode. Switching ph Float Parallel operation is disabled. S locked to S_IN external clock. S witching phase _OUT outputs a delayed version of lock switching c High This is Slave mode. The S_IN signal directly drives the power FETs. S_OUT outputs a delayed version of S_IN NOTE addition : E al two EV138 npirion Applications can be contacted for information on the Parallel operation of up to 0s for high output current. To Gates Maximum value of R EXT= (V IN-2)*67k Input pin current = /REXT (VIN -2) 100kR3 R EXT PINTo VIN Vf 1380Q ~ 2V EV I AGND

©Enpirion 2010 all rights reserved, E&OE 14 www.enpirion.com Design Considerations Exposed Metal on Bottom of Package Package lead frames offer advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. They do, however, require some special considerations. In the assembly process, lead-frame construction requires-for mechanical support- that some of the le ad-frame cantilevers be exposed at the point where wire-bonds or internal passives are attached. Because of this lead frame requirement, several small pads are exposed on the bottom of the package. Only the large thermal pad and the perimeter pads should be mechanically or electrically connected to the PC boar d. The PCB top layer under the EV1380 should be clear of any metal except for the large thermal pad. The “grayed- out” area in Figure 8 represents the area that should be clear of all me tal (traces, vias, or planes) on the top layer of the PCB. Figure 8: Lead-Frame Exposed Metal. Gray area highlights exposed metal below which there should not be any metal (traces, vias, or planes) on the top layer of the PCB

©Enpirion 2010 all rights reserved, E&OE 15 www.enpirion.com Recommended PCB Footprint Figure 9: EV1380 Package PCB Footprint

©Enpirion 2010 all rights reserved, E&OE 16 www.enpirion.com Package and Mechanical Figure 10: EV1380 Package Dimensions Contact Information Enpirion, Inc. Perryville III

53 Frontage Road, Suite 210

Hampton, NJ 08827 USA Phone: 908-894-6000 Fax: 908-894-6090 Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion.