EV0060

MP1567 MPS | Alldatasheet

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Technical content

1.2A Synchronous Rectified Step-Down Converter MP1567 Rev. 2.3 www.MonolithicPower.com 1 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. The Future of Analog IC Technology TM TM

DESCRIPTION

The MP1567 is a 1.2A, 800KHz DC to DC converter designed for low voltage applications requiring high efficiency. Capable of providing output voltages as low as 0.9V from a 3.3V supply voltage, the MP1567 eliminates the need for a 5V rail, providing over 90% efficiency via synchronous rectification and eliminating heat issues in confined spaces. Soft-start operation protects internal circuitry from hard turn on issues. Switching at 800KHz reduces the size of external components and thereby reduces board space. The MP1567 includes cycle-by-cycle current limiting and under voltage lockout. Internal power switches combined with the tiny 10-pin MSOP or QFN packages provide a solution requiring a minimum of space. EVALUATION BOARD REFERENCE Board Number Dimensions EV0033 (MP1567DK) 2.5”X x 2.0”Y x 0.7”Z EV0059 (MP1567DK) 2.5”X x 2.0”Y x 0.4”Z EV0060 (MP1567DQ) 2.5”X x 2.0”Y x 0.4”Z

FEATURES

• 1.2A Output Current
• Synchronous Rectified
• Internal 180m Ω and 220mΩ Power Switches
• V IN Range of 2.6V to 6V
• Over 90% Efficiency
• Zero Current Shutdown Mode
• Under Voltage Lockout Protection
• Soft-Start Operation
• Thermal Shutdown
• Internal Current Limit (Source & Sink)
• Tiny 10-Pin MSOP or QFN Packages
• Evaluation Boards Available

APPLICATIONS

• SOHO Routers, PCMCIA Cards, Mini PCI
• Handheld Computers, PDAs
• Cell Phones
• Digital Video Cameras
• Small LCD Displays “MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MP1567 SW IN BS 845 FB BPSS COMPSGND PGND EN VOUT 1.8V/1.2A INPUT 2.6V to 6V OPEN IF NOT USED MP1567_TAC_S01 OFF ON 10nF 10nF 1nF 10nF 100 EFFICIENCY (%) 10 100 1000 LOAD CURRENT (mA) MP1567_EC01 Efficiency vs Load Current VIN=5V VIN=4V VIN=3.3V VOUT=1.8V

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER MP1567 Rev. 2.3 www.MonolithicPower.com 2 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM PACKAGE REFERENCE Part Number* Package Temperature MP1567DK MSOP10 –40°C to +85°C * For Tape & Reel, add suffix –Z (eg. MP1567DK–Z) For Lead Free, add suffix –LF (eg. MP1567DK–LF–Z) ABSOLUTE MAXIMUM RATINGS (1) Recommended Operating Conditions (2) MP1567_PD02_QFN10 TOP VIEW BS IN SW PGND SGND EN BP COMP FB SS EXPOSED PAD ON BACKSIDE Part Number Package Temperature MP1567DQ QFN10 (3mm x 3mm) –40°C to +85°C For Tape & Reel, add suffix –Z (eg. MP1567DQ–Z) For Lead Free, add suffix –LF (eg. MP1567DQ–LF–Z) Thermal Resistance (3) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper.

ELECTRICAL CHARACTERISTICS

VIN = 5V, TA = +25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Input Voltage Range V IN 2.6 6 V Input Undervoltage Lockout 2.2 V Input Undervoltage Lockout Hysteresis 100 mV Shutdown Supply Current V EN ≤ 0.3V 0.5 1.0 µA Operating Supply Current V EN > 2V, VFB = 1.1V 1.2 1.8 mA BP Voltage V BP V IN = 2.6 to 6V 2.4 V EN Input Low Voltage V IL 0.4 V EN Input High Voltage V HL 1.5 V EN Hysteresis 100 mV EN Input Bias Current 1 µA Oscillator Switching Frequency f SW 800 KHz Maximum Duty Cycle D MAX V FB = 0.7V 85 % Minimum On Time t ON 200 ns BS IN SW PGND SGND EN BP COMP FB SS TOP VIEW MP1567_PD01_MSOP10

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER MP1567 Rev. 2.3 www.MonolithicPower.com 3 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = +25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Error Amplifier Voltage Gain A VEA 400 V/V Transconductance G EA 300 µA/V COMP Maximum Output Current ±30 µA FB Regulation Voltage V FB 875 905 935 mV FB Input Bias Current I FB FB = 0.9V –100 nA Soft-Start Soft-Start Current I SS 2 µA Output Switch On-Resistance VIN = 5V 265 m Ω Switch On Resistance VIN = 3V 330 m Ω VIN = 5V 220 m Ω Synchronous Rectifier On Resistance VIN = 3V 270 m Ω Switch Current Limit (Source) 1.5 2.0 A Synchronous Rectifier Current Limit (Sink) 350 mA Thermal Shutdown 160 °C TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3V, VOUT = 1.8V, TA = +25°C, unless otherwise noted. MP1567-TPC01 Current Limit vs. Duty Cycle VOUT 50mV/div. ILOAD 0.5A/div. MP1567-TPC02 Load Transient 0.1A to 1A Load Step VSS 1V/div. VOUT 1V/div. IIN 0.5A/div. 2ms/div. MP1567-TPC03 VOUT 1V/div. VSS 1mV/div. IINDUCTOR 1A/div. 2ms/div. MP1567-TPC04 Output Short Circuit IOUT = 1.2A VSW 2V/div. IINDUCTOR 1A/div. MP1567-TPC05 Steady State 2.5 2.0 1.5 1.0 0.5 CURRENT LIMIT (A) 0 2 04 06 08 0 DUTY CYCLE (%)

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER MP1567 Rev. 2.3 www.MonolithicPower.com 4 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM PIN FUNCTIONS Pin# Name Function 1 BS Power Switch Boost. BS powers the gate of the high-side N-Channel power MOSFET switch. Connect a 10nF or greater capacitor between BS and SW. 2 IN Internal Power Input. IN supplies the power to the MP1567 through the internal LDO regulator. Bypass IN to PGND with a 10µF or greater capacitor. Connect IN to the input source voltage. 3 SW Output Switching Node. SW is the source of the high-side N-Channel switch and the drain of the low-side N-Channel switch. Connect the output LC filter between SW and the output. 4 PGND Power Ground. PGND is the source of the N-Channel MOSFET synchronous rectifier. Connect PGND to SGND as close to the MP1567 as possible. 5 SGND Signal Ground. 6 SS Soft-Start Input. Place a capacitor from SS to SGND to set the soft-start period. The MP1567 sources 2µA from SS to the soft-start capacitor at start up. As the voltage at SS rises, the feedback threshold voltage increases to limit inrush current at start up. 7 FB Feedback Input. FB is the inverting input of the internal error amplifier. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. 8 COMP Compensation Node. COMP is the output of the error amplifier. Connect a series RC network to compensate the regulation control loop. 9 BP Internal 2.4V Regulator Bypass. Connect a 10nF capacitor between BP and SGND to bypass the internal regulator. Do not apply any load to BP. 10 EN On/Off Control Input. Drive EN high to turn on the MP1567; low to turn it off. For automatic startup, connect EN to IN. OPERATION The MP1567 measures the output voltage through an external resistive voltage divider and compares that to the internal 0.9V reference to generate the error voltage at COMP. The current-mode regulator uses the voltage at COMP and compares it to the inductor current to regulate the output voltage. The use of current-mode regulation improves transient response and improves control loop stability. At the beginning of each cycle, the high-side N-Channel MOSFET is turned on, forcing the inductor current to rise. The current at the drain of the high-side MOSFET is internally measured and converted to a voltage by the current sense amplifier. That voltage is compared to the error voltage at COMP. When the inductor current raises sufficiently, the PWM comparator turns off the high-side switch and turns on the low-side switch, forcing the inductor current to decrease. The average inductor current is controlled by the voltage at COMP, which in turn, is controlled by the output voltage. Thus the output voltage controls the inductor current to satisfy the load. Since the high-side N-Channel MOSFET requires voltage above V IN to drive its gate, a bootstrap capacitor from SW to BS is required to drive the high-side MOSFET gate. When SW is driven low (through the low-side MOSFET), the BS capacitor is internally charged. The voltage at BS is applied to the high-side MOSFET gate to turn it on, and maintains that voltage until the high-side MOSFET is turned off and the low-side MOSFET is turned on, and the cycle repeats. Connect a 10nF or greater capacitor from BS to SW to drive the high-side MOSFET gate. Using a larger capacitor does little to improve performance.

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER MP1567 Rev. 2.3 www.MonolithicPower.com 5 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM MP1567_BD01 EN IN FB PGND SW L1 BP VBP 2.4V VBP VIN 2.6V to 6V SGND VOUT OFF ON 800KHz OSCILLATOR RAMP PWM COMPARATOR ENABLE CKT & LDO REGULATOR GATE DRIVE REGULATOR UVLO & THERMAL SHUTDOWN CURRENT LIMIT COMPARATOR CONTROL LOGIC Vdr Vdr Vdr SS VFB 0.9V GM ERROR AMPLIFIER CURRENT LIMIT THRESHOLD COMP CURRENT SENSE AMPLIFIER BS Figure 1—Functional Block Diagram

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER MP1567 Rev. 2.3 www.MonolithicPower.com 6 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM

APPLICATION INFORMATION

Internal Low-Dropout Regulator The internal power to the MP1567 is supplied from the input voltage through an internal 2.4V low-dropout linear regulator, whose output is BP. Bypass BP to SGND with a 10nF or greater capacitor to insure the MP1567 operates properly. The internal regulator cannot supply more current than is required to operate the MP1567, therefore do not apply any external load to BP. Soft-Start The MP1567 includes a soft-start timer that slowly ramps the output voltage at startup to prevent excessive current at the input. This prevents premature termination of the battery voltage at startup due to input current overshoot at startup. When power is applied to the MP1567 a 2 µA internal current source charges the external capacitor at SS. As the capacitor charges, the voltage at SS will rise. The MP1567 internally limits the feedback threshold voltage at FB to that of the voltage at SS. This forces the output voltage to rise at the same rate as the voltage at SS, forcing the output voltage to ramp linearly from 0V to the desired regulation voltage during soft-start. The soft-start period is determined by the equation: 5C45.0tSS ×= Where C5 (in nF) is the soft-start capacitor from SS to GND, and t SS (in ms) is the soft-start period. Determine the capacitor required for a given soft-start period by the equation: SSt22.25C ×= Use values for C5 between 10nF and 22nF to set the soft-start period (between 4ms and 10ms). Setting the Output Voltage Set the output voltage by selecting the resistive voltage divider ratio. The voltage divider drops the output voltage to the 0.9V feedback threshold voltage. Use 10k Ω for the low-side resistor of the voltage divider. Determine the high side resistor by the equation: V VV2R FB FBOUT Where R2 is the high-side resistor, R1 is the low-side resistor, VOUT is the output voltage and VFB is the feedback regulation threshold. For R1 = 10kΩ and VFB = 0.9V, then R2(kΩ) = 11.1kΩ (VOUT – 0.9V) Selecting the Input Capacitor The input current to the step-down converter is discontinuous, so a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. A low ESR capacitor is required to keep the noise at the IC to a minimum. Ceramic capacitors are preferred, but tantalum or low ESR electrolytic capacitors will also suffice. Use an input capacitor with a value greater than 10µF. The capacitor can be electrolytic, tantalum or ceramic. However, since it absorbs the input switching current it requires an adequate ripple current rating. Use a capacitor with a RMS current rating greater than 1/2 of the DC load current. For insuring stable operat ion, place the input capacitor as close to the IC as possible. Alternately, a smaller high quality 0.1 µF ceramic capacitor may be placed closer to the IC with the larger capacitor placed further away. If using this technique, it is recommended that the larger capacitor be a tantalum or electrolytic type. All ceramic capacitors should be placed close to the MP1567. Selecting the Output Capacitor The output capacitor is required to maintain the DC output voltage. Low ESR capacitors are preferred to keep the output voltage ripple to a minimum. The characteristics of the output capacitor also affect the stability of the regulation control system. Ceramic, tantalum or low ESR electrolytic capacitors are recommended. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance, and so the

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER MP1567 Rev. 2.3 www.MonolithicPower.com 7 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM output voltage ripple is mostly independent of the ESR. The output voltage ripple is estimated to be: SW LC INRIPPLE f fV4.1V ⎟⎟ ⎛××= Where VRIPPLE is the output ripple voltage, V IN is the input voltage, f LC is the resonant frequency of the LC filter and f SW is the switching frequency. In the case of tantalum or low-ESR electrolytic capacitors, the ESR dominates the impedance at the switching frequency, and so the output ripple is calculated as: ESRRIPPLE RIV ×∆= Where ∆I is the inductor ripple current, and RESR is the equivalent series resistance of the output capacitors. Choose an output capacitor to satisfy the output ripple requirements of the design. A 10 µF ceramic capacitor is suitable for most applications. Selecting the Inductor The inductor is required to supply constant current to the output load while being driven by the switched input voltage. A larger value inductor results in less ripple current that will results in lower output ripple voltage. However, the larger value inductor has a larger physical size, higher series resistance and/or lower saturation current. Choose an inductor that does not saturate under the worst-case load conditions. A good rule for determining the inductance is to allow the peak-to-peak ripple current to be approximately 30% of the maximum load current. Make sure that the peak inductor current (the load current plus half the peak-to-peak inductor ripple current) is below 2A to prevent loss of regulation due to the current limit. Calculate the required inductance value by the equation: IfV )VV(VL SWIN OUTINOUT ∆×× −×= Compensation The system stability is controlled through the COMP pin. COMP is the output of the internal transconductance error amplifier. A series capacitor-resistor combination sets a pole-zero combination to control the characteristics of the control system. The DC loop gain is: ⎛×××= OUT FB LOADCSVEAVDC V VRGAA Where A VEA is the transconductance error amplifier voltage gain, G CS is the current sense gain (roughly the output current divided by the voltage at COMP) and R LOAD is the load resistance (V OUT/IOUT where I OUT is the output load current) The system has 2 poles of importance, one is due to the compensation capacitor (C3), and the other is due to the load resistance and the output capacitor (C2). The first is: 3CA2 Gf VEA EA 1P ××π= Where P1 is the first pole and G EA is the error amplifier transconductance (300 µA/V). The second is: 2CR2 LOAD 2P ××π= The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). The zero is: 3C3R2 1f 1Z ××π= If large value capacitors with relatively high equivalent-series-resistance (ESR) are used, the zero due to the capacitance and ESR of the output capacitor can be compensated by a third pole set by R3 and C4. This pole is: 4C3R2 1f 3P ××π= The system crossover frequency (the frequency where the loop gain drops to 1, or 0dB) is important. Set the crossover frequency to

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER MP1567 Rev. 2.3 www.MonolithicPower.com 8 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM 75KHz or lower to insure stable operation. Lower crossover frequencies result in slower response and worse transient load recovery. Higher crossover frequencies degrade the phase and/or gain margins and can result in instability. Choosing the Compensation Components The values of the compensation components given in Table 1 yield a stable control loop for the output voltage and capacitor given. Table 1—Compensation Values for Typical Output Voltage/Capacitor Combinations VOUT C2 R3 C3 C4 1.8V 4.7 µF Ceramic 3.3k Ω 2.2nF None 2.5V 4.7 µF Ceramic 5.1k Ω 1.5nF None 3.3V 4.7 µF Ceramic 6.8k Ω 1.2nF None 1.8V 10 µF Ceramic 7.5k Ω 1nF None 2.5V 10 µF Ceramic 10k Ω 820pF None 3.3V 10 µF Ceramic 10k Ω 820pF None 1.8V 47µF Tantalum (300mΩ) 10kΩ 2.2nF 1.5nF 2.5V 47µF Tantalum (300mΩ) 10kΩ 3.3nF 1.5nF 3.3V 47µF Tantalum (300mΩ) 10kΩ 4.7nF 1.5nF To optimize the compensation components for conditions not listed in Table 1, use the following procedure. Choose the compensation resistor to set the desired crossover frequency. Determine the value by the following equation: FBCSEA COUT VGG fV2C23R ×× ×××π= Putting in the known constants and setting the crossover frequency to the desired 75KHz: OUT 8 V2C1036.43R ×××≈ In this case, the actual crossover frequency is less than the desired 75KHz, and it is calculated by: OUT FBCSEA C V2C2 VGG3Rf ××π ×××= Choose the compensation capacitor to set the zero to one fourth of the crossover frequency. Determine the value by the following equation: FBCSEA OUT VGG3R V2C43C ××× ××= Determine if the second compensation capacitor, C4, is required. It is required if the ESR zero of the output capacitor occurs at less than four times the crossover frequency, or: 1fR2C8 CESR ≥×××π Where RESR is the equivalent series resistance of the output capacitor. If this is the case, then add the second compensation capacitor. Determine the value by the equation: R2C )MAX(ESR× Where R ESR(MAX) is the maximum ESR of the output capacitor. For Example: Given: VOUT = 1.8V C2 = 10µF Ceramic (ESR = 10mΩ max.) Calculate: (Use the nearest standard value of 7.5kΩ.) nF05.1V8.1F10 109.13C =×µ (Use 1nF since it is a standard value.) 19.0fR2C8 CESR =×××π which is less than 1, therefore the second compensation capacitor (C4) is not required.

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER MP1567 Rev. 2.3 www.MonolithicPower.com 10 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM

PACKAGE INFORMATION

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER NOTICE: The information in this document is subject to change wi thout notice. Please contact MPS for current specifications. Users should warrant and guarantee that th ird party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP1567 Rev. 2.3 www.MonolithicPower.com 11 1/3/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. TM QFN10 (3mm x 3mm)