EUP3484S EUTECH | Alldatasheet
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DS3484S Ver1.2 May 2012 3A, 24V, 340KHz Synchronous Step-Down Converter
DESCRIPTION
The EUP3484S is a synchronous current mode buck regulator capable of driving 3A continuous load current with excellent line and load regulation. The EUP3484S can operate with an input range 4.5V to 24V and the output can be externally set from 0.925V to 18V with a resistor divider. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. In shutdown mode the regulator draws 1 µA of supply current. Programmable soft-start minimizes the inrush supply current and the output overshoot at initial startup. Automatic pulse skipping mode operation increase efficiency at light loads. The EUP3484S require a minimum number of external components. Typical Application Circuit
FEATURES
/circle6 3A Output Current /circle6 Automatic Pulse Skipping Mode at Light Load /circle6 Integrated 160mΩ/110mΩ DMOS Switches /circle6 4.5V to 24V Input Operating Range /circle6 Output Adjustable from 0.925V to 18V /circle6 Up to 95% Efficiency /circle6 1µA Shutdown Current /circle6 Fixed 340KHz Frequency /circle6 Programmable Soft-Start /circle6 Thermal Shutdown and Overcurrent Protection /circle6 Input Supply Undervoltage Lockout /circle6 230ns Minimum On Time /circle6 Available in SOP-8 (EP) Package /circle6 RoHS Compliant and 100% Lead(Pb)-Free Halogen-Free
APPLICATIONS
/circle6 Distributed Power Systems /circle6 Networking Systems /circle6 PC Monitors /circle6 Portable Electronics Figure 1. 12V to 3.3V/5V Application Circuit
DS3484S Ver1.2 May 2012 Pin Configurations Package Type Pin Configurations SOP-8 (EP) Pin Description PIN PIN NAME DESCRIPTION 1 BS High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel DMOS switch. Connect a 0.01µF or greater capacitor from SW to BS to power the high side switch. 2 IN Input Supply Pin. IN supplies the power to the IC, as well as the step-down converter switches. Drive IN with a 4.5V to 24V power source. Bypass IN to GND with a suitably large capacitor to minimize input ripple to the IC. See Input Capacitor Section of the applications notes. 3 SW Power Switching Output. Connect the output LC filter from SW to the output load. 9 (Exposed Pad) GND Ground. GND pin should be connected to the exposed thermal pad for proper operation. This power thermal pad should be connected to PCB ground plane using multiple vias for good thermal performance. 5 FB Output Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage divider connected to it from the output voltage. The feedback threshold is 0.925V. See Setting the Output Voltage . 6 COMP Loop compensation Input. Connect a series RC network from COMP to GND to compensate the regulation control loop. See Compensation. 7 EN Enable Input. EN is a logic input that controls the regulator on or off. Drive EN high to turn on the regulator; low to turn it off. Don’t leave EN pin floating. Directly connect EN to IN (or through a resistance) for automatic startup. 8 SS Soft-Start Control Input. Connect an external capacitor to program the soft-start. If unused, leave it open, which means internal soft-start function.
DS3484S Ver1.2 May 2012
Ordering Information
Order Number Package Type Marking Operating Temperat ure Range EUP3484SDIR1 SOP-8 (EP) xxxxx 3484S -40 °C to +85°C Lead Free Code 1: Lead Free, Halogen-Free Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type D: SOP Block Diagram Figure 2.Functional Block Diagram
DS3484S Ver1.2 May 2012 Absolute Maximum Ratings (1) Recommend Operating Conditions (2) Note(1):Stress beyond those listed under “Absolute Maximum Ratings” may damage the device. Note(2):The device is not guaranteed to function outside the recommended operating conditions.
Electrical Characteristics
The ● denote specifications which apply over the full operating temperature range, otherwise specification are VIN=12V , TA =25°C unless otherwise specified. EUP3484S Parameter Conditions Min Typ Max. Unit Shutdown Supply Current V EN =0V 1 5 µA Supply Current V FB =1V 0.45 0.9 mA Error Amplifier V oltage Gain 360 V/V Error Amplifier Transconductance ∆IC = ±10µA 800 µA/V High-Side Switch On-Resistance 160 m Ω Low-Side Switch On-Resistance 110 m Ω High-Side Switch Leakage Current V EN =0V , V SW =0V 5 µA Upper Switch Current Limit Minimum Duty Cycle 3.8 5.5 A Lower Switch Current Limit From Drain to Source 0 A COMP to Current Sense Transconductance 7.5 A/V Oscillation Frequency 300 340 380 KHz Short Circuit Oscillation Frequency V FB =0V 110 KHz Maximum Duty Cycle V FB =0.7V 90 % Minimum On Time 230 ns EN Disable Threshold ● 0.36 1.5 2.0 V 2.3 2.5 2.8 EN Lockout Threshold V EN Rising ● 2 2.5 3 V EN Lockout Threshold Hysteresis 210 mV Input Under V oltage Lockout Threshold VIN Rising 3.8 4.1 4.4 V Soft-Start Charge Current V SS =0V 6 µA Thermal Shutdown 160 °C
DS3484S Ver1.2 May 2012 Typical Operating Characteristics (See Figure1, C1 =10µF, C2=22µF× 2, L=10µH, TA =+25°C)
DS3484S Ver1.2 May 2012 Typical Operating Characteristics (continued) (See Figure1, C1 =10µF, C2=22µF× 2, L=10µH, TA =+25°C)
DS3484S Ver1.2 May 2012 Typical Operating Characteristics (continued) (See Figure1, C1 =10µF, C2=22µF× 2, L=10µH, TA =+25°C)
DS3484S Ver1.2 May 2012 Functional Description The EUP3484S regulates input voltages from 4.5V to 24V down to an output voltage as low as 0.925V , and supplies up to 3A of load current. The EUP3484S uses current-mode control to regulate the output voltage. The output voltage is measured at FB through a resistive voltage divider and amplified through the internal transconductance error amplifier. The voltage at the COMP pin is compared to the switch current (measured internally) to control the output voltage. The converter uses internal N-Channel MOSFET switches to step-down the input voltage to the regulated output voltage. Since the high side MOSFET requires a gate voltage greater than the input voltage, a boost capacitor connected between SW and BS is needed to drive the high side gate. The boost capacitor is charged from the internal 5V rail when SW is low. At light loads, the inductor current may reach zero or reverse on each pulse. The bottom DMOS is turned off by the current reversal comparator and the switch voltage will ring. This is discontinuous mode operation, and is normal behavior for the switching regulator. At light load, the EUP3484S will automatically skip pulses in pulse skipping mode operation to maintain output regulation and increases efficiency. When the FB pin voltage exceeds 15% of the nominal regulation value of 0.925V , the over voltage comparator is tripped and forcing the high-side switch off.
Application Information
Setting the Output Voltage The output voltage is set using a resistive voltage divider connected from the output voltage to FB. The voltage divider divides the output voltage down to the feedback voltage by the ratio: Thus the output voltage is: R2 can be as high as 100k Ω, but a typical value is 10k Ω. Using the typical value for R2, R1 is determined by: For example, for a 3.3V output voltage, R2 is 10k Ω and R1 is 26.1kΩ. Inductor The inductor is required to supply constant current to the load while being driven by the switched input voltage. A larger value inductor will result in less ripple current that will in turn result in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. A good rule for determining inductance is to allow the peak-to-peak ripple current to be approximately 30% of the maximum switch current limit. Also, make sure that the peak inductor current is below the maximum switch current limit. The inductance value can be calculated by: Where V OUT is the output voltage, V IN is the input voltage, f S is the switching frequency, and ∆IL is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current, calculated by: Where I LOAD is the load current. The choice of which style inductor to use mainly depends on the price vs. size requirements and any EMI constraints. Optional Schottky Diode During the transition between the high-side switch and low-side switch, the body diode of the low-side power MOSFET conducts the inductor current. The forward voltage of this body diode may be high and cause efficiency loss. An optional small 1A Schottky diode B130 in parallel with low-side switch is recommended to improve overall efficiency when input voltage is higher. Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors will also suffice. Choose X5R or X7R dielectrics when using ceramic capacitors. Since the input capacitor (C1) absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: The worst-case condition occurs at V IN = 2V OUT , where IC1 = I LOAD /2. For simplification, use an input capacitor with a RMS current rating greater than half of the maximum load current. R2 R1 OUT VFB V 2R1R925 . 0OUT V +∗= IN V OUT V LSf2 OUT V LOAD ILP I IN V OUT V LISf OUT V L −∗∗= IN V OUT V IN V OUT V LOAD I1CI
DS3484S Ver1.2 May 2012 The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1µF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple for low ESR capacitors can be estimated by: Where C1 is the input capacitance value. For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: Where C2 is the output capacitance value and R ESR is the equivalent series resistance (ESR) value of the output capacitor. When using ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance which is the main cause for the output voltage ripple. For simplification, the output voltage ripple can be estimated by: When using tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: The characteristics of the output capacitor also affect the stability of the regulation system. The EUP3484S can be optimized for a wide range of capacitance and ESR values. Compensation Components EUP3484S employs current mode control for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. COMP is the output of the internal transconductance error amplifier. A series capacitor- resistor combination sets a pole-zero combination to govern the characteristics of the control system. The DC gain of the voltage feedback loop is given by: Where V FB is the feedback voltage (0.925V), A VEA is the error amplifier voltage gain, G CS is the current sense transconductance and R LOAD is the load resistor value. The system has two poles of importance. One is due to the compensation capacitor (C3) and the output resistor of the error amplifier, and the other is due to the output capacitor and the load resistor. These poles are located at: Where G EA is the error amplifier transconductance. The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: In this case, a third pole set by the compensation capacitor (C4) and the compensation resistor (R3) is used to compensate the effect of the ESR zero on the loop gain. This pole is located at: The goal of compensation design is to shape the converter transfer function to get a desired loop gain. The system crossover frequency where the feedback OUT V FB V EA VACS GLOAD RVDC A ∗∗∗= VEA AC3 2π EA G P1 f LOAD RC2 2π P2 f R3 C3 2π Z1 f ESR RC2 2 ESR f ∗∗π= R3 C4 2 P3 f ∗∗π= −∗∗ V IN V OUT 1 V IN V OUT Sf1C LOAD I IN ∆V ∗∗+∗ C2 Sf8 ESR R IN V OUT V LSf OUT V OUT ∆V ∗∗∗ IN V OUT V 2CL2 Sf8 OUT V OUT V ESR R IN V OUT V LSf OUT V OUT V ∗−∗ =Δ
- Choose the compensation resistor (R3) to set the
desired crossover frequency. typically below one tenth of the switching frequency.
- Choose the compensation capacitor (C3) to achieve
frequency provides sufficient phase margin. Where R3 is the compensation resistor.
- Determine if the second compensation capacitor
improve the efficiency of the regulator. Figure 3. Add Optional External Bootstrap Diode
DS3484S Ver1.2 May 2012 Packaging Information SOP-8 (EP) Remark: Exposed pad outline drawing is for reference only. MILLIMETERS INCHES SYMBOLS MIN. Normal MAX. MIN. Normal MAX. A 1.35 - 1.75 0.053 - 0.069 A1 0.00 - 0.25 0.000 - 0.010 L 0.40 - 1.27 0.016 - 0.050 b 0.31 - 0.51 0.012 - 0.020 e 1.27 0.050