FAN5236_10 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
Highly Flexible, Dual Synchronous Switching PWM Controller that Includes Modes for: - DDR Mode with In-phase Operation for Reduced Channel Interference - 90° Phase-shifted, Two-stage DDR Mode for Reduced Input Ripple - Dual Independent Regulators, 180° Phase Shifted Complete DDR Memory Power Solution - VTT Tracks VDDQ/2 - VDDQ/2 Buffered Reference Output Lossless Current Sensing on Low-side MOSFET or Precision Over-Current Using Sense Resistor VCC Under-Voltage Lockout Converters can Operate from +5V or 3.3V or Battery Power Input (5V to 24V) Excellent Dynamic Response with Voltage Feedforward and Average-Current-Mode Control Power-Good Signal Supports DDR-II and HSTL Light-Load Hysteretic Mode Maximizes Efficiency TSSOP28 Package
Applications
DDR VDDQ and VTT Voltage Generation Mobile PC Dual Regulator Server DDR Power Hand-held PC Power Related Resources Application Note — AN-6002 Component Calculations and Simulation Tools for FAN5234 or FAN5236 Application Note — AN-1029 Maximum Power Enhancement Techniques for SO-8 Power MOSFET
Description
The FAN5236 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range of 0.9V to 5.5V required to power I/O, chip-sets, and memory banks in high-performance notebook computers, PDAs, and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to high efficiency over a wide range of loads. The Hysteretic Mode can be disabled separately on each PWM converter if PWM Mode is desired for all load levels. Efficiency is enhanced by using MOSFET R DS(ON) as a current-sense component. Feedforward ramp modulation, average-current-mode control scheme, and internal feedback compensation provide fast response to load transients. Out-of-phase operation with 180-degree phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR mode, one of the channels tracks the output voltage of another channel and provides output current sink and source capability — essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5236 monitors these outputs and generates separate PGx (power good) signals when the soft-start is completed and the output is within ±10% of the set point. Built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over-voltage conditions cease. Under-voltage protection latches the chip off when output drops below 75% of the set value after the soft- start sequence for this output is completed. An adjustable over-current f unction monitors the output current by sensing the voltage drop across the lower MOSFET. If precision current -sensing is required, an external current-sense resistor may be used.
Figure 3. Pin Configuration measured with respect to this pin. 4 SW1 Switching Node. Return for the high-side MOSFET driver and a current sense input.
6 BOOT1
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 4.
23 BOOT2
11 ILIM1 Current Limit 1. A resistor from this pin to GND sets the current limit.
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5236 • Rev. 1.3.2 4 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Pin Descriptions (Continued) Pin # Name Description 13 DDR DDR Mode Control. HIGH = DDR Mode. LOW = two separate regulators operating 180° out of phase.
14 VIN
Input Voltage. Normally connected to battery, providing voltage feedforward to set the amplitude of the internal oscillator ramp. When us ing the IC for two-step conversion from 5V input, connect through 100KΩ resistor to ground, which sets the appropriate ramp gain and synchronizes the channels 90° out of phase. 15 PG1 Power Good Flag. An open-drain output that pulls LOW when V SEN is outside a ±10% range of the 0.9V reference.
16 PG2 /
Power Good 2. When not in DDR Mode, open-drain output that pulls LOW when the VOUT is out of regulation or in a fault condition. Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the VDDQ/2 reference.
18 ILIM2 / REF2
Current Limit 2. When not in DDR Mode, a resistor from this pin to GND sets the current limit. Reference for reg #2 when in DDR Mode. Typically set to VOUT1 / 2.
28 VCC
VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling).
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5236 • Rev. 1.3.2 5 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC V CC Supply Voltage 6.5 V VIN V IN Supply Voltage 27 V BOOT, SW, ISNS, HDRV 33 V BOOTx to SWx 6.5 V All Other Pins -0.3 V CC+0.3 V TJ Junction Temperature -40 +150 ºC TSTG Storage Temperature -65 +150 ºC TL Lead Temperature (Soldering,10 Seconds) +300 ºC Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VCC V CC Supply Voltage 4.75 5.00 5.25 V VIN V IN Supply Voltage 24 V TA Ambient Temperature -10 +85 °C ΘJA Thermal Resistance, Junction to Ambient 90 °C/W
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5236 • Rev. 1.3.2 6 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Electrical Characteristics
Recommended operating conditions, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Power Supplies IVCC V CC Current LDRV, HDRV Open, VSEN Forced Above Regulation Point 2.2 3.0 µA Shutdown (EN-0) 30 µA ISINK V IN Current, Sinking V IN = 24V 10 30 µA ISOURCE V IN Current, Sourcing V IN = 0V -15 -30 µA ISD V IN Current, Shutdown 1 µA VUVLO UVLO Threshold Rising VCC 4.30 4.55 4.75 V Falling 4.10 4.25 4.45 V VUVLOH UVLO Hysteresis 300 mV Oscillator fosc Frequency 255 300 345 KHz VPP Ramp Amplitude VIN = 16V 2 V VIN = 5V 1.25 V VRAMP Ramp Offset 0.5 V G Ramp / V IN Gain VIN ≤ 3V 125 mV/V 1V < VIN < 3V 250 mV/V Reference and Soft Start VREF Internal Reference Voltage 0.891 0.900 0.909 V ISS Soft-Start Current At Startup 5 µA VSS Soft-Start Complete Threshold 1.5 V PWM Converters Load Regulators I OUTX from 0 to 5A, VIN from 5 to 24V -2 +2 % ISEN V SEN Bias Current 50 80 120 nA VOUT Pin Input Impedance 45 55 65 KΩ UVLOTSD Under-Voltage Shutdown % of Set Point, 2µs Noise Filter 70 75 80 % UVLO Over-Voltage Threshold % of Set Point, 2µs Noise Filter 115 120 125 % ISNS Over-Current Threshold RILIM= 68.5KΩ, Figure 12 112 140 168 µA Output Drivers HDRV Output Resistance Sourcing 12.0 15.0 Ω Sinking 2.4 4.0 LDRV Output Resistance Sourcing 12.0 15.0 Ω Sinking 1.2 2.0 Continued on following page…
Figure 4. IC Block Diagram
19 VSEN2
26 PGND2
10 VSEN1
Figure 5. DDR Regulator Application Table 1. DDR Regulator BOM
- Suitable for typical notebook computer app lication of 4A continuous, 6A peak for VDDQ. If continuous operation
Section and use AN-6002 for design calculations.
Figure 6. Dual Regulator Application Table 2. DDR Regulator BOM
1 Capacitor 68µf, Tantalum, 25V, ESR 95mΩ 1 C1 AVX TPSV686*025#095
2 Capacitor 10nf, Ceramic 2 C2, C3 Any
4 Capacitor 150nF, Ceramic 2 C5, C7 Any
5 Capacitor 330µf, Poscap, 4V, ESR 40mΩ 2 C6, C8 Sanyo 4TPB330ML
27 Schottky Diode 30V 2 D1, D2 Fairchild
29 Dual MOSFET with Schottky 1 Q1 Fairchild
30 DDR Controller 1 U1 Fairchild
- If currents above 4A continuous are required, use single SO-8 packages. For more information, refer to the
Power MOSFET Selection Section and AN-6002 for design calculations.
where t0.9 is in seconds if CSS is in μF. is forced into PWM Mode during soft-start. effective switching frequency. node and settles out at the value of the output voltage. Figure 11. Transitioning Between PWM and Hysteretic Mode changed to PWM on the next clock cycle. the diode to block reverse conduction. Output inductor and capacitor ESR.
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5236 • Rev. 1.3.2 15 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Design and Component Selection Guidelines As an initial step, define operating input voltage range, output voltage, and minimum and maximum load currents for the controller. Setting the Output Voltage The internal reference voltage is 0.9V. The output is divided down by a voltage divider to the VSEN pin (for example, R5 and R6 in Figure 5). The output voltage therefore is: V9.0V V9.0 OUT = (12) To minimize noise pickup on this node, keep the resistor to GND (R6) below 2K; for example, R6 at 1.82KΩ. Then choose R5: ( )( ) K24.39.0 9.0VK82.1 5R OUT = = (13) For DDR applications converting from 3.3V to 2.5V or other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converter’s FPWM to GND. When converter’s FPWM is at GND, the converter’s maximum duty cycle is greater than 90%. When using as a DDR converter with 3.3V input, set up the converter for in-phase synchronization by tying the VIN pin to +5V. Output Inductor Selection The minimum practical output inductor value keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. At light load, the controller can automatically switch to Hysteretic Mode of operation to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor: ESR V 12I OUT MIN Δ ×=Δ = (14) where ΔI is the inductor ripple current and ΔVOUT is the maximum ripple allowed: IN OUT SW OUTIN V V If VV L ×Δ× = (15) for this example, use: KHz300f A2.1A6•%20I 5.2V,20V SW OUTIN ==Δ (16) therefore: µH6L ≈ (17) Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor, it filters the sequence of pulses produced by the switcher and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, inductor ripple current ( ΔI), and the allowable ripple voltage (ΔV): I VESR Δ Δ< (18) In addition, the capacitor’s ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 6 is 120mV PP. Some additional ripple appears due to the capacitance value itself: SWOUT f8C IV ×× Δ=Δ (19) which is only about 1.5mV, for the converter in Figure 6, and can be ignored. The capacitor must also be rated to withstand the RMS current, which is approximately 0.3 X ( ΔI), or about 400mA for the converter in Figure 6. High-frequency decoupling capacitors should be placed as close to the loads as physically possible Input Capacitor Selection The input capacitor should be selected by its ripple current rating. Two-Stage Converter Case In DDR Mode (shown in Figure 5), the V TT power input is powered by the VDDQ output; therefore, all of the input capacitor ripple current is produced by the V DDQ converter. A conservative estimate of the output current required for the 2.5V regulator is: I II VTT VDDQREGI += (20) As an example, if the average I VDDQ is 3A and average IVTT is 1A, I VDDQ current is about 3.5A. If average input voltage is 16V, RMS input ripple current is: )MAX(OUTRMS DDII −= (21) where D is the duty cycle of the PWM1 converter: 5.2 V V D IN OUT =< (22) therefore: A49.116 5.2 5.25.3I RMS =⎟ −= (23)
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5236 • Rev. 1.3.2 17 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller For the high-side MOSFET, V DS = VIN, which can be as high as 20V in a typical portable application. Care should be taken to include the delivery of the MOSFET’s gate power (PGATE) in calculating the power dissipation required for the FAN5236: SWCCGATEG fVQP ××= (32) where QG is the total gate charge to reach VCC. Low-Side Losses Q2, however, switches on or off with its parallel Schottky diode conducting; therefore V DS ≈ 0.5V. Since PSW is proportional to V DS, Q2’s switching losses are negligible and Q2 is selected based on RDS(ON) only. Conduction losses for Q2 are given by: () )ON(DSOUTCOND RID1P 2 ××−= (33) where R DS(ON) is the R DS(ON) of the MOSFET at the highest operating junction temperature, and: IN OUT V V D = (34) is the minimum duty cycle for the converter. Since D MIN < 20% for portable computers, (1-D) ≈ 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (P D(MAX)) is a function of the maximum allowable die temperature of the low-side MOSFET, the ΘJA, and the maximum allowable ambient temperature rise: JA )MAX(A)MAX(J )MAX(D TT P Θ = (35) ΘJA depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC Application Note AN-1029 — Maximum Power Enhancement Techniques for SO-8 Power MOSFETs) Layout Considerations Switching converters, even during normal operation, produce short pulses of current that could cause substantial ringing and be a source of EMI if layout constraints are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rates and are noise generators. The low-power components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high-dV/dt voltage swing; such as SW, HDRV, and LDRV. All surrounding circuitry tends to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use high- density interconnect systems, or micro-vias, on these signals. The use of blind or buried vias should be limited to the low-current signals only. The use of normal thermal vias is at the discretion of the designer. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components, like the soft-start capacitor and current sense re sistors, as close as possible to the respective pins of the IC. The FAN5236 utilizes advanced packaging technology with lead pitch of 0.6mm. High-performance analog semiconductors utilizing narrow lead spacing may require special consi derations in design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices.
Figure 19. 28-Lead, Thin Shrink Outline Package specifically the warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/.
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5236 Rev. 1.3.2 19 FAN5236 — Dual Mobile-Friendly DDR/Dual-Output PWM Controller