ETC9310

ETC9311 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

{57 SGS-THOMSON = _ETC9410/ETC9411 ‘TF iwicrosuscrnomies _ETC9310/ETC9311 CMOS MICROCONTROLLERS « LOWEST POWER DISSIPATION (40yW typical) « LOW COST «= POWER SAVING HALT MODE WITH CON- ETC9410/ETC9310 TINUE FUNCTION = POWERFUL INSTRUCTION SET 2 512x 8 ROM, 32 x4 RAM LE. = 20 VO LINES (ETC9410) i oy. N « TWO-LEVEL SUBROUTINE STACK ey hog (Plastic Package) = DC TO 4us INSTRUCTION TIME Nita, = SINGLE SUPPLY OPERATION (2.4V to 5.5V) ny = GENERAL PURPOSE AND TRI-STATE® OUT- PUTS = INTERNAL BINARY/COUNTER REGISTER WITH MICROWIRE®@ COMPATIBLE SERIAL vo = LSTTLUCMOS COMPATIBLE IN AND OUT ETC9411/ETC9311 » SOFTWARE/HARDWARE COMPATIBLE WITH OTHER MEMBERS OF THE ET9400 FAMILY = EXTENDED TEMPERATURE (- 40°C to + 85°C) Hy = S.O.1.C. 20/24 PACKAGE AVAILABLE Haha (Plastic Package)

DESCRIPTION

The ETC9410, C9411,C9310, and C9311, fully Static, Single-Chip CMOS Microcontrollers are fully compatible with the COPS® family, fabricated using PIN CONNECTIONS double-poly, silicon gate CMOS technology. These Controller Oriented Processors are complete micro- ws computers containing all system timing, internal wo]? 241) v0 logic, ROM, RAM, and /O necessary to implement exo]? 2D or dedicated control functions in a variety of applica- cx 3 2H oe tions. Features include single supply operation, a acer He variety of output configuration options, with an ins- RESET 21H og truction set, intemal architecture and /O scheme a7 Qs af cs designed to facilitate keyboard input, display output tes ETO 4h co and BCD data manipulation. The ETC9411 is ident- es Pe ical to the ETC9410 but with 16 I/O lines instead of 20. They are an appropriate choice for use in numer- Cs 17) Go ous human interface control environments. Stan- Yee Ys wwf] sk dard test procedures and reliable high-density Ls Go 15} so fabrication techniques provide the medium to large edn ts! volume customers with a customized Controller 1 Oriented Processor at a low end-product cost. U1 Qi 13} to The ETC9310/C9311 is the extended temperature range version of the ETC9410/C9411. April 1989 wet

Figure 1 : Block Diagram (24-pin version). i Bog 48 @ Bess (} CSI — HEE} HN 28 ees ses} |°3"8 2 35H z AE =] Seg. > $ 2-4 an 4 neo Oq| ° Fae Go S| mh ES clean = {s]--- 2 . | ds Bj Las g: | |3< Dan pea a = se 3 8 ced =| |= [a]e> s & £ Sees

8 LL g--s

Fj [s]—- 5 8 = fa 2 v4 2 3 o g 23 Fy Fae 9 8 5 6~U) 8 2 - 2.) 2 22 4 « sO eeel fa eo Fy - EE oa Ed ne H 23 ° E eet Gy SSS-THOMsON

3 SY/ imicroascrmoncs

[vs [supply Voltage Veo) Ambient Operating Temperature Ambient Storage Temperature | -e5t0+150_ | oo Lead Temperature (soldering, 10 seconds) |__| Total Source Current sm Total Sink Current [as ma Absolvie maximum ratings indicate limits Beyond which damage tothe device may occur. DC and AG electrical specications are not ensured when operating the device al absolute maximum ratings OF ststomson SY/ facnoa.ecrnomes

£TC9410/9411-ETC9310/9311 DC ELECTRICAL CHARACTERISTICSO’C < T, < + 70°C (unless otherwise specified) [Parameter | TestConaitions |i. [| Max | Units | [Operating Votage | Cie | Power Supply Ripple (note 5) [ PeakioPeak | | tVee || ‘Supply Current (note 1) Veco = 2.4V, te = 125s 40 HA Voc =5.0V, tc = 16s 500 nA Veo = 5.0V, tc = 4us 2000 HA ({c is the instruction cycle time) HALT Mode Current (note 2) Voc = 5.0V, Fin = kHz 15 HA Voc =2.4V, Fin = OkHZ 6 nA Input Voitage Levels RESET, CKI Logic High 0.9Vce v Logic Low 0.1Vce v All Other Inputs: Logic High O.7%Vcc v Logic Low 02Vco v Hi-Z Input Leakage foo +1 A Input Capacitance +7 pF Output Voltage Levels Standard Outputs LSTTL Operation Voc = 5.0V + 5% Logic High IOH =- 252A 27 v Logic Low IOL = 400A Vv CMOS Operation Logic High lou == 10nA Voo-0.2 v Logic Low lou = 10HA Vv Output Current Levels (except CKO) Sink (note 6) Voc = 4.5V, Vour = Veo 12 mA Voc =2.4V, Vout = Veo 02 mA Source (standard option) Veo = 4.5V, Vour = OV os mA | Vcc = 2.4V, Vout = OV 04 mA ‘Source (low current option) Veo = 4.5V, Vout = OV 30 330 LA Voc = 2.4V, Vout = OV 6 80 HA CKO (as clock out) Current Levels Sink Veo = 4.5V, CKI = Vec, Vout = Veo 03 mA divide by 4 06 mA divide by 8 12 mA | divide by 16 Source Veo = 4.8V, CKI = Vee, Vour = 0 03 mA divide by 4 06 mA | divide by 8 12 mA divide by 16 ‘Allowable Loading on CKO (as HALT) Current needed to over-ride HALT | (note 3) 100 pF To continue Voc = 4.5V, VIN = 2Vec 6 mA To halt Veo = 4.5V, VIN = 7Vcc 1.6 mA TRI-STATE® or open drain leakage +2 HA [current “ey ses-tHomson iicRoELECTROMICE

AC ELECTRICAL CHARACTERISTICS 0°C < T, < + 70°C (unless otherwise specified) [____ Parameter | Test Conditions | Min. | Max. | Units | Instruction Cycle Veo 2 4.5V oc Time = tc 45V > Voo 2 24V oc ‘Operating CKI Frequency + 4 Mode Dc 1.0 MHz + 8 Mode Vec > 4.5 ined 2.0 MHz + 16 Mode pc 4.0 MHz + 4Mode oc 250 kHz + 8 Mode Veo 2 2.4V oc 500 kHz + 16 Mode oc 1.0 MHz Instruction Cycle R = 30k 45%, Voc =5V Time - CKI (RC) (note 4) C = 82pF + 5% (+ 4 mode) bs INPUTS : (see tig. 3) tserue G Inputs tc/4 =+ 0.7 us SI Input Veo 2 4.5V 03 us All Others | 17 us thovo Veo 2 4.5V 0.25 hs Veo 2 2.4V 10 us OUTPUT | Propagation Delay (see fig. 3) Vout = 1.5V, Cu = 100pF, Ru =5K | teor, teoo Vec 2 4.5V | 10 hs teor, tpoo Voc 2 2.4V 40 us Note: 1. Supply current is measured after running for 2000 cycle times with a square-wave clock on CK!, CKO open, and all other pins pulled up to Voc with 20k resistors. 2 The HALT mode wil stop Cki from oscillating inthe RC and crystal coiigurations. 3. When forcing HALT, current is only needed tor a short time (approx. 200ns) to flip the HALT flip-flop. 4, This parameter is only sampled and not 100% tested. 5 Vottage change must be les than 05 vol in a ims period. 6. SO output sink current must be kmited to keep Vo. below 0.2 Veo when por is running in order to prevent entering test mode ETC9310/ETC931i ABSOLUTE MAXIMUM RATINGS [Symbol] SSS Parameter —SSSCSCSCS~wCS aw —* Supply Vottage (Vcc) ee ee [ota Alowabe Source Gur ee a |__| Total allowable Sink Current [a5 ma Operating Temperature Range = 40 to + 85 Absolute maximum ratings indicate limits beyond which damage to the device may occur. OC and AC electrical specications are not ensured when operating the device at absolute maximum ratings 521 SY7 imcromactromce at

DC ELECTRICAL CHARACTERISTICS — 40°C < T, < + 85°C (unless otherwise specified) Parameter Test Conditions Min. | Max. | Units | Power Supply Role (now 6) | PeakioPeak «| S| tee (| ‘Supply Current (note 1) Veo = 3.0V, te = 125us 60 pA Voc = 5.0V, te = 16s 600 pA Voc = 5.0V, te = 4us 2500 pA (tc is the instruction cycle time) HALT Mode Current (note 2) Vec = 5.0V, Fin = OKHz uA Voc = 3.0V, Fin = OkHz WA Input Voltage Levels RESET, CKI Logic High 0.9Vec v | Input Logic Low 0.1Veo v | All Other Inputs Logic High 0.7Vce v Logic Low 0.2Vcc v ‘Output Voltage Levels ‘Standard Outputs LSTTL Operation Voc = 5.0V + 5% Logie High Jon = 25uA 27 v Logic Low Tox = 400A 04 v CMOS Operation Logic High low =— 10HA Vec~0.2 v Logic Low lou = 10HA 02 Vv Output Current Levels ‘Sink (note 6) Voc =4.5V, Vou = Veco 12 mA Voc = 3.0V, Vour = Veo 02 mA Source (standard option) Veo = 4.5V, Vou = OV 0s mA Voc = 3.0V, Vour = OV 0.1 mA Source (low current option) Voc = 4.5V, Vour = 0V 30 | 440 pA Voc = 3.0V, Vour = OV 8 200 pA ‘CKO Current Levels (as clock out) Sink 4 Vec = 4.5V, CKI = Voc, Vour = Veo 03 mA | +8 06 mA +16 120 | mA Source + 4 Voc = 4.5V, CKI = OV, Vour = OV 03 mA + 8 06 mA +16 12 mA Allowable Loading on CKO (as HALT| 100 pF VO pin) Current needed to override HALT (note 3) to continue Voc = 4.5V, Vin = 0.2Vco 08 mA to halt Veo = 4.5V, Vin = 0.7Vce 2.0 mA TRI-STATE or Open Drain Leakage +4 pA Current _

62 L577 Scs:THOMSON

AC ELECTRICAL CHARACTERISTICS — 40°C <T, < + 85°C (unless otherwise specified) [Parameter Test Conditions [ min. [7 Max. | units | Instruction Cycle Time (tc) Voc s 4.5V oc 4.5V > Voc 2 3.0V oc Operating CKI Frequency = 4 Mode oc 1.0 MHz + 8 Mode} Vcc 2 4.5V bc 2.0 MHz + 16 Mode oc 4.0 MHz + 4Mode bc 250 kHz + 8 Mode] 4.5V > Vcc 2 3.0V oc 500 KHz + 16 Mode ed 1.0 MHz Instruction Cycle Time R = 30k + 5%, Voc =5V us. RC Oscillator (note 4) C = 82pF + 5% (= 4 mode) Inputs (see figure 3) tserue G Inputs tela =+ 0.7 us SI Input Vec>45V | 03 us All Others 17 us tHoLo Voc 2 4.5V 0.25 us Voc 2 3.0V. 1.0 us ‘Output Propagation Delay Vout = 1.5V, C = 100pF, Ru = 5K teor, tpoo Veo 2 4.5V 1.0 us teo1, tpoo Voc 2 3.0V 4.0 ts Note : 1. Supply currents measured ater ning for 2000 eycle umes with a square-ware cock on CK, CKO open, and all oter pins pulled Upto Vor with 20k resistors 2. The HALT mode wil stop CKI from oscilatng inthe RC and cyst confgurations. 3. When forcing HALT, curents only needed fora short ime (approximately 200ns) to fip the HALT fip-op, 4. This parameter is only sampled and not 100% tested, 5. Vollage change must be less than 0.5 voltin a ims period 6. SO output srk curent must be limited to keep Va. below 0.2Voc when pots running in order to prevent entering test mode FUNCTIONAL DESCRIPTION ROM ADDRESSING To ease reading of this description, only ETC9410 ROMaddressing is accomplished by a 9-bit PC reg- and/or ETC9411 are referenced ; however, all such _ister. Its binary value selects one of the 512 8-bit references apply equally to ETC9310 and/or — words contained in ROM. A new address is loaded ETC9311. into the PC register during each instruction cycle. A block diagram of the ETC9410 is given in figure Unless the instruction isa transfer of control instruc- 1. Data paths are illustrated in simplified form tode- _ tion, the PC register is loaded with the next sequen- pict how the various logic elements communicate _ tial 9-bitbinary count value. Two levels of subroutine with each other in implementing the instruction set Nesting are implemented by two 9-bit subroutine of the device. Positive logic is used. When a bit is Save registers, SA and SB. set, itis logic "1" when a bit is reset, itis a logic"0". ROM instruction words are fetched, decoded, and executed by the Instruction Decode, Control and PROGRAM MEMORY Skip Logic dreuitry. Program memory consists of a 512-byte ROM. As can be seen by an examination of the ETC9410/¢ -: DATA MEMORY 9411 instruction set, these words may be program Data memory consists of a 128-bit RAM, organized instructions, program data, or ROM addressing —_as 4 data registers of 8 x 4-bit digits. RAM address- data. Because of the special characteristics associ-__ingis implemented by a 6-bit B register whose upper ated with the JP, JSRP, JID, and LQID instructions, 2 bits (Br) select 1 of 4 data registers and lower 3 ROM must offen be thought of being organized into _bits of the 4-bit Bd select 1 of eight 4-bit digits in the 8 pages of 64 words (bytes) each. selected data register. While the 4-bit contents of YU incnoaacronce 3

the selected RAM digit (M) are usually loaded into The most significant bit of Bd is not used to select a or from, or exchanged with, the A register (accumu- RAM digit. Hence, each physical digit of RAM may lator), they may also be loaded into the Qlatches or _be selected by two different values of Bd as shown loaded from the L ports. RAM addressing may also _in figure 4 below. The skip condition for XIS and XDS be performed directly by the XAD 3, 15 instruction. _instructions will be true if Bd changes between 0 and The Bd register also serves as a source register for 15, but NOT between 7 and 8 (see table 3). 4-bit data sent directly to the D outputs. Figure 2 : Pin Connections. ow fr 7 xb ow , cxo [2 zai or ut af) is oi 3 2) v2 Vec 2 wf us ese Qa 21f} os os wef) 7 os 2D os ws v7] Reser wO6 ercoaio 190 a2 u QseTc o41n6D) cx ts(]7 ETC9310 yf] g, vo PeETCS316 bo us 70 co sQ7 4] or vec G9 161) sx sos 13) ez

6 Qo 181] so sx (Jo woe

en wos eno []10 nD co u Qe 13[]} Lo Figure 2 : Pin Connections. [pin [oi seription [_Ds-Do_| 4 General Purpose Outputs (D1-Do for20pin package) [si | Serial input or countering) i [so __| Serial Output (or general purpose output) Logic-controlied Clock (or general purpose output) gat Gy S&s:THomson ASSO) ncposzctncnc8 |

Figure 3 : Input/output Timing Diagrams (divide-by-8 mode). [+-_—wstaucnon crete me #9 —+ LOU UU LULL AA eon = ‘p00 Saleen Von You Gy-Gp.L7-Lo, Fe —'serup—-4 Hou 3 shtuPut ZLZZZZL0 ZL DEEK—————XZPZETEOETTL. 3-G9.D3-Dp, | ksi = eo Uy-tg $0. SK Vou fo Sireurs The D register provides 4 general purpose outputs at Sl is shifted into the least significant bit of SIO. and is used as the destination register for the 4-bit ‘SO can be enabled to output the most significant contents of Bd. bit of SIO each instruction cycle time. (See 4 ‘The XAS instruction copies C into the SKL Latch. In below). The SK output becomes a logic control- the counter mode, SK is the output of SKL ; in the led clock. shift register mode, SK is a sync clock, inhibited 2. EN1 is not used, it has NO effect on the when SKL is a logic "0". ETC9410/C9411. The EN register is an internal 4-bit register loaded 3. With EN2 set, the L drivers are enabled to out- under program control by the LEI instruction. The put the data in Q to the L V/O ports. Resetting state of each bit of this register selects or deselects EN2disablestheL drivers, placing the L /O ports the particular feature associated with each bit of the ina hight impedance input state. EN register (EN3-ENo). 4. EN3, in conjunction with ENO, affects the SO out- 1. The least significant bit of the enable register, put. With ENO set (binary counter option se- ENO, selects the SIO register as either a 4-bit lected), SO will output the value loaded into EN3. shift register or as a 4-bit binary counter. With With ENO reset (serial shift register option se- ENO set, SIO isan asynchronous binary counter, lected), setting EN3 enables SO as the output of DECREMENTING its value by one upon each the SIO shift register, outputting serial shifted low going pulse ("1" to "0") occurring on the SI data each instruction time. Resetting EN3 with input. Each pulse must be at least2 (two) instruc- the serial shift register option selected, disables tion cycles wide. SK outputs the value of SKL. SO as the shift register output : data continues The SO output is equal to the value of EN3. With tobe shifted through SIO and can be exchanged ENO reset, SIO is a serial shift register, shifting with A via an XAS instruction but SO remains left each instruction cycle time. The data present reset to "0". ENABLE REGISTER MODES - BITS EN, AND ENo [ens [en [ si [si Tso TK

0 Shift Register Input to Shitt Register oO If SKL = 1, SK = Clock

If SKL =0, SK =0

1 Shift Register Input to Shift Register ‘Serial Out If SKL = 1, SK = Clock

If SKL =0, SK =0 i} Binary Counter | Input to Binary Counter i) If SKL = 1, SK =1 If SKL =0, SK =0

1 Binary Counter | Input to Binary Counter 1 If SKL =1, SK =1

If SKL =0, SK =0 921

INTERNAL LOGIC The SIO register functions as a 4-bit serial-n/serial- The intemal logic of the ETC9410/C9411 is de- Out shift register or as a binary counter depending signed to insure fully static operation of the device. Upon the contents of the EN register. (See EN reg- . ister description above). Its contents can be ex- The 4-bit A register (accumulator) is the source and changed with A, allowing it to input or output destination register for most /O, arithmetic, logic continuous serial data stream. With SIO functioning and data memory access operations. Itcan alsobe ae a serial-in/serial-out shift register and SK as a used to load the Bd portion of the register, toload 4 sync-clock, the ETC9410/C9411 is MICROWIRE® bits of the 8-bit Q latch data and to perform dataex- compatible. changes with the SIO register. A4-bit adder performs the arithmetic and logicfunc- INITIALIZATION tions of the ETC9410/C9411, storing its results in A. The internal reset logic will initialize the device upon It also outputs the carry information to a 1-bit carry power-up if the power supply rise time is less than register, most often employed to indicate arithmetic ms andif the operating frequency at CKl is greater overflow. The C register in conjunction with the XAS- than 32kHz, otherwise the external RC network instruction and the EN register, also serves to con-_ shown in figure 5 must be connected to the RESET trol the SK output. C can be output directly to SK or _ pin. The RESET pin is configured as a Schmitt trig- can enable SK to be a sync clock each instruction ger input. If not used, it should be connected to Vcc. cycle time. (See XAS instruction and EN registerde- _jnitialization will occur whenever a logic °0" is ap- scription below). plied to the RESET input, providing it stays low for The G register contents are outputs to 4 general. _at least three instruction cycle times. purpose bidirectional /O ports. Note :If CKI clock is less than 32kHz, the intemal The Q register is an internal, latched, 8-bit register, reset logic (option 25 = |) MUST be disabled used to hold data loaded from RAM and A, as well and the external RC network must be pres- as 8-bit data from ROM. Its contents are output to ent. the L VO ports when the L drivers are enabledunder Figure § : Power-up Clear Circuit program control. (See LEI instruction). The 8 L drivers, when enabled, output the contents of latched Q data to the L /O ports. Also, the con- e° tents of L may be read directly into A and RAM. 5 Figure 4: RAM Digit Address to Physical RAM Di- Y Yee git Mapping. R — i ETC 9410 Pp P GND 8d VALUE RAM DIGIT 4 o° { 3 I . LTP

1 TR RC > 5 x Power Supply Rise Time and RC > 100 x

‘oO | HAS CKI period °° | aA Upon initialization, the PC register is cleared to 0 SF {__] (ROM address 0) and the A, B, C,D, EN, and G reg- 3 Y // isters are cleared. The SK output is enabled as a SY SYNC output, providing a pulse each instruction ‘ cycle time. Data Memory (RAM) is not cleared upon 3 initialization. The first instruction at address 0 must 2 be a CLRA (clear A register). OY “TaNNSTRUGHON Gee TABLE) HALT MODE The ETC9410/C9411 is a FULLY STATIC circuit ; therefore, the user may stop the system oscillator at any time to halt the chip. The chip may also be halted joret THOMSON G7 SSsaietone

by the HALT instruction orbyforcingCKO highwhen CKO PIN OPTIONS it is used as an HALT VO port. Once in the HALT _in acrystal controlled oscillator system, CKOis used mode, the internal circuitry does not receive any a5 an output to the etystal network. CKO will be clock signal, and is therefore frozen in the exact forced high during the execution of a HALT instruc- state it was in when halted. All information is re- tion, thus inhibiting the crystal network. If a one pin tained until continuing. The HALT modeis the mini-_gecillator system is chosen (RC or external, CKO mum power dissipation state. will be a selected as HALT and is an I/O flip-flop The HALT mode has slight differences depending which is an indicator of the HALT status. An exter- upon the type of oscillator used nal signal can over ride this pin to start and stop the - chip. By forcing a high level to CKO ; the chip wil a) One-pin oscillator - (RC or External) stop as soon as CK is high and the CKO output will The HALT mode may be entered into by either Go high to keep the chip stopped. By forcing a low Program control (HALT instruction) or by forcing jeyel to CKO, the chip will continue and CKO output CKO to a logic "1" state. will go low. The circuit may be awakened by one of two dif- | features associated with the CKO /O pin are ferent methods : available with the 24-pin package only. 1. Continue function - by forcing CKO to a logic “0”, the system clock is re-enabled and the OSCILLATOR OPTIONS Circuit continues to operate from the point There are three options available that define the use where it was stopped. of CKI and CKO. 2. Restart - forcing the RESET pin to alogic"0" —_a) Crystal Controlled Oscillator. CKI and CKO are will restart the chip regardless of HALT or connected to an external crystal. The instruction CKO (see Initialization). cycle time equals the crystal frequency divided b) Two-pin oscillator - (Crystal) by 16 (optionally by 8 or 4). The HALT mode may be enteredintobyprogram —_) External Oscillator. CKlis configured asa LSTTL control (HALT instruction) which forces CKO to compatible input accepting an external clock sig- a logic "1" state. The circuit can be awakened nal. The external frequency is divided by 16 (op- only by the RESET function, tionally by 8 or 4) to give the instruction cycle time. CKO is the HALT /O port. ETco411 ¢) RC Controlled Oscillator. CKI is configured as a If the ETC9410 is bonded as a 20-pin package, it single pin RC controlled Schmitt trigger oscilla- becomes the ETC9411 illustrated in figure 2, tor. The instruction cycle equals the oscillation ETC9410/C9411 Connection Diagrams. Note that frequency divided by 4. CKO is the HALT 0 the ETC9411 does not contain D2, D3, G3, or CKO. port. Use of this option of course precludes use of D2, D3, G3, and CKO options. All other options are avail- able for the ETC9411. tet

ETC9410/9411-ETC9310/9311 _ - Figure 6 : ETC9410C Oscillator. on oxo] nat HALT VO a nsrnucitat Daf or foc a ve i) "om ESET Tp LATCH — a ENABLE c HALT 1/0 port. kt @ ie a lox Ko, vee t T reas CRYSTAL OR RESONATOR R/C CONTROLLED OSCILLATOR Crystal "Component Values [ A | ¢ [eyctetime[ Vee | Value | Rt R2__ C1(pF) _C2(0F) 15k s2pF | 4to ous | 2 45V 32kHz | 220k 20M 30 5.36 30k 82pF 8 to 16us 2 45V 455kHz 5k 10M 80 40 60k 100pF 16 to 32us | 24 to 4.5V 2.096MHz| 2k 1M 30 5.36 Nowe: 1mkens ion aMriz} 1k | 1M | 30 | 536_ S0pF < C < 1509 This Grout and these values are for mdicavon only AS the os- clair charactenstes are nat guaranteed, please consider and ‘examine the crcutt eanstantscarehly on your application VO OPTIONS 1) Open-Drain TRI-STATE® L Output - This has £TC9410/C9411 outputs have the following op- the N-channel device to ground only. tional configurations, illustrated in figure 7 : The SI and RESET inputs are Hi-Z inputs (fig. a) Standard - A CMOS push-pull buffer with an N- 7g). Channel device to ground in conjunction with a When using either the G or L VO ports as inputs, a P-channel device to Voc, compatible withCMOS —_ pull-up device is necessary. This can be an extemal and LSTTL. device or the following alternative is available : Se- b) Low Current - This is the same configuration as ‘lect the low-current output option. Now, by setting a) above except that the sourcing current much _ the output registers to a logic “I" level, the P-chan- feos, nel devices wil act as the pulbup load, Note that when using the L ports in this fashion the Q regis: ©) Open Drain - An N-channel device to ground ters must be set to'a logic "I" level and the L drivers only, allowing external pull-up as requiredby the MUST BE ENABLED by an LE! instruction, user's application. Alloutput drivers use one or more of three common ¢) Standard TRESTATE® | Output -ACMOS out devices numbered 1 to 3. Minimum and maximum ut butter similar to a) which may be disabled by current (lou Vor curves are given in figure 8 foreach Program control. of these devices to allow the designer to effectively e) Low-Current TRI-STATE® L Output-This is the use these I/O configurations. same as d) above except that the sourcing cur- rent is much less. 12721 i221 — ky SesstHomson me 900469? 0563003 331,

Figure 7 : Input and Output Configurations. Yoo Yoo Yee Mt NI i Y a) Standard Push Pull Output ®) Low Current Push Pull Ourput ©) Open Drain Ouput Veo Yoo n DISABLE | DISABLE, T re 63 DISABLE = > {ar 7 bp if d) Standard TRI-STATE® “L" Output ) Low Current TRESTATE® “L" Output f) Open Drain TRISTATE® “L" Output atm 9) HiZ Input 1 139/21

Figure 8 : Input/output Characteristics. Secneeeneeen Coo aoL_ TTT TTT TTT wo LEP TTT TTT TT yy yest | SeGeeeeeeeee eCCCC eet oe Se

2 Ae _* ASS

2 Joa ye POS

3 Cee 8° BSP Re

B)2a09eeenn COCOA oa PEER oo BECOOCPNN Yree CEES AT > EECERN TAT cxcouon esas comcunnenrorrion Se om GeO Seeeeeeeeene oPPEECE Pe «fetter LT TT EAT TT Ty hy Saneneeeee «CEE TPNH oo POSSE . hoo ee Seeenceeneee

2 APEC No 2 ew REO

3 “CARRERA ON 3 FESO » CEE ENN ao COO CECCCCP RC COCCI oR AA » CaCO Loe SemmNay Bett oN TT >» CLERK FERS) You (VOLTS) You (VOLTS) ~ Ree [TT TT oo PREECE be CARS rt ttt 4 « EES » WA : SSSR Nees . I] | TA LL

3 COO 3 YA

3? OC » OTT Yr a POLO » 4 pow TTT TT ATT | | [7 LE wo PLES Ce NE CS COON ° vow vectxr9 wes on OT SS

ETC9410/C9411 INSTRUCTION SET Table 3 provides the mnemonic, operand, machine, Table 2is a symbol table providing internal architec. 0de, data flow, skip conditions and description as- ture, instruction operand and operational symbols __S0Ciated with each instruction in theETC9410/ used in the instruction set table. (C9411 Ingtruction eet Table 2 : ETC9410/C9411 Instruction Set Table Symbols. INTERNAL ARCHITECTURE SYMBOLS INSTRUCTION OPERAND SYMBOLS [Symboi| Definition |= [Symbol] Datinition A 4-bit Accumulator d 4-bit Operand Field, 0-15 Binary (RAM | 8 | 6-bit RAM Address Register digit select) Br Upper 2 Bits of B (register address) r 2-bit Operand Field, 0-3 Binary (RAM 8d | Lower 4 Bits of B (digit address) register select) C | t-bit Carry Register a__| S-bit Operand Field, 0-511 Binary (ROM D | 4-bit Data Output Port address) EN | 4-bit Enable Register y 4-bit Operand Field, 0-15 Binary G__ | 4-bit Register to Latch Data for G /O Port (immediate data) | 8-bit TRISTATE 1/0 Port RAM{(s) | Contents of RAM location addressed by s. | M 4-bit Contents of RAM Memory Pointed to ROM(t) | Contents of RAM location addressed by t. by B Register pc | si Fou Address Register (program OPERATIONAL SYMBOLS Q__ | 8-bit Register to Latch Data for L VO Port [Symbol] Definition == SA | 9-bit Subroutine Save Register A Pus SB__ | 9-bit Subroutine Save Register B * sinus SIO | 4-Lit Shift Register and Counter | Ropiaces SK _ | Logic-controlled Clock Output 7. | te exchanged wah, = Is equal to. A The one’s complement of A @ Exclusive-OR Range of Values | Table 3 : ETC9410/C9411 Instruction Set. ARITHMETIC INSTRUCTIONS [ Machine | Hex| Language Skip oti Mnem cous, ‘“oote Conditions Description (binary) ASC 30 (0011/0000) A+C RAM(B) >A Carry Add with Carry, Skip o7 Carty > C Carry aod] _| 31 |lo911j0001)| A+ RAM) >A [None | Add RAM to A asc] y Jo1ot| Y jJA+y>A Carry | Add immediate Skip on Carry (y # 0) wor | ## |i 9010100\\[ None | None | No Operaten | pe || [ootroora pec | None | newt [yon] | 02 [loooojootoi] A@RAMB) >A "| None _| Exclusive-OR Ram with A ‘SGS-THOMSON 15/21 G7 SSaiotonet

TRANSFER OF CONTROL INSTRUCTIONS Machine Language Skip Code Conditions (binary) JID FF ROM (PCg A, M) Jump Indirect > PCr.o oe 0110j/000a9) aPC Jump 1 ag.9 a PCeo Jump within Page (note 1) (pages 2,3 only) 11 aso a> PCso JSRP 10 aso PC+1+SA3 SB Jump to Subroutine Page 010 + PCeg (note 2) a> PCso JSR 0110)100}fa jj PC+13SA4SB Jump to Subroutine aro a+PC [rer [ae reree reo | 56+ sa Po [None | Retr ram Suboino | /RETSK| 49 0100/1001 SB SA PC Always Skip | Return from Subroutine ‘on Return | then Skip HALT 0011/0011 | Halt Processor 0011/,/1000 SS SSSSSSSSSSSSFeseF & SGS-THOMSON

MEMORY REFERENCE INSTRUCTIONS Machine Language Skip Code Conditions Description (binary) ‘CAMQ) 33 |(001110011]| A>Qr« Copy A, RAM to 3C }1001111100]] RAM (B) > Qa.o Lo 00 r1/0101)}| RAM(B) >A Load RAM into A, Br@r— Br Exclusive-OR Br with r Laip 4011]11114]| ROM(PCa,m) > Q Load Q Indirect SA SB oO 4C |[0100/1100}| 0 RAM (B)o Reset RAM Bit 3 43 [10 100100141) 0 > RAM (B)3 sMB | O 4D |[0100)1101j| 1 > RAM (B)o Set RAM Bit 2 46 |(0100|0110j| 1 > RAM (B)z 3 4B |1010011011)| 1 > RAM (B)s stil y 7 |lorts| y y > RAM (B) None Store Memory Immediate Bd+ 1 Bd and Increment Bd 00}r {0110 j| RAM(B)++A Exchange RAM with A, Br@r— Br Exclusive-OR Br with r 23 ||0010/0011)) RAM(3,15) >A Exchange A with RAM BF |jyortj1114 (3,15) 7 |toojr jo111 || RAM(B) A Bd Exchange RAM with A and Bd- 1 Bd Decrements Decrement Bd, Br@r— Br Past 0 Exclusive-OR Br with r xIS LOO|r 10100 )j| RAM(B)+>A Bd Exchange RAM with A and Bd+1— Bd Increments| Increment Bd, Br@r— Br Past 15 Exclusive-OR Br with r REGISTER REFERENCE INSTRUCTION Machine Language Skip Code Conditions (binary) [cea | | 4e [loroojrstojf essa | None | Copy Ba to'A Lal 00) + | 4) i] ra sB Skip untit | Load B Immediate with rd (d =0.915) not a LBI Ler y oo1ijoott| y>eN Load EN Immediate orol y — ~ ar ‘SGS-THOMSON ioe

£TC9410/9411-ETC9310/9311 TEST INSTRUCTIONS Machine Language Skip | Code Conditions | Description (binary) i [sc [|e |ivore coca Sidi Sep ae [sxe [ [21 [igoroiooory! [A= RAB) Skip if A Equals RAM ‘SKGZ 33 [loo11joo1t Skip if G is zero (all 4 bits) cal 0010j0001 SKGBZ 33 {[0011/0011 1st Byte Skip if G Bit is zero. 0 |} 01 Jjo000|0001j Go =0 1 1 0001/0001 G, =0 2 | 03 lloooojoor1))| Maeve G2 #0 3 13 |ooo1jo014 G3 =0 Oo o1 oooojo00r RAM(B}o = 0 | Skip if RAM Bit is zero. 1 11 |[oo01j0001| RAM(B); =0 2 | 03 |foooojoors RAM(B)2 =0 | 3 [13 ftoootjoorny RAM(B): =0 | INPUT/OUTPUT INSTRUCTIONS Machine Language Skip Code Conditions (binary) ING 33 |[0011]0011]/G>A None | Input G Ports to A 2A |[0010|1010 _ INL 33 |(00114/0011)) tra > RAMBIB) None | Input L Ports to RAM. A ‘080 33 |001110011]/ BA+0 Output Bd to D Outpuis 3E [0011 14 110 33 |[0011/0611)] RAM) >G None | Output RAM to G Ports A |(0011|1010 [xas || 4F [io t00\\1111)] A+ SI0,C > SKL None | Exchange A with SIO Note; 1. The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word ofa page 2 AJSAP transfers program contro to subroutine page 2 (0010s loaded into the upper 4 bits of P). A JSAP may not be used when in pages 2 or 3. JSP may not jump to the last word in page 2 18/21 a CS-THOMSON __ G7 SSSontomonet

The following information is provided to assist the leaving PCe unchanged. The ROM data pointed to user in understanding the operation of several —_by the new address is fetched and loaded into the unique instructions and to provide notes useful to latches. Next, the stack is "popped" (SB programmers in writing ETC9410 C9411. SA-PC), restoring the saved value of PC to con- tinue sequential program execution. Since LAID XAS INSTRUCTION pusches SASB, the previous contents of SB are XAS (Exchange A with SIO) exchanges the 4-bit __lost. Also, when LQID pops the stack, the previously contents of the accumulator with the 4-bit contents pushed contents of SA are left in SB. The net result of the SIO register or binary counter data, depend- is that the contents of SA are placed in SB ing on the value of the EN register. An XAS instruc- (SA-SB). Note that LQID takes two instruction tion will also affect the SK output. (See Functional _cycle times to execute. Description, EN Register, above). If SIO is selected as a shift register, an XAS instruction must be per- NSTRUCTION SET NOTES formed once every 4 instruction cycles to effect aa) The first word of a ETC9410/C9411 program continuous data stream. (ROM address 0) must be a CLRA (Clear A) ins- truction. JID INSTRUCTION b) Although skipped instructions are not executed, JID (Jump Indirect) is an indirect addressing instruc- one instruction cycle time is devoted to skipping tion, transferring program control to a new ROM lo- each byte of the skipped instruction. Thus all pro- cation pointed to indirectly by A and M. It loads the gram paths except JID and LQID take the same lower 8 bits of the ROM address register PC with number of cycle times whether instructions are the contents of ROM Addressed by the 9-bit word, skipped or executed. JID and LOID instructions PCs, A, M, PCa is not affected by this instruction. take 2 cycles if executed and 1 cycle if skipped Note : That JID requires 2 instruction cycles to ex-_¢) The ROMis organized into 8 pages of 64 words ecute. each. The Program Counter is a 9-bit binary counter, and will count through page boundaries. LOID INSTRUCTION ta JP, JSRP, JID or LQID instruction is located LOID (Load Q indirect) loads the 8-bit Q register with in the last word of a page, the instruction oper- the contents of ROM pointed to by the 9-bit word ates as if it were in the next page. For example PCs, A, M. LQID can be used for table lookup or a JP located in the last word of a page will jump code conversion such as BCD to seven-segment. to a location in the next page. Also, a LQID or The LQID instruction "pushes" the stack JID located in the last word of page 3 or 7 will ac- (PC +1-»SA~SB) and replaces the least significant cess data in the next group of 4 pages. 8 bits of PC as follows : A>PC74 RAM (B)-»PC3.0 G57 S6s:THoMsON 192 To BY cts,

OPTION LIST Option 9 : Vee Pin. The ETC9410/ETC9411 mask-programmable op- Option 10 : Ls Driver. (Same as Option 5.) tons 2 assigned numbers which correspond with Option 11 : Le Driver. (Same as Option 5.) Ls Option 12 : Li Driver. (Same as Option 5.) The following is a list of £TC9410 options. When ee ' specifying a ETC9411 chip, Options 20,21, and 22 «Option 13 : Lo Driver. (Same as Option 5.) must be set to 0. The options are programmed at Option 14 : SI Input. the same time as the ROM pattern to provide the No option available. user with the hardware flexibility to interface to vari- = 1: Hi-Z input ous to components using litle or no external ci Gao 45 - $0 Output “on. , . ; =0:: Standard push-pull output. Option 1 ; = 0 : Ground Pin. No options available. = 1: Low-curtent push-pull output. Option 2: CKO 1/0 Port. Determined by Option 3. = 2: Open-drain output Option 3 ‘ CKI Input , Option 16 : SK Driver. (Same as Option 15.) = 0: Crystal controlled oscillator input (- 4). ion 17 : Go VO Pott. (S: ion 1 = 1: Single-pin RC-controlled oscillator (- 4). Option ‘* mad ame as Option 16.) = 2: External oscillator input (- 4). Option 18 : G1 YO Port. (Same as Option 15:) = 3: Crystal oscillator input (- 8). Option 19 : G2 /O Port. (Same as Option 15.) = 4: Extemal oscillator input (- 8). Option 20 : Gs Output. (Same as Option 15.) = 5 : Crystal oscillator input (- 16). Option 21 : D3 Output. (Same as Option 15.) = 6 : External oscillator input (- 16). ; Option 22 : Dz Output. (Same as Option 15.) Option i : RESET Input = 1: Hi-Z input. No option Option 23 : D: Output. (Same as Option 15.) Option 8 Lz Orver Option 24 : Do Output. (Same as option 15.) = 0 : Standard TRI-STATE push-pull output Option 25 : Internal Initialization logic. = 1: Low-current TRI-STATE push-pull output = 0: Normal operation. = 2: Open-drain TRISTATE output = 1: No internal initialization Logic Option 6 : Ls Driver. (Same as Option 5.) Option 26 : No option available. Option 7 : Ls Driver (Same as Option 5.) rio oeeie ay device) : : ‘ =0: pin device). Option 8 : Ls Driver : (Same as Option 5.) ry :ETC9411 20 pin device) = 2: ETC9410 and ETC9411.

24—-PINS — PLASTIC PACKAGE ep eg eg tg tee eee eyece je th.tmae, 0.51 min. 4 | pl 5.08 mox}}] } i) ~ i 3 | 0.38 ume, / WL o2 of. 39 0.508 03 TIS? 526 | (2) Datum L (1) Nomina dimension p | (2) True geometrical position cola ooo ooo 326moe 14

24 Pins

20-PINS — PLASTIC PACKAGE. mon en 25412) mex mal Ax 5,08 max. / J : HH : + ane HY EE 7 Vast // 02. \\ a // 0.38 7m. 8 762 \\ a9 0,508 (2) ot le if a_/ 1 Datum / (1) Nominal cimension Oo _} een | (2) True geometrical positior lo P T 0 5 a 20 Pins