ETC5067-X

ETC5064 STMICROELECTRONICS | Alldatasheet

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Technical content

SERIAL INTERFACE CODEC/FILTER WITH RECEIVE ORDERING NUMBERS: ETC5064FN ETC5064FN-X ETC5067FN ETC5067FN-X .COMPLETE CODEC AND FILTERING SYS- TEM INCLUDING : - Transmit high-pass and low-pass filtering. - Receive low-pass filter with sin x/x correction. - Active RC noise filter. - µ-law or A-law compatible CODER and DE- CODER. - Internal precision voltage reference. - Serial I/O interface. - Internal auto-zero circuitry. - Receive push-pull power amplifiers. .µ-LAW ETC5064 .A-LAW ETC5067 .MEETS OR EXCEEDS ALL D3/D4 AND CCITT SPECIFICATIONS. .± 5 V OPERATION. .LOW OPERATING POWER-TYPICALLY 70 mW .POWER-DOWN STANDBY MODE-TYPICALLY 3m W .AUTOMATIC POWER DOWN .TTL OR CMOS COMPATIBLE DIGITAL INTER- FACES .MAXIMIZES LINE INTERFACE CARD CIR- CUIT DENSITY .0°CT O7 0°C OPERATION: ETC5064/67 .–40°CT O8 5°C OPERATION: ETC5064-X/67-X

DESCRIPTION

The ETC5064 (µ-law), ETC5067 (A-law) are mono- lithic PCM CODEC/FILTERS utilizing the A/D and D/Aconversion architectureshown in the Block Dia- grams and a serial PCM interface. The devices are fabricated using double-poly CMOS process. Similar to the ETC505X family, these devices fea- ture an additional Receive Power Amplifier to pro- vide push-pull balanced output drive capability. The receive gain can be adjusted by means of two ex- ternal resistors for an output level of up to± 6.6 V across a balanced600Ω load. Also included is an Analog Loopback switch and TS X output. DIP20 (Plastic) N PLCC20 FN SO20 D ORDERING NUMBERS: ETC5064N ETC5064N-X ETC5067N ETC5067N-X ORDERING NUMBERS: ETC5064D ETC5064D-X ETC5067D ETC5067D-X

BLOCK DIAGRAM (ETC5064 - ETC5064-X - ETC5067 - ETC5067-X) PIN CONNECTIONS (Top views) DIP20 & SO20 PLCC20 ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

Type (*) N Description VPO + O 1 The Non-inverting Output of the Receive Power Amplifier GNDA GND 2 Analog Ground. All signals are referenced to this pin. VPO - O 3 The Inverting Output of the Receive Power Amplifier VPI I 4 Inverting Input to the Receive Power Amplifier. Also powers down both amplifiers when connected to VBB . VF R O O 5 Analog Output of the Receive Filter. VCC S 6 Positive Power Supply Pin. V CC =+ 5 V±5% FS R I 7 Receive Frame Sync Pulse which enable BCLK R to shift PCM data into D R .F SR is an 8KHz pulse train. See figures 1 and 2 for timing details. D R I 8 Receive Data Input. PCM data is shifted into D R following the FSR leading edge BCLK R /CLKSEL I 9 The bit Clock which shifts data into D R after the FSR leading edge. May vary from 64KHz to 2.048MHz. Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in synchronous mode and BCLK X is used for both transmit and receive directions (see table 1). This input has an internal pull-up. MCKL be asynchronous with MCLKX , but should be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. be asynchronous with MCLKR . BCLK X I 12 The bit clock which shifts out the PCM data on DX . May vary from 64KHz to 2.048MHz, but must be synchronous with MCLKX . D X O 13 The TRI-STATE  PCM data output which is enabled by FSX . FS X I 14 Transmit frame sync pulse input which enables BCLK X to shift out the PCM data on DX.F SX is an 8KHz pulse train. See figures 1 and 2 for timing details. TS X O 15 Open drain output which pulses low during the encoder time slot. Must to be grounded if not used. ANLB I 16 Analog Loopback Control Input. Must be set to logic ’0’ for normal operation. When pulled to logic ’1’, the transmit filter input is disconnected from the output of the transmit preamplifier and connected to the VPO+ output of the receive power amplifier. GS X O 17 Analog output of the transmit input amplifier. Used to set gain externally. VF XI- I 18 Inverting input of the transmit input amplifier. VF XI+ I 19 Non-inverting input of the transmit input amplifier. VBB S 20 Negative Power Supply Pin. V BB = -5V±5% (*) I: Input, O: Output, S: Power Supply. TRI-STATE  is a trademark of National Semiconductor Corp. ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

high impedance state until the second FSX pulse. sates for the 193 rd clock pulse each frame. the negativeedge of BCLKX (or on BCKLR if running). FSX and FSR must be synchronous with MCLKX/R.

1.544 MHz for the ETC5064, and need not be syn-

and must be synchronous with MCLKX and BCLKX. chronous or asynchronousoperating mode. figure 3. Based on the transmit frame sync FS Table 1:Selection of Master Clock Frequencies.

pulses are being used. For 64 kHz operation, the frame sync pulses must be kept low for a minimum of 160 ns (see Fig 1). The D X TRI-STATE output buffer is enabledwith the rising edge of FSX or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising edges clock out the remaining seven bits. The DX outputis disabled by the falling BCLK X edge following the eighth rising edge, or by FSX goinglow, whichevercomes later. Arising edge on the receive frame sync pulse, FSR , will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKx in synchronous mode).Bothdevicesmay utilize the long frame sync pulse in synchronous or asynchronousmode. TRANSMIT SECTION The transmitsectioninput is an operationalamplifier with provision for gainadjustmentusingtwo external resistors,seefigure4. The low noiseandwide band- width allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter directly drives the encodersample- and-hold circuit. The A/D is of companding type ac- cording to A-law (ETC5067 and ETC5067-X) orµ- law (ETC5064 and ETC5064-X) coding conven- tions. A precision voltage reference is trimmed in manufacturing to provide an input over load (t MAX ) of nominally 2.5V peak (see table of Transmission Characteristics). The FS X frame sync pulse controls the sampling of thefiler output,and thenthe succes- sive-approximationencodingcyclebegins.The8-bit code is then loaded into a buffer and shifted out throughDX atthe next FSX pulse.the total encoding delaywill be approximately 165µs (due to the trans- mit filter) plus 125µs (due to encodingdelay), which totals 290µs. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. RECEIVE SECTION The receive section consist of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256kHz. The decoderis A-law (ETC5067 and ETC5067-X) orµ–law (ETC5064 and ETC5064-X) and the 5 th order low pass filter corrects for the sin x/x attenuation due to the 8kHz sample and hold. The filter is then followed by a 2 nd order RC active post-filter and power amplifier capableof driving a 600Ω load to a level of 7.2dBm. The receive section is unity-gain. Upon the oc- curence of FS R , the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCKLX) periods.At the endofthe decodertime slot, the decoding cycle begins, and 10µs later the de- coder DAC outputis updated.The total decoder de- lay is about10µs (decoder up-date) plus 110µs (fil- ter delay) plus 62.5µs (1/2 frame), which gives ap- proximately 180µs. RECEIVE POWER AMPLIFIERS Two inverting mode power amplifiers are provided for directly driving a matched line interface trans- former. The gain of the first power amplifier can be adjustedto boostthe± 2.5Vpeakoutputsignal from the receive filter up± 3.3V peak into an unbalanced 300Ω load,or±4.0V into an unbalanced15kΩ load. The second power amplifier is internally connected in unity-gain inverting mode to give 6dB of signal gainfor balancedloads. Maximum powertransferto a 600Ω subscriber line termination is obtained by differientially driving a balanced transformer with a √2 : 1 turns ratio, as shown in figure 4. A total peak power of 15.6dBmcan be delivered to the load plus termination. Both power amplifier can be powered downindependentlyfromthe PDN inputbyconnect- ing the VPI input to VBB saving approximately 12 mW of power. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC VCC to GNDA 7 V VBB VBB to GNDA -7 V VIN,VOUT Voltage at any Analog Input or Output V CC +0.3 to VBB -0.3 V Voltage at any Digital Input or Output V CC +0.3 to GNDA -0.3 V Toper Operating Temperature Range:ETC5064/67 ETC5064-X/67-X -25 to +125 -40 to +125 Tstg Storage Temperature Range -65 to +150 °C Lead Temperature (soldering, 10 seconds) 300 °C ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

ELECTRICAL OPERATING CHARACTERISTICS VCC =5.0V±5%,V BB =-5 V±5%, GNDA =0V, TA =0°Ct o 7 0°C (ETC5064-X/67-X:TA =–4 0°Ct o8 5°), unless otherwise noted; typical characteristics specified at VCC = 5.0V, VBB =-5.0V, TA =2 5°C; all signals are refer- enced to GNDA. DIGITAL INTERFACE (All devices) Symbol Parameter Min. Typ. Max. Unit VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.2 V VOL Output Low Voltage IL = 3.2 mA D X IL = 3.2 mA, Open Drain TS X 0.4 0.4 V V VOH Output High Voltage IH = 3.2 mA D X 2.4 V IIL Input Low Current (GNDA≤ VIN ≤ VIL )all digital inputs Except BCLKR –1 0 1 0 µA IIH Input High Current (VIH ≤ VIN ≤ VCC ) Except ANLB – 10 10 µA IOZ Output Current in High Impedance State (TRI-STATE) (GNDA ≤ VO ≤ VCC )D X –1 0 1 0 µA ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices) Symbol Parameter Min. Typ. Max. Unit IIXA Input Leakage Current VFxI + or VFxI– – 200 200 nA R IXA Input Resistance VF XI+ or VFX I–

10 M Ω

R O XA Output Resistance (closed loop, unity gain) 1 3 Ω R LXA Load Resistance GS X 10 k Ω C LXA Load Capacitance GS X 50 pF VO XA Output Dynamic Range (R L ≥ 10 kΩ )G S X – 2.8 +2.8 V AVXA Voltage Gain (VF X I+ to GSX) 5000 V/V FU XA Unity Gain Bandwidth 1 2 MHz VOS XA Offset Voltage – 20 20 mV VCM XA Common-mode Voltage – 2.5 2.5 V CMRRXA Common-mode Rejection Ratio 60 dB PSRRXA Power Supply Rejection Ratio 60 dB ANALOG INTERFACE WITH RECEIVE FILTER (all devices) Symbol Parameter Min. Typ. Max. Unit R O RF Output Resistance VF R O1 3 Ω R LRF Load Resistance (VF R O= ± 2.5 V) 10 k Ω C LRF Load Capacitance 25 pF VOS R O Output DC Offset Voltage – 200 200 mV ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

ANALOG INTERFACE WITH POWER AMPLIFIERS (all devices) Symbol Parameter Min. Typ. Max. Unit IPI Input Leakage Current (– 1.0 V≤ VPI ≤ 1.0 V) – 100 100 nA RIPI Input Resistance (– 1.0≤ VPI ≤ 1.0 V) 10 M Ω VIOS Input Offset Voltage – 25 25 mV ROP Output Resistance (inverting unity–gain at VPO+ or VPO –)1 Ω FC Unity–gain Bandwidth, Open Loop (VPO–) 400 kHz C LP Load Capacitance (VPO + or VPO – to GNDA) R L ≥ 1500 Ω R L = 600 Ω R L = 300Ω 100 500 1000 pF GAp + Gain VPO – to VPO + to GNDA, Level at VPO– = 1. 77 Vrms (+ 3 dBmO) – 1 V/V PSRRp Power Supply Rejection of VCC or VBB (VPO – connected to VPI) 0 kHz – 4 kHz 0 kHz – 50 kHz dB POWER DISSIPATION (all devices) Symbol Parameter Min. Typ. Max. Unit ICC 0 Power-down Current at ETC6064/67 ETC5064-X/67-X 0.5 0.5 1.5 mA mA IBB 0 Power-down Current at ETC6064/67 ETC5064-X/67-X 0.05 0.05 0.3 0.4 mA mA ICC 1 Active Current at ETC6064/67 ETC5064-X/67-X 7.0 7.0 10.0 12.0 mA mA IBB 1 Active Current at ETC6064/67 ETC5064-X/67-X 7.0 7.0 10.0 12.0 mA mA ELECTRICAL OPERATING CHARACTERISTICS (Continued) ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

Symbol Parameter Min. Typ. Max. Unit 1/tPM Frequency of master clocks MCLK X and MCLK R Depends on the device used and the BCLK R /CLKSEL Pin 1.536 2.048 1.544 MHz tWMH Width of Master Clock High MCLK X and MCLK R 160 ns tWML Width of Master Clock Low MCLK X and MCLK R 160 ns tRM Rise Time of Master Clock MCLK X and MCLK R 50 ns tFM Fall Time of Master Clock MCLK X and MCLK R 50 ns tPB Period of Bit Clock 485 488 15.725 ns tWBH Width of Bit Clock High (VIH = 2.2 V) 160 ns tWBL Width of Bit Clock Low (VIL = 0.6 V) 160 ns tRB Rise Time of Bit Clock (tPB = 488 ns) 50 ns tFB Fall Time of Bit Clock (tPB = 488 ns) 50 ns tSBFM Set-up time from BCLKX high to MCLKX falling edge. (first bit clock after the leading edge of FSX ) 100 ns tHBF Holding Time from Bit Clock Low to the Frame Sync (long frame only) 0n s tSFB Set-up Time from Frame Sync to Bit Clock (long frame only) 80 ns tHBFI Hold Time from 3rd Period of Bit Clock FS X or FSR Low to Frame Sync (long frame only) 100 ns tDZF Delay Time to valid data from FSX or BCLKX , whichever comes later and delay time from FSX to data output disabled (CL = 0 pF to 150 pF) 20 165 ns tDBD Delay Time from BCLKX high to data valid (load = 150 pF plus 2 LSTTL loads) 0 150 ns tDZC Delay Time from BCLKX low to data output disabled 50 165 ns tSDB Set-up Time from DR valid to BCLKR/X low 50 ns tHBD Hold Time from BCLKR/X low to DR invalid 50 ns tHOLD Holding Time from Bit Clock High to Frame Sync (short frame only) 0 ns tSF Set-up Time from FSX/R to BCLKX/R Low (short frame sync pulse) - Note 1 80 ns tHF Hold Time from BCLKX/R Low to FSX/R Low (short frame sync pulse) - Note 1 100 ns tXDP Delay Time to TSX low (load = 150 pF plus 2 LSTTI loads) 140 ns tWFL Minimum Width of the Frame Sync Pulse (low level) (64 bit/s operating mode) 160 ns Note : 1.For short frame sync timing. FSX and FSR must go high while their respective bit clocks are high. Figure 1 :64 k bits/s TIMING DIAGRAM. (see next page for complete timing) ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

Figure 2 :Short Frame Sync Timing. ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

Figure 3 :Long Frame Sync Timing. ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

TRANSMISSION CHARACTERISTICS (all devices) TA =0 °Ct o7 0°C (ETC5064-X/67-X: TA = –40°Ct o8 5°), VCC =5 V ± 5%, VBB =–5 V ± 5%, GNDA=0V, f =1.02kHz,VIN = 0dBm0transmit inputamplifierconnectedforunity–gainnon–inverting.(unless otherwise specified). AMPLITUDE RESPONSE Symbol Parameter Min. Typ. Max. Unit Absolute Levels - Nominal 0 dBm0 is 4 dBm (600Ω ). 0 dBm0

1.2276 Vrms

3.14 dBm0 ETC5067 3.17 dBm0 ETC5064 2.492 2.501 VPK G XA Transmit Gain, Absolute (TA =2 5°C, VCC = 5V, VBB = -5V) Input at GSX = 0dBm0 at 1020Hz -0.15 0.15 dB GXR Transmit Gain, Relative to GXA f = 16Hz f = 50Hz f = 60Hz f = 180Hz f = 200Hz f = 300Hz -3000Hz f = 3200Hz (ETC5064-X/67-X) f = 3300Hz f = 3400Hz f = 4000Hz f = 4600Hz and up, measure response from oHz to 4000Hz -2.8 -1.8 -0.15 -0.35 -0.35 -0.7 -40 -30 -26 -0.2 -0.1 0.15 0.20 0.05 -14 -32 dB G TA =0 °C to +70°C TA = –40°C to +85°C (ETC5064-X/67-X) -0.1 -0.15 0.1 0.15 dB (VCC =5 V ±5%, VBB = -5V±5%) -0.05 0.05 dB G XRL Transmit Gain Variation with Level Sinusolidal Test Method Reference Level = -10dBm0 VF X I+ = -40dBm0 to +3dBm0 VF X I+ = -50dBm0 to -40dBm0 VF X I+ = -55dBm0 to -50dBm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 dB G RA Receive Gain, Absolute (TA =2 5°C, VCC = 5V, VBB = -5V) Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz -0.15 0.15 dB G RR Receive Gain, Relative to GRA f = 0Hz to 3000Hz f = 3200Hz (ETC5064-X/67-X) f = 3300Hz f = 3400Hz f = 4000Hz -0.15 -0.35 -0.35 -0.7 0.15 0.20 0.05 -14 dB G TA =0 °C to +70°C TA = –40°C to +85°C (ETC5064-X/67-X) -0.1 -0.15 0.1 0.15 dB (VCC =5 V ±5%, VBB = -5V±5%) -0.05 0.05 dB G RRL Receive Gain Variation with Level Sinusoidal Test Method; Reference Input PCM code corresponds to an ideally encoded -10dBm0 signal PCM level = -40dBm0 to +3dBm0 PCM level = -50dBm0 to -40dBm0 PCM level = -55dBm0 to -50dBm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 dB V RO Receive Filter Output at VFR OR L = 10KΩ -2.5 2.5 V ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

TRANSMISSION CHARACTERISTICS (continued). ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol Parameter Min. Typ. Max. Unit D XA Transmit Delay, Absolute (f = 1600 Hz) 290 315 µs D XR Transmit Delay, Relative to DXA f = 500 Hz-600 Hz f = 600 Hz-800 Hz f = 800 Hz-1000 Hz f = 1000 Hz-1600 Hz f = 1600 Hz-2600Hz f = 2600 Hz-2800 Hz f = 2800 Hz-3000 Hz 195 120 130 220 145 105 155 µs D RA Receive Delay, Absolute (f = 1600 Hz) 180 200 µs D RR Receive Delay, Relative to DRA f = 500 Hz-1000 Hz f = 1000 Hz-1600 Hz f = 1600 Hz-2600 Hz f = 2600 Hz-2800 Hz f = 2800 Hz-3000 Hz –4 0 –3 0 –2 5 –2 0 100 145 125 175 µs NOISE Symbol Parameter Min. Typ. Max. Unit N XP Transmit Noise, P Message (A-LAW, VFX I+ = 0 V) Weighted 1) ETC5064 ETC5064-X –7 4 –7 4 –6 9 –6 7 dBm0p dBm0p N RP Receive Noise, P Message Weighted (A-LAW, PCM Code Equals Positive Zero) – 82 – 79 dBm0p N XC Transmit Noise, C Message Weighted (µ-LAW, VFxI+ =0V ) ETC5064 ETC5064-X dBrnC0 dBrnC0 N RC Receive Noise, C Message Weighted (µ-LAW, PCM Code Equals Alternating Positive and Negative Zero) 8 11 dBrnC0 N RS Noise, Single Frequency f = 0 kHz to 100 kHz, Loop around Measurement, VFXI+ =0 V – 53 dBm0 PPSR X Positive Power Supply Rejection, Transmit (note 2) VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz 40 dBp NPSR X Negative Power Supply Rejection, Transmit (note 2) VBB = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz 40 dBp PPSR R Positive Power Supply Rejection, Receive (PCM code equals positive zero, VCC = 5.0 VDC + 100 mVrms) f = 0 Hz-4000Hz A LAW µ LAW f = 4 kHz-25 kHz f = 25 kHz-50 kHz dBp dBc dB dB NPSR R Negative Power Supply Rejection, Receive (PCM code equals positive zero, VBB = – 5.0 VDC + 100 mVrms) f = 0 Hz-4000Hz A LAW µ LAW f = 4 kHz-25 kHz f = 25 kHz-50 kHz dBp dBc dB dB SOS Spurious out-of-band Signals at the Channel Output 0 dBm0, 300 Hz-3400 Hz input PCM applied at D R

4600 Hz-7600 Hz

7600 Hz-8400 Hz

8400 Hz-100,000 Hz

–32 –40 –32 dB dB dB ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

TRANSMISSION CHARACTERISTICS (continued). DISTORTION Symbol Parameter Min. Typ. Max. Unit STD X or STD R Signal to Total Distortion (sinusoidal test method) Transmit or Receive Half-channel Level = 3.0 dBm0 = 0 dBm0 to – 30 dBm0 = – 40 dBm0 XMT RCV = – 55 dBm0 XMT RCV dBp (ALAW) dBc (µLAW) SFD X Single Frequency Distortion, Transmit (TA =2 5°C) – 46 dB SFD R Single Frequency Distortion, Receive (TA =2 5°C) – 46 dB IMD Intermodulation Distortion Loop Around Measurement, VFXI+ = – 4 dBm0 to – 21 dBm0, two Frequencies in the Range 300 Hz-3400 Hz –4 1 d B CROSSTALK Symbol Parameter Min. Typ. Max. Unit CT X-R Transmit to Receive Crosstalk, 0dBm0 Transmit f = 300 Hz-3400 Hz, DR = Steady PCM Code ETC5064/67 ETC5064-X/67-X –9 0 –7 5 –6 5 dB dB CT R-X Receive to Transmit Crosstalk, 0dBm0 Receive Level (note 2) f = 300 Hz-3400 Hz, VFXI=0V ETC5064/67 ETC5064-X/67-X –9 0 –7 0 –6 5 dB dB POWER AMPLIFIERS Symbol Parameter Min. Typ. Max. Unit VOL Maximum 0 dBm0 Level for Better than± 0.1 dB Linearity Over the Range 10 dBm0 to + 3 dBm0 (balanced load, R L connected between VPO+ and VPO –) R L = 600Ω R L = 1200Ω R L =3 0kΩ 3.5 4.0 Vrms S/DP Signal/Distortion RL = 600 Ω , 0 dBm0 50 dB Notes : 1. Measured by extrapolation from the distortion test results. 2. PPSRX, NPSRX, CTR–X measured with a –50dBm0 activating signal applied at VFX I+ ENCODING FORMAT AT D X OUTPUT A-Law (Including even bit inversion) µLaw VIN (at GSX ) = + Full-scale 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 VIN (at GSX )=0V 1 1 0 1 0 1 0 1 01010101 11111111 01111111 VIN (at GSX ) = – Full-scale 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

APPLICATION INFORMATION

While the pins at the ETC506X family are well pro- tected against electrical misure, it is recommended that the standard CMOS practice be followed, en- suring that ground is connected tothe device before any other connections are made. In applications where the printed circuit board may be pluggedinto a ”hot” socket with power and clocks already pre- sent, an extra long ground pin in the connector should be used. All ground connectionsto each device should meet at a common point ascloseas possible to the GNDA pin. This minimizes the interaction of ground return currentsflowing througha common bus impedance. 0.1µF supply decoupling capacitors should be con- nected from this common ground point to VCC and VBB as close to the device as possible. For best performance, the ground point of each CODEC/FILTER on a card should be connected to a common card groundin star formation,rather than via a ground bus. This common groundpoint should be decoupled to VCC and VBB with 10µF capaci- tors. For best performance, TSx should be grounded if not used. Figure 4 :Typical Asynchronous Application. ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

SO20 PACKAGE MECHANICAL DATA DIM. mm inch A 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 ° (typ.) D 12.6 13.0 0.496 0.510 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.4 7.6 0.291 0.300 L 0.5 1.27 0.020 0.050 M 0.75 0.030 S8 ° (max.) ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

PLCC20 PACKAGE MECHANICAL DATA DIM. mm inch A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 e3 5.08 0.200 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.045 ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

DIP20 PACKAGE MECHANICAL DATA DIM. mm inch a1 0.254 0.010 B 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L 3.3 0.130 Z 1.34 0.053 ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifica- tions mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information pre- viously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics .  1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. ETC5064 - ETC5064-X - ETC5067 - ETC5067-X