ETC5054

ETC5054 STMICROELECTRONICS | Alldatasheet

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SERIAL INTERFACE CODEC/FILTER COMPLETE CODEC AND FILTERING SYS- TEM (DEVICE) INCLUDING: – Transmit high-pass and low-pass filtering. – Receive low-pass filter with sin x/x correction. – Active RC noise filters – µ-law or A-law compatible COder and DECoder. – Internal precision voltage reference. – Serial I/O interface. – Internal auto-zero circuitry. A-LAW 16 PINS (ETC5057FN, 20 PINS) µ-LAW WITHOUT SIGNALING, 16 PINS (ETC5054FN, 20 PINS) MEETS OR EXCEEDS ALL D3/D4 AND CCITT SPECIFICATIONS ±5V OPERATION LOW OPERATING POWER - TYPICALLY 60 mW POWER-DOWN STANDBY MODE - TYPI- CALLY 3 mW AUTOMATIC POWER-DOWN TTL OR CMOS COMPATIBLE DIGITAL IN- TERFACES MAXIMIZES LINE INTERFACE CARD CIR- CUIT DENSITY 0t o7 0°C OPERATION

DESCRIPTION

The ETC5057/ETC5054 family consists of A-law and µ–law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in the block diagram below, and a serial PCM inter- face. The devices are fabricated using double- poly CMOS process. The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-ca- pacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded A-law orµ–law PCM format. The de- code portion of each device consists of an ex- panding decoder, which reconstructs the analog signal from the companded A-law orµ–law code, a low-pass filter which corrects for the sin x/x re- sponse of the decoder output and rejects signals above 3400 Hz and is followed by a single-ended power amplifier capable of driving low impedance loads. The devices require 1.536 MHz, 1.544 MHz, or 2.048 MHz transmit and receive master clocks, which may be asynchronous, transmit and receive bit clocks which may vary from 64 kHz to

2.048 MHz, and transmit and receive frame sync

pulses. The timing of the frame sync pulses and PCM data is compatible with both industry stand- ard formats. This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. March 2000 DIP16 (Plastic) ORDERING NUMBERS: ETC5057N ETC5054N SO16 (Wide) ORDERING NUMBERS: ETC5057D ETC5054D PLCC20 ORDERING NUMBERS: ETC5057FN ETC5054FN

PIN CONNECTIONS (Top view) DIP and SO PLCC BLOCK DIAGRAM ETC5054 - ETC5057

N ° DIP and SO N ° PLCC (**) Function Description VBB S 1 1 Negative Power Supply VBB =–5V ± 5% . GNDA GND 2 2 Analog Ground All signals are referenced to this pin. VF R O O 3 3 Receive Filter Output Analog Output of the Receive Filter VCC S 4 5 Positive Power Supply VCC =+5V ± 5% . FS R I 5 6 Receive Frame Sync Pulse Enables BCLKR to shift PCM data into DR .F SR is an 8kHz pulse train. See figures 1, 2 and 3 for timing details. D R I 6 7 Receive Data Input PCM data is shifted into DR following the FSR leading edge. BCLK R /CLKSEL I 7 8 Shift-in Clock Shifts data into D R after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLK X is used for both transmit and receive directions (see table 1). This input has an internal pull- up. MCLK R /PDN I 8 9 Receive Master Clock Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLK X, but should be synchronous with MCLKX for best performance. When MCLK R is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. MCLK X I 9 12 Transmit Master Clock Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKR . BCLK XI 10 14 Shift-out Clock Shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. D X O 11 15 Transmit Data Output The TRI-STATE  PCM data output which is enabled by FSX. FS X I 12 16 Transmit Frame Sync Pulse Enables BCLKX to shift out the PCM data on DX.F SX is an 8 kHz pulse train. See figures 1, 2 and 3 for timing details. TS X O 13 17 Transmit Time Slot Open drain output which pulses low during the encoder time slot. Recommended to be grounded if not used. GS X O 14 18 Gain Set Analog output of the transmit input amplifier. Used to set gain externally. VF XI– I 15 19 Inverting Amplifier Input Inverting Input of the Transmit Input Amplifier. VF XI+ I 16 20 Non-inverting Amplifier Input Non-inverting Input of the Transmit Input Amplifier. (*) I: Input, O: Output, S: Power Supply (**) Pins 4,10,11 and 13 are not connected TRI-STATE  is a trademark of National Semiconductor Corp. ETC5054 - ETC5057

When power is first applied, power-on reset cir- cuitry initializes the device and places it into the power-down mode. All non-essential circuits are deactivated and the D X and VFR O outputs are put in high impedance states. To power-up the device, a logical low level or clock must be ap- plied to the MCLK R /PDN pin and FSX and/or FSR pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLK R /PDN pin high ; the alternative is to hold both FSX and FSR inputs continuously low. The device will power-down approximately 2 ms after the last FSX or FSR pulse. Power-up will occur on the first FSX or FSR pulse. The TRI-STATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse. SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLK X and the MCLK R /PDN pin can be used as a power-down control. A low level on MCLKR /PDN powers up the device and a high level powers down the de- vice. In either case, MCLK X will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be applied to BCLKX and the BCLKR /CKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. With a fixed level on the BCLK R /CLKSEL pin, BCLKX will be selected as the bit clock for both the transmit and receive directions. Table 1 indicates the frequen- cies of operation which can be selected, depend- ing on the state of BCLK R /CLKSEL. In this syn- chronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must be synchro- nous with MCLKX. Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the posi- tive edge of BCLKX. After 8 bit clock periods, the TRI-STATE D X output is returned to a high im- pedance state. With and FSR pulse, PCM data is latched via the DR input on the negative edge of BCLK X (or BCLKR if running). FSX and FSR must be synchronouswith MCLKX/R. ASYNCHRONOUS OPERATION For asynchronous operation, separate transmit and receive clocks may be applied, MCLKX and MCLK R must be 2.048 MHz for the ETC5057, or 1.536 MHz, 1.544 MHz for the ETC5054, and need not be synchronous. For best transmission performance, however, MCLK R should be syn- chronous with MCLKX, which is easily achieved by applying only static logic levels to the MCLK R/PDN pin. This will automatically connect MCLK X to all internal MCLKR functions (see pin description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FS X starts each encoding cycle and must be synchronous with MCLK X and BCLK X.F SR starts each decoding cycle and must be synchronous with BCLKR . BCLKR must be a clock, the logic levels shown in table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to 2.048 MHz. SHORT FRAME SYNC OPERATION The device can utilize either a short frame sync pulse or a long frame sync pulse. Upon power in- itialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR , must be one bit clock period long, with timing relationships specified in figure 2. With FSX high during a falling edge of BCLKX the next ris- ing edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remain- ing seven bits, and the next falling edge disables the D X output. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. Both devices may utilize the short frame sync pulse in synchronous or asyn- chronous operating mode. LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships speci- fied in figure 3. Based on the transmit frame sync, FS X, the device will sense whether short or long frame sync pulses are being used. For 64 kHz op- eration, the frame sync pulse must be kept low for a minimum of 160 ns (see fig. 1). The D X TRI- STATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX, which- ever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising Table 1: Selectionof Master Clock Frequencies. BCLK R /CLKSEL Master Clock Frequency Selected ETC5057 ETC5054 Clocked 1 (or open circuit)

2.048 MHz

1.536 MHz or

1.544 MHz

edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge fol- lowing the eighth rising edge, or by FSX going low, which-ever comes later. A rising edge on the receive frame sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). Both devices may utilize the long frame sync pulse in synchronous or asynchronous mode. TRANSMIT SECTION The transmit section input is an operational ampli- fier with provision for gain adjustment using two external resistors, see figure 6. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unitygain filter consisting of RD ac- tive pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the en- coder sample-and-hold circuit. The A/D is of com- panding type according to A-law (ETC5057) orµ– law (ETC5054) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (t MAX ) of nominally 2.5V peak (see table of transmission characteristics). The FSX frame sync pulse controls the sampling of the filter output, and then the successive-ap- proximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through DX at the next FSX pulse. The total en- coding delay will be approximately 165µs (due to the transmit filter) plus 125µs (due to encoding delay), which totals 290µs. Any offset vol-tage due to the filters or comparator is cancelled by sign bit integration. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (ETC5057) orµ–law (ETC5054) and the 5th order low pass filter corrects for the sin x/x at- tenuation due to the 8 kHz sample and hold. The filter is then followed by a 2nd order RC ac- tive post-filter and power amplifier capable of driv- ing a 600Ω load to a level of 7.2 dBm. The re- ceive section is unity-gain. Upon the occurence of FS R , the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKX)p e - riods. At the end of the decoder time slot, the de- coding cycle begins, and 10µs later the decoder DAC output is updated. The total decoder delay is ∼ 10µs (decoder update) plus 110µs (filter delay) plus 62.5µs (1/2 frame), which gives ap- proximately 180µs. A mute circuitry is a active during 10ms when power up. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC VCC to GNDA 7 V V BB VBB to GNDA – 7 V VIN,V OUT Voltage at any Analog Input or Output V CC + 0.3 to VBB – 0.3 V Voltage at Any Digital Input or Output V CC + 0.3 to GNDA – 0.3 V Toper Operating Temperature Range – 25 to + 125 °C Tstg Storage Temperature Range – 65 to + 150 °C Lead Temperature (soldering, 10 seconds) 300 °C ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0 V± 5% , VBB = – 5.0 V± 5%GNDA = 0 V, TA =0 °Ct o7 0°C; Typical Characteristics Specified at VCC = 5.0 V, VBB = – 5.0 V, TA =2 5°C ; all signals are referenced to GNDA. Symbol Parameter Min. Typ. Max. Unit VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.2 V VOL Output Low Voltage IL = 3.2mA D X IL = 3.2mA, Open Drain TS X 0.4 0.4 V V V OH Output High Voltage IH = 3.2mA D X 2.4 V IIL Input Low Current (GNDA≤ VIN ≤ VIL, all digital inputs) –10 10 µA IIH Input High Current (VIH ≤ VIN ≤ VCC ) except BCLKR /BCLKSEL –10 10 µA IOZ Output Current in HIGH Impedance State (TRI-STATE) (GNDA ≤ VO ≤ VCC )D X –10 10 µA ETC5054 - ETC5057

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices) Symbol Parameter Min. Typ. Max. Unit IIXA Input Leakage Current VF XI+ or VFX I- (–2.5V≤ V ≤ +2.5V) – 200 200 nA R IXA Input Resistance VF XI+ or VFX I- (–2.5V≤ V ≤ +2.5V)

10 M Ω

R O XA Output Resistance (closed loop, unity gain) 1 3 Ω R LXA Load Resistance GS X 10 k Ω C LXA Load Capacitance GS X 50 pF VO XA Output Dynamic Range (R L ≥ 10KΩ )G S X ±2.8 V AV X A Voltage Gain (VFXI+ to GSX) 5000 V/V FU XA Unity Gain Bandwidth 1 2 MHz VOS XA Offset Voltage – 20 20 mV VCM XA Common-mode Voltage – 2.5 2.5 V CMRRXA Common-mode Rejection Ratio 60 dB PSRRXA Power Supply Rejection Ratio 60 dB ANALOG INTERFACE WITH RECEIVE FILTER (all devices) Symbol Parameter Min. Typ. Max. Unit R O RF Output Resistance VF R O1 3 Ω R LRF Load Resistance (VF R O= ±2.5V) 600 Ω C LRF Load Capacitance 500 pF VOS R O Output DC Offset Voltage – 200 200 mV POWER DISSIPATION (all devices) Symbol Parameter Min. Typ. Max. Unit ICC 0 Power-down Current 0.5 1.5 mA IBB 0 Power-down Current 0.05 0.3 mA ICC 1 Active Current 6.0 9.0 mA IBB 1 Active Current 6.0 9.0 mA ETC5054 - ETC5057

Symbol Parameter Min. Typ. Max. Unit 1/tPM Frequency of master clocks Depends on the device used and the BCLKR /CLKSEL Pin MCLK X and MCLK R 1.536 1.544 2.048 MHz MHz MHz t WMH Width of Master Clock High MCLK X and MCLK R 160 ns tWML Width of Master Clock Low MCLK X and MCLK R 160 ns tRM Rise Time of Master Clock MCLK X and MCLK R 50 ns tFM Fall Time of Master Clock MCLK X and MCLK R 50 ns tPB Period of Bit Clock 485 488 15.725 ns tWBH Width of Bit Clock High (VIH = 2.2V) 160 ns tWBL Width of Bit Clock Low (VIL= 0.6V) 160 ns tRB Rise Time of Bit Clock (tPB = 488ns) 50 ns tFB Fall Time of Bit Clock (tPB = 488ns) 50 ns tSBFM Set-up time from BCLKX high to MCLKX falling edge. (first bit clock after the leading edge of FSX ) 100 ns tHBF Holding Time from Bit Clock Low to the Frame Sync (long frame only) 0n s tSFB Set-up Time from Frame Sync to Bit Clock (long frame only) 80 ns tHBFI Hold Time from 3rd Period of Bit Clock FS X or FSR Low to Frame Sync (long frame only) 100 ns tDZF Delay time to valid data from FSX or BCLKX , whichever comes later and delay time from FSX to data output disabled. (CL = 0pF to 150pF) 20 165 ns tDBD Delay time from BCLKX high to data valid. (load = 150pF plus 2 LSTTL loads) 0 180 ns tDZC Delay time from BCLKX low to data output disabled. 50 165 ns tSDB Set-up time from DR valid to BCLKR/X low. 50 ns tHBD Hold time from BCLKR/X low to DR invalid. 50 ns tHOLD Holding Time from Bit Clock High to Frame Sync (short frame only) 0n s tSF Set-up Time from FSX/R to BCLKX/R Low (short frame sync pulse) - Note 1 80 ns tHF Hold Time from BCLKX/R Low to FSX/R Low (short frame sync pulse) - Note 1 100 ns tXDP Delay Time to TSX low (load = 150pF plus 2 LSTTL loads) 140 ns tWFL Minimum Width of the Frame Sync Pulse (low level) 64kbit/s operating mode) 160 ns Figure 1:64kbits/s TIMING DIAGRAM (see next page for complete timing). Note 1:For short frame sync timing FSX and FSR must go high while their respective bit clocks are high. FSx FSR ETC5054 - ETC5057

Figure 2:Short Frame Sync Timing ETC5054 - ETC5057

Figure 3:Long Frame Sync Timing ETC5054 - ETC5057

TRANSMISSION CHARACTERISTICS TA = 0 to 70°C, VCC = +5V ±5%, VBB = –5V ±5%, GNDA = 0V, f = 1.0KHz, VIN = 0dBm0 transmit input amplifier connected for unity-gain non-inverting (unless otherwise specified). AMPLITUDE RESPONSE Symbol Parameter Min. Typ. Max. Unit Absolute levels - nominal 0 dBm0 level is 4 dBm (600Ω ) 0 dBm0

1.2276 Vrms

3.14 dBm0 (A LAW) 3.17 dBm0 (U LAW) 2.492 2.501 VPK VPK G XA Transmit Gain, Absolute (TA = 25°C, VCC = 5 V, VBB =–5V ) Input at GSX = 0 dBm0 at 1020 Hz – 0.15 0.15 dB G XR Transmit Gain, Relative to GXA f = 16 Hz f = 50 Hz f = 60 Hz f = 180 Hz f = 200 Hz f = 300 Hz - 3000 Hz f = 3300 Hz f = 3400 Hz f = 4000 Hz f = 4600 Hz and up, Measure Response from 0 Hz to 4000 Hz – 2.8 – 1.8 – 0.15 – 0.35 – 0.7 –4 0 –3 0 –2 6 – 0.2 – 0.1 0.15 0.05 –1 4 –3 2 dB G TA = 0 to +70°C – 0.1 0.1 dB G XRL Transmit Gain Variations with Level Sinusoidal Test Method Reference Level = – 10 dBm0 VFXI+ = – 40 dBm0 to + 3 dBm0 VF XI+ = – 50 dBm0 to – 40 dBm0 VF XI+ = – 55 dBm0 to – 50 dBm0 – 0.2 – 0.4 – 1.2 0.2 0.4 1.2 dB dB dB G RA Receive Gain, Absolute (TA =2 5°C, VCC = 5V, VBB = –5V) Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz – 0.15 0.15 dB G RR Receive Gain, Relative to GRA f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz – 0.35 – 0.35 – 0.7 0.20 0.05 –1 4 dB dB dB dB G TA = 0 to +70°C – 0.1 0.1 dB G RRL Receive Gain Variations with Level Sinusoidal Test Method; Reference input PCM code corresponds to an ideally encoded – 10 dBm0 signal PCM level = – 40 dBm0 to + 3 dBm0 PCM level = – 50 dBm0 to – 40 dBm0 PCM level = – 55 dBm0 to – 50 dBm0 – 0.2 – 0.4 – 1.2 0.2 0.4 1.2 dB dB dB V RO Receive Output Drive Level (RL = 600Ω ) – 2.5 2.5 V ETC5054 - ETC5057

ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol Parameter Min. Typ. Max. Unit D XA Transmit Delay, Absolute (f = 1600Hz) 290 315 µs D XR Transmit Delay, Relative to DXA f = 500Hz - 600Hz f = 600Hz - 800Hz f = 800Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz 195 120 130 220 145 105 155 µs D RA Receive Delay, Absolute (f = 1600Hz) 180 200 µs D RR Receive Delay, Relative to DRA f = 500Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz –4 0 –3 0 –2 5 –2 0 100 145 125 175 µs TRANSMISSION (continued) NOISE Symbol Parameter Min. Typ. Max. Unit N XP Transmit Noise, P Message Weighted (A LAW, VFXI+ = 0 V) 1) – 74 – 69 dBm0p N RP Receive Noise, P Message Weighted (A LAW, PCM code equals positive zero) – 82 – 79 dBm0p N XC Transmit Noise, C Message Weightedµ LAW (VFXI + = 0 V) 12 15 dBmC0 N RC Receive Noise, C Message Weighted (µ LAW, PCM Code Equals Alternating Positive and Negative Zero) 8 11 dBrnC0 N RS Noise, Single Frequency f = 0 kHz to 100 kHz, Loop around Measurement, VF XI+ = 0 Vrms – 53 dBm0 PPSR X Positive Power Supply Rejection, Transmit (note 2) VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz 40 dBp NPSR X Negative Power Supply Rejection, Transmit (note 2) VBB = – 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz 40 dBp PPSR R Positive Power Supply Rejection, Receive (PCM code equals positive zero, VCC = 5.0 VDC + 100mVrms) f = 0Hz to 4000Hz f = 4KHz to 25KHz f = 25KHz to 50KHz dBp dB dB NPSR R Negative Power Supply Rejection, Receive (PCM code equals positive zero, VBB = 5.0 VDC + 100mVrms) f = 0Hz to 4000Hz f = 4KHz to 25KHz f = 25KHz to 50KHz dBp dB dB ETC5054 - ETC5057

NOISE (continued) Symbol Parameter Min. Typ. Max. Unit SOS Spurius out-of-band Signals at the Channel Output Loop around measurement, 0dBm0, 300Hz - 3400Hz input applied to DR, measure individual image signals at DX 4600Hz - 7600Hz 7600Hz - 8400Hz 8400Hz - 100,000Hz –3 2 –4 0 –3 2 dB dB dB TRANSMISSION CHARACTERISTICS (continued) DISTORTION Symbol Parameter Min. Typ. Max. Unit STD X or STD R Signal to Total Distortion (sinusoidal test method) Transmit or Receive Half-channel Level = 3.0dBm0 Level = 0dBm0 to –30dBm0 Level = –40dBm0 XMT RC V Level = –55dBm0 XMT RCV dBp SFD X Single Frequency Distortion, Transmit (TA =2 5°C) –46 dB SFD R Single Frequency Distortion, Receive (TA =2 5°C) –46 dB IMD Intermodulation Distortion Loop Around Measurement, VFXI+ = –4dBm0 to –21dBm0, two Frequencies in the Range 300Hz - 3400Hz –41 dB CROSSTALK Symbol Parameter Min. Typ. Max. Unit CT X-R Transmit to Receive Crosstalk, 0 dBm0 Transmit Level f = 300Hz to 3400Hz, DR = Steady PCM Mode – 90 – 75 dB CT R-X Receive to Transmit Crosstalk, 0 dBm0 Receive Level f = 300Hz to 3400Hz, (note 2) – 90 – 70 dB Notes: 1) Measured by extrapolation from distortion test results. 2) PPSR X, NPSRX,C TR-X is measured with a –50dBm0 activating signal applied at VFXI+. ENCODING FORMAT AT D X OUTPU T A-Law (including even bit inversion) µLaw VIN (at GSX) = +Full-scale 1 0 10101010000000 VIN (at GSX)=0 V 1 VIN (at GSX) = – Full-scale 0 0 10101000000000 ETC5054 - ETC5057

APPLICATION INFORMATION

While the pins at the ETC505X family are well protected against electrical misuse, it is recom- mended that the standard CMOS practice be fol- lowed, ensuring that ground is connected to the device before any-other connections are made. In applications where the printed circuit board may be plugged into a ”hot” socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1µF supply decoupling capaci- tors should be connected from this common ground point to V CC and VBB as close to the de- vice as possible. For best performance, the ground point of each CODEC/FILTER on a card should be connected to a common card ground in star formation, rather than via a ground bus. This common ground point should be decoupled to V CC and VBB with 10µF capacitors. RECEIVE GAIN ADJUSTMENT For applications where a ETC505X family CODEC/filter receive output must drive a 600Ω load, but a peak swing lower then± 2.5V is re- quired, the receive gain can be easily adjusted by inserting a matched T-pad orπ –pad at the out- put. Table II lists the required resistor values for 600Ω terminations. As these are generally non- standard values, the equations can be used to compute the attenuation of the closest pratical set of resistors. It may be necessary to use unequal values for the R1 or R4 arms of the attenuatorsto achieve a precise attenuation. Generally it is tol- erable to allow a small deviation of the input im- pedance from nominal while still maintaining a good return loss. For example a 30dB return loss against 600Ω is obtained if the output impedance of the attenuator is in the range 282Ω to 319Ω (assuming a perfect transformer).Figure 4:T-PAD Attenuator Figure 5:Π -PAD Attenuator Table 2 :AttenuatorTables For Z1 = Z2 = 300Ω (all values inΩ ). dB R1 R2 R3 R4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.7 3.5 5.2 6.9 8.5 10.4 12.1 13.8 15.5 17.3 34.4 51.3 100 115 129 143 156 168 180 190 200 210 218 233 246 26k 13k 8.7k 6.5k 5.2k 4.4k 3.7k 3.3k 2.9k 2.6k 1.3k 850 650 494 402 380 284 244 211 184 161 142 125 110 3.5 6.9 10.4 13.8 17.3 21.3 24.2 27.7 31.1 34.6 107 144 183 224 269 317 370 427 490 550 635 720 816 924 1.17k 1.5k 52k 26k 17.4k 13k 10.5k 8.7k 7.5k 6.5k 5.8k 5.2k 2.6k 1.8k 1.3k 1.1k 900 785 698 630 527 535 500 473 450 430 413 386 366 R1 = Z1 N 2 + 1 N2 − 1 N N 2 − 1 N N2 − 1 POWEROUT and: S =√Z1 Where ZSC = impedance with short circuit termi- nation and ZOC = impedance with open circuit ter- mination. N 2 − 1 N R3 = Z1 N 2 − 1 N2 − 2NS + 1 ETC5054 - ETC5057

Figure 6:Typical Synchronous Application. ETC5054 - ETC5057

DIM. mm inch A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 10.1 10.5 0.398 0.413 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 K0 ° (min.)8° (max.) hx 45 A eB D E H L CK 1 8 SO16 Wide OUTLINE AND MECHANICAL DATA ETC5054 - ETC5057

DIM. mm inch a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 OUTLINE AND MECHANICAL DATA ETC5054 - ETC5057

B A G (Seating Plane Coplanarity)PLCC20ME E e F D M M PLCC20 DIM. mm inch A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.045 OUTLINE AND MECHANICAL DATA ETC5054 - ETC5057

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