ES29LV400E EXCELSEMI | Alldatasheet

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1 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. ES29LV400E 4Mbit(512Kx 8/256K x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory GENERAL FEATURES

  • Single power supply operation - 2.7V -3.6V for read, program and erase operations
  • S e c t o r S t r u c t u r e - 16Kbyte x 1, 8Kbyte x 2, 32Kbyte x 1 boot sectors - 64Kbyte x 7sectors
  • Top or Bottom boot block - ES29LV400ET for Top boot block device - ES29LV400EB for Bottom boot block device
  • Package Options - 48-pin TSOP - 48-ball FBGA ( 6 x 8 mm ) - Pb-free packages - All Pb-free products are RoHS-Compliant
  • Low Vcc write inhibit
  • Manufactured on 0.18um process technology
  • Compatible with JEDEC standards - Pinout and software compatible with single-power supply flash standard DEVICE PERFORMANCE
  • Read access time - 70ns / 90ns
  • Program and erase time - Program time : 6us/byte, 8us/word ( typical ) - Sector erase time : 0.7sec/sector ( typical )
  • Power consumption (typical values) - 200nA in standby or automatic sleep mode - 7mA active read current at 5 MHz - 15mA active write current during program or erase
  • Minimum 100,000 program/erase cycles per sector
  • 20 Year data retention at 125 oC SOFTWARE FEATURES
  • Erase Suspend / Erase Resume
  • Data# poll and toggle for Program/erase status
  • Unlock Bypass program
  • Autoselect mode
  • Auto-sleep mode after t ACC + 30ns HARDWARE FEATURES
  • Hardware reset input pin ( RESET#) - Provides a hardware reset to device - Any internal device operation is terminated and the device returns to read mode by the reset
  • Ready/Busy# output pin ( RY/BY#) - Provides a program or erase operational status about whether it is finished for read or still being progressed
  • Sector protection / unpr otection ( RESET# , A9 ) - Hardware method of locking a sector to prevent any program or erase operation within that sector - Two methods are provided : - In-system method by RESET# pin - A9 high-voltage method for PROM programmers
  • Temporary Sector Un protection ( RESET# ) - Allows temporary unprotection of previously protected sectors to change data in-system

2 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. The ES29LV400 is a 4 megabit, 3.0 volt-only flash memory device, organized as 512K x 8 bits (Byte mode) or 256K x 16 bits (Word mode) which is con- figurable by BYTE#. Four boot sectors and seven main sectors are provided : 16Kbytes x 1, 8Kbytes x 2, 32Kbytes x 1 and 64Kbytes x 7. The device is manufactured with ESI’s proprietary, high perfor- mance and highly reliable 0.18um CMOS flash technology. The device can be programmed or erased in-system with standard 3.0 Volt Vcc supply ( 2.7V-3.6V) and can also be programmed in stan- dard EPROM programmers. The device offers min- imum endurance of 100,000 program/erase cycles and more than 10 years of data retention. The ES29LV400 offers access time as fast as 70ns, allowing operation of high-speed micropro- cessors without wait states. Three separate control pins are provided to eliminate bus contention : chip enable (CE#), write enable (WE#) and output enable (OE#). All program and erase operation are automatically and internally performed and controlled by embed- ded program/erase algorithms built in the device. The device automatically generates and times the necessary high-voltage pulses to be applied to the cells, performs the verification, and counts the num- ber of sequences. Some status bits (DQ7, DQ6 and DQ5) read by data# po lling or toggling between consecutive read cycles provide to the users the internal status of program/erase operation: whether it is successfully done or still being progressed. The ES29LV400 is complete ly compatible with the JEDEC standard command set of single power sup- ply Flash. Commands are written to the internal command register using standard write timings of microprocessor and data can be read out from the cell array in the device with the same way as used in other EPROM or flash devices. GENERAL PRODUCT DESCRIPTION

3 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Command Register Analog Bias Generator Address LatchBYTE# CE# OE# A<0:17> RESET# Vcc Vss Chip Enable Output Enable Logic Vcc Detector Timer/ Counter Y-Decoder X-Decoder Y-Decoder Cell Array Data Latch/ Sense Amps Input/Output Buffers Sector Switches RY/BY# Write State Machine WE# FUNCTION BLOCK DIAGRAM PRODUCT SELECTOR GUIDE Family Part Number ES29LV400 Voltage Range 2.7 ~ 3.6V Speed Option 70 90 Max Access Time (ns) 70 90 CE# Access (ns) 70 90 OE# Access (ns) 35 40 DQ0-DQ15(A-1)

4 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. PIN DESCRIPTION Pin Description A0-A17 18 Addresses DQ0-DQ14 15 Data Inputs/Outputs DQ15/A-1 DQ15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) CE# Chip Enable OE# Output Enable WE# Write Enable RESET# Hardware Reset Pin, Active Low BYTE# Selects 8-bit or 16-bit mode RY/BY# Ready/Busy Output Vcc 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) Vss Device Ground NC Pin Not Connected Internally LOGIC SYMBOL DQ0 ~ DQ15 (A-1) RY/BY#BYTE# RESET# OE# CE# A0 ~ A17 WE# 16 or 8

5 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. CONNECTION DIAGRAM 48-Ball FBGA (6 x 8 mm) (Top View, Balls Facing Down) A15 A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# NC A17 A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# 48-Pin Standard TSOP ES29LV400 A13 A12 A14 A15 A16 DQ15/ Vss WE# OE#CE#A0A1A2A4 NC A11 DQ7 DQ14 DQ13 DQ6 NC NC NC DQ5 NC DQ2 DQ0 DQ8 DQ9 DQ1 DQ10 DQ11 DQ3 DQ12 Vcc DQ4 A10 A B C D E F G H BYTE# A-1 RESET# RY/ A7 A17 A6 Vss BY#

6 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Several device operational modes are provided in the ES29LV400 device. Commands are used to ini- tiate the device operations . They are latched and stored into internal registers with the address and data information needed to execute the device operation. The available device operational modes are listed in Table 1 with the required inputs, controls, and the resulting outputs. Each operational mode is described in further detail in the following subsec- tions. Read The internal state of the device is set for the read mode and the device is ready for reading array data upon device power-up, or after a hardware reset. To read the stored data from the cell array of the device, CE# and OE# pins should be driven to V IL while WE# pin remains at V IH. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. Word or byte mode of output data is determined by the BYTE# pin. No additional command is needed in this mode to obtain array data. Standard micro- processor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device stays at the read mode until another operation is activated by writing commands into the internal command register. Refer to the AC read cycle timing diagrams for further details ( Fig. 16 ). Word/Byte Mode Configuration ( BYTE# ) The device data output can be configured by BYTE# into one of two modes : word and byte modes . If the BYTE# pin is set at logic ‘1’, the device is configured in word mode, DQ0 - DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is configured in byte mode, and only data I/O pins DQ0 - DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8 - DQ14 are tri- stated, and the DQ15 pin is used as an input for the LSB (A-1) address. Standby Mode When the device is not se lected or activated in a system, it needs to stay at the standby mode, in which current consumption is greatly reduced with outputs in the high impedance state. DEVICE BUS OPERATIONS

7 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. The device enters the CMOS standby mode when CE# and RESET# pins are both held at Vcc +0.3V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within Vcc +0.3V, the device will be still in the standby mode, but the standby current will be greater than the CMOS standby current (0.2uA typi- cally). When the device is in the standby mode, only standard access time (t CE) is required for read access, before it is ready for read data. And even if the device is deselected by CE# pin during erase or programming operation, the device draws active cur- rent until the operation is completely done. While the device stays in the standby mode, the output is placed in the high impedance state, independent of the OE# input. The device can enter the deep power-down mode where current consumption is greatly reduced down to less than 0.2uA typically by the following three ways: - CMOS standby ( CE#, RESET# = Vcc + 0.3V ) - During the device reset ( RESET# = Vss + 0.3V ) - In Autosleep Mode ( after tACC + 30ns ) Refer to the CMOS DC characteristics Table 7 for further current specification. Autosleep Mode The device automatically enters a deep power-down mode called the autosleep mode when addresses remain stable for t ACC+30ns. In this mode, current consumption is greatly reduced ( less than 0.2uA typical ), regardless of CE#, WE# and OE# control signals. Writing Commands To write a command or command sequences to ini- tiate some operations such as program or erase, the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin deter- mines whether the device accepts program data in bytes or words. Refer to “BYTE# timings for Write Operations” in the Fig. 19 for more information. Unlock Bypass Mode To reduce more the programming time, an unlock- bypass mode is provided. Once the device enters this mode, only two write cycles are required to ini- tiate the programming operation instead of four cycles in the normal program command sequences which are composed of two unlock cycles, program set-up cycle and the last cycle with the program data and addresses. In this mode, two unlock cycles are saved ( or bypassed ). Sector Addresses The entire memory space of cell array is divided into a many of small sectors: 16Kbytes x 1, 8Kbytes x 2, 32Kbytes x 1 and 64Kbytes x 7 main sectors. In erase operation, a single se ctor, multiple sectors, or the entire device (chip eras e) can be selected for erase. The address space that each sector occupies is shown in detail in the Table 3-4. Autoselect Mode Flash memories are intended for use in applications where the local CPU alters memory contents. In such applications, manufacturer and device identifi- cation (ID) codes must be accessible while the device resides in the target system ( the so called “in-system program”). On the other hand, signature codes have been typically accessed by raising A9 pin to a high voltage in PROM programmers. How- ever, multiplexing high voltage onto address lines is not the generally desired system design practice. Therefore, in the ES29LV400 device an autoselect command is provided to allow the system to access the signature codes without any high voltage. The conventional A9 high-voltage method used in the PROM programers for sig nature codes are still sup- ported in this device. If the system writes the autoselect command sequence, the device enters the Autoselect mode. The system can then read some useful codes such as manufacturer and device ID from the internal reg- isters on DQ7 - DQ0. Standard read cycle timings apply in this mode. In the Autoselect mode, the fol- lowing three informations can be accessed through either autoselect command method or A9 high-volt- age autoselect method. Refer to the Table 2. Manufacturer ID - Device ID - Sector protection verify Hardware Device Reset ( RESET# ) The RESET# pin provides a hardware method of resetting the device to read array data. When the RESET# pin is driven low for at least a period of t RP ,

8 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. the device immediately te rminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once after the device is ready to accept another command sequence, to ensure data integrity. CMOS Standby during Device Reset Current is reduced for the duration of the RESET# pulse. When RESET# is held at Vss + 0.3V, the device draws the greatly reduced CMOS standby current ( I CC4 ) . I f R E S E T # i s h e l d a t VIL but not within Vss+0.3V, the standby current will be greater. RY/BY# and Terminating Operations If RESET# is asserted dur ing a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is completed, which requires a time of t READY (during Embedded Algo- rithms). The system can thus monitor RY/BY# to determine whether the reset operation is completed. If RESET# is asserted wh en a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo rithms). The system can read data after the RESET# pin returns to VIH, which requires a time of tRH. RESET# tied to the System Reset The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot- up firmware from the Flash memory.Refer to the AC Characteristics tables fo r RESET# parameters and to Fig. 17 for the timing diagram. SECTOR PROTECTION The ES29LV400 features hardware sector protec- tion. In the device, sector protection is performed on the sector previously defined in the Table 3-4. Once after a sector is protecte d, any program or erase operation is not allowed in the protected sector. The previously protected sectors must be unprotected by one of the unprotect methods provided here before changing data in those sectors. Sector protection can be implemented via two methods. In-system protection - A9 High-voltage protection To check whether the se ctor protection was suc- cessfully executed or not, another operation called “protect verification” needs to be performed after the protection operation on a sector. All protection and protect verifications provided in the device are summarized in detail at the Table 1. In-System Protection “In-system protection”, the primary method, requires V ID (11.5V~12.5V) on the RESET# with A6=0, A1=1, and A0=0. This method can be imple- mented either in-system or via programming equip- ment. This method uses standard microprocessor bus cycle timing. Refer to Fig. 26 for timing diagram and Fig. 2 for the protection algorithm. A9 High-Voltage Protection “High-voltage protection”, the alternate method intended only for programming equipment, must force V ID (11.5~12.5V) on address pin A9 and con- trol pin OE# with A6=0, A1=1 and A0=0. Refer to Fig. 28 for timing diagram and Fig. 4 for the protec- tion algorithm. SECTOR UNPROTECTION The previously protected sectors must be unpro- tected before modifying any data in the sectors. The sector unprotection al gorithm unprotects all sectors in parallel. All unprotected sectors must first be protected prior to the first sector unprotection write cycle to avoid any over-erase due to the intrin- sic erase characteristics of the protection cell. After the unprotection operation, all previously protected sectors will need to be i ndividually re-protected. Standard microprocessor bus cycle timings are used in the unprotection and unprotect verification operations. Three unprotect methods are provided in the ES29LV400 device. All unprotection and unprotect verification cycles are summarized in detail at the Table 1. In-system unprotection - A9 High-voltage unprotection - Temporary sector unprotection

and Fig. 3 for the unprotection algorithm. ously protected sectors to change data in-system. shows the timing diagrams for this feature. Vcc power-up and power-down. tentional writes when Vcc is greater than VLKO. or WE# do not initiate a write cycle. automatically reset to the read mode on power-up.

  1. All protected sectors are unprotected .
  2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect

Table 1. ES29LV400 Device Bus Operations

  1. Addresses are A17:A0 in word mode (BYTE#=VIH) , A17:A-1 in byte mode (BYTE#=VIL).
  2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Pro-

tection and Unprotection” section. IN or DOUT as required by command sequence, data polling, or sector protection algorithm. Table 2. Autoselect Codes (A9 High-Voltage Method)

Table 3. Top Boot Sector Addresses (ES29LV400ET) The addresses range is A17:A-1 in byte mode (BYTE#=VIL) or A17:A0 in word mode (BYTE#=VIH). Table 4. Bottom Boot Sector Addresses (ES29LV400EB) The addresses range is A17:A-1 in byte mode (BYTE#=VIL) or A17:A0 in word mode (BYTE#=VIH).

14 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 defines the valid register command sequences. Note that writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is required to return the device to normal operation. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever hap- pens first. Refer to the AC Characteristics section for timing diagrams. READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend com- mand, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next sectio n, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more informa- tion.The Read-Only Operati ons table provides the read parameters, and Fig. 16 shows the timing dia- gram RESET COMMAND Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to which the system was writ ing to the read mode. Once erasure begins, how ever, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to which the system was writing to the read mode. If the program command sequence is written to a sec- tor that is in the Erase Suspend mode, writing the reset command returns the device to the erase-sus- pend-read mode. Once programming begins, how- ever, the device ignore s reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend- read mode. If DQ5 goes high during a program or erase opera- tion, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase-Suspend). COMMAND DEFINITIONS

Table 5. ES29LV400 Command Definitions

90 X00 4A

55 SA 30

RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A17-A12 uniquely select any sector.

  1. The data is 00h for an unprotected sector and 01h for a
  2. The Unlock Bypass command is required prior to the Unlock-
  3. The Unlock Bypass Reset command is required to return
  4. The system may read and program in non-erasing sectors,
  5. The Erase Resume command is valid only during the Erase
  6. See Table 1 for description of bus operations.
  7. All values are in hexadecimal.
  8. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

  1. Data bits DQ15-DQ8 are don’t care in command sequences,
  2. Unless otherwise noted, address bits A17-A11 are don’t cares.
  3. No unlock or command cycles required when device is in
  4. The Reset command is required to return to the read mode

goes high (while the device is providing status information).

  1. The fourth cycle of the autoselect command sequence

Autoselect Command Sequence section for more information.

locked or customer lockable version. Table 5 shows the address and data requirements. write cycle that contains the autoselect command. used for reading the manufacturer code. the device was previously in Erase Suspend). byte, depending on the state of the BYTE# pin . pulses and verifies the programmed cell margin. Figure 6. Program Operation

17 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Program Status Bits : DQ7, DQ6 or RY/BY# When the Embedded Program algorithm is com- plete, the device then retu rns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section Table 6 for information on these status bits. Any Commands Ignored during Program- ming Operation Any commands written to the device during the Embedded Program algorithm are ignored. Note that a hardware reset can immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming from “0” back to “1” Programming is allowed in any sequence and across sector boundaries. But a bit cannot be pro- grammed from “0” back to a ”1”. Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1” Unlock Bypass In the ES29LV400 device, an unlock bypass pro- gram mode is provided for faster programming oper- ation. In this mode, two cycles of program command sequences can be saved. To enter this mode, an unlock bypass enter command should be first written to the system. The unlock bypass enter command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle contain- ing the unlock bypass command, 20h. The device then enters the unlock-bypass program mode. A two-cycle unlock bypass program command sequence is all that is r equired to program in this mode. The first cycle in this sequence contains the unlock bypass program set-up command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program com- mand sequence, resulting in faster total program- ming time. Table 5 shows the requirements for the command sequence. During the unlock-bypass mode, only the unlock- bypass program and unlock-bypass reset com- mands are valid. To exit the unlock-bypass mode, the system must issue the two-cycle unlock-bypass reset command sequence. The first cycle must con- tain the data 90h. The second cycle need to only contain the data 00h. The device then returns to the read mode. - Unlock Bypass Enter Command - Unlock Bypass Reset Command - Unlock Bypass Program Command CHIP ERASE COMMAND To erase the entire memory, a chip erase command is used. This command is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up com- mand. Two additional unlock write cycles are then followed by the chip eras e command, which in turn invokes the Embedded Erase algorithm. The chip erase command erases the entire memory includ- ing all other sectors except the protected sectors, but the internal erase operation is performed on a single sector base. Embedded Erase Algorithm The device does not require the system to prepro- gram prior to erase. The Embedded Erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to pro- vide any controls or timings during these opera- tions. Table 5 shows the address and data requirements for the chip erase command sequence. Note that the autoselect is unavailable while an erase operation is in progress Erase Status Bits : DQ7, DQ6, DQ2, or RY/ BY# When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Opera- tion Status section Table 6 for information on these status bits. Commands Ignored during Erase Operation Any command written during the chip erase opera- tion are ignored. However, note that a hardware

illustrates the algorithm for the erase operation. Fig. 21 section for timing diagrams. unavailable while an erase operation is in progress. trols or timings these operations. ber of sectors may be from one sector to all sectors. mand may not be accepted, and erasure may begin. DQ7,DQ6,DQ2, or RY/BY# in the erasing sector. for information on these status bits.

  1. See Table 5 for erase command sequence
  2. See the section on DQ3 for information on the sector erase timer

Figure 7. Erase Operation

19 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. sequence should be reinitiated once the device has returned to reading array data, to ensure data integ- rity. Fig. 7 illustrates the algo rithm for the erase opera- tion. Refer to the Erase and Program Operations tables in the AC Characteristics section for parame- ters, and Fig. 21 section for timing diagrams. ERASE SUSPEND/ERASE RESUME An erase operation is a long-time operation so that two useful commands are provided in the ES29LV400 device Erase Suspend and Erase Resume Commands. Through the two commands, erase operation can be suspended for a while and the suspended operation can be resumed later when it is required. While the erase is suspended, read or program operations can be performed by the system. Erase Suspend Command, (B0h) The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only dur- ing the sector erase operation, including the 50us time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embed- ded Program algorithm. When the Erase Suspend command is written during the sector erase opera- tion, the device requires a maximum of 20us to sus- pend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time- out period and suspends the erase operation. Read and Program during Erase-Suspend- Read Mode After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for er asure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sec- tors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is ac tively erasing or is erase- suspended. Refer to the Write Operation Status sec- tion for information on these status bits (Table 6). After an erase-suspended program operation is complete, the device returns to the erase-suspend- read mode. The system can determine the status for the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to the Write Operation Status section for more information. Autoselect during Erase-Suspend- Read Mode In the erase-suspend-read mode, the system can also issue the autoselected command sequence. Refer to the Auto select Mode and Autoselect Com- mand Sequence section for details (Table 5). Erase Resume Command To resume the sector er ase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

Figure 8. Command Diagram

21 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. In the ES29LV400 device, several bits are provided to determine the status of a program or erase oper- ation: DQ2, DQ3, DQ5, DQ6, DQ7 and RY/BY#. Table 6 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/ BY#, to determine whether an Embedded Program or Erase operation is in progress or has been com- pleted. DQ7 (DATA# POLLING) The Data# Polling bit, DQ7, indicates to the host system whether an Embedde d Program or Erase algorithm is in progress or completed, or whether a device is in Erase Sus pend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During Programming During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is com- plete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 250ns, then the device returns to the read mode. During Erase During the Embedded Erase algorithm, Data# Poll- ing produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. Erase on the Protected Sectors After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is acti ve for approximately 1.8us, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. How- ever, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Data# Polling Algorithm Just prior to the completion of an Embedded Program or Ease operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable(OE#) is asserted low. That is, this device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ7 will appear on successive read cycles. Table 6 shows the outputs for Data# Polling on DQ7. Fig. 9 shows the Data# Pollin g algorithm. Fig. 22 in the AC Characteristics section shows the Data# Polling timing diagram. WRITE OPERATION STATUS

standby mode, or in the erase-suspend-read mode. Table 6 shows the outputs for RY/BY#. use either OE# or CE# to control the read cycles. which sectors are erasing or erase-suspended. Table 6 shows the outputs for Toggle Bit I on DQ6. the subsection on DQ2 : (Toggle Bit II). ten, then returns to reading array data.

  1. VA = Valid address for programming. During a sector erase

any non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because

Figure 9. Data# Polling Algorithm

because the toggle bit may stop toggling as DQ5 changes to “1”. See the subsections on DQ6 and DQ2 for more information. those sectors that have been selected for erasure. Table 6 to compare outputs for DQ2 and DQ6. Fig. tion. Fig. 23 shows the toggle bit timing diagram. Figure 10. Toggle Bit Algorithm

has exceeded a specified in ternal pulse count limit. Table 6. Write Operation Status

  1. DQ5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the

section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage

may overshoot to Vcc+2.0V for periods up to 20ns. See Fig. 11.

  1. Minimum DC input voltage on pins A9, OE# and RESET# is -0.5V
  2. No more than one output may be shorted to ground at a time. Du-

ration of the short circuit should not be greater than one second. ditions for extended periods may affect device reliability. nality of the device is guaranteed. Figure 11. Maximum Overshoot Waveform

Table 7. CMOS Compatible

  1. The Icc current listed is typically less than 2 mA/MHz, with OE# at VIH , Typical condition : 25oC, Vcc = 3V
  2. Maximum ICC specifications are tested with Vcc = Vcc max.
  3. Icc active while Embedded Erase or Embedded Program is in progress.
  4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current is

Table 9. Read-Only Operations Figure 16. Read Operation Timings

Figure 17. Reset Timings Table 10. Hardware Reset ( RESET #) Description All Speed Options UnitJEDEC Std.

Table 12. Erase and Program Operations Description 70 90 UnitJEDEC Std.

  1. See the “Erase And Programming Performance” section for more information.
  1. PA = program address, PD = program data, Dout is the true data at the program address.
  2. Illustration shows device in word mode.

Figure 20. Program Operation Timings

  1. SA = sector address(for Sector Erase), VA = valid address for reading status data(see “Write Operation Status”).
  2. These waveforms are for the word mode.

Figure 21. Chip/Sector Erase Operation Timings

Figure 22. Data# Polling Timings (During Embedded Algorithms)

Figure 25. Temporary Sector Unprotect Timing Diagram Description All Speed Options UnitJEDEC Std. Table 13. Temporary Sector Unprotect

Figure 26. Sector Protect & Unprotect Timing Diagram

Table 14. Alternate CE# Controlled Erase and Program Operations Description 70 90 UnitJEDEC Std.

  1. See the “Erase And Programming Performance” section for more information.

Figure 27. Alternate CE# Controlled

  1. Figure indicates last two bus cycles of a program or erase operation.
  2. PA = program address, SA = sector address, PD = program data
  3. DQ7# is the complement of the data written to the device. Dout is the data written to the device.
  4. Waveforms are for the word mode.

Figure 28. Sector Protection timings (A9 High-Voltage Method) Table 15. AC CHARACTERISTICS

Figure 29. Sector Unprotection timings (A9 High-Voltage Method) NOTE : It is recommended to verify for all sectors.

  1. Typical program and erase times assume the following conditions: 25oC, 3.0V Vcc, 10,000 cycles. Additionally, programming

typicals assume checkerboard pattern.

  1. Under worst case conditions of 90oC, Vcc = 2.7V, 100,000 cycles.
  2. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

  1. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
  2. System-level overhead is the time required to execute the two-or-four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

  1. The device has a minimum erase and program cycle endurance of 100,000 cycles.

Table 17. LATCHUP CHARACTERISTICS Table 18. TSOP, SO, AND BGA PACKAGE CAPACITANCE Table 19. DATA RETENTION Table 16. ERASE AND PROGRAMMING PERFORMANCE

44 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. PARALLEL TO SEATING PLANE L R c 0.25MM (0.0098”) BSC B B A SEE DETAIL A DETAIL A -A- -B-SEE DETAIL B D N 2---- N 2---- 1+ 0.10 C e -C- SEATING PLANE GAUGE PLANE -X- e/2 X = A OR B b (c) WITH PLATING BASE METAL DETAIL B SECTION B-B 0.08MM (0.0031”) M C A-B S 1 N E Package TS 48 JEDEC MO-142 (B) DD Symbol MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 - 0.16 c 0.10 - 0.21 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 E 11.90 12.00 12.10 e 0.50 BASIC L 0.50 0.60 0.70 R 0.08 - 0.20 N4 8 θ 0° 5°3° NOTES: 1. Controlling dimensions are in millimeters(mm). (Dimensioning and tolerancing conforms to ANSI Y14.5M-1982) 2. Pin 1 identifier for standard pin out (Die up). 3. Pin 1 identifier for reverse pin out (Die down): Ink or Laser mark 4. To be determined at the seating plane. The seating plane is def- ined as the plane of contact that is made when the package lea- ds are allowed to rest freely on a flat horizontal surface. 5. Dimension D1 and E do not include mold protrusion. Allowable mold protrusion is 0.15mm (0.0059”) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.0031”) total in excess of b dimension at max. material condition. Minimum space between protrusion and an adjacent lead to be 0.07mm (0.0028”). 7. These dimensions apply to the flat section of the lead between 8. Lead coplanarity shall be within 0.10mm (0.004”) as measured from the seating plane. 9. Dimension “e” is measured at the centerline of the leads. PHYSICAL DIMENSIONS 48-Pin Standard TSOP (measured in millimeters)

45 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. PACKAGE xFBD 048 JEDEC N/A 6.00 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A 1.10 OVERALL THICK NESS A1 0.21 0.25 0.29 BALL HEIGHT A2 0.7 0.76 0.82 BODY THICKNESS D 8.00 BSC BODY SIZE E 6.00 BSC BODY SIZE D1 5.60 BSC BALL FOOTPRINT E1 4.00 BSC BALL FOOTPRINT MD 8 ROW MATRIX SIZED DIRECTION ME 6 ROW MATRIX SIZED DIRECTION N 48 TOTAL BALL COUNT b 0.30 0.35 0.40 BALL DIAMETER e 0.80 BSC BALL PITCH SD / SE 0.40 BSC SOLDER BALL PLACEMENT NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994 2. All dimensions are in millimeters. 3. Ball position designation per JESD 95-1, SPP-010. 4. e represents the solder ball grid pitch. 5. Symbol “MD” is the ball row matrix size in the “D” direction. Symbol “ME” is the ball column matrix size in the “E” direct- ion. N is the maximum number of solder balls for matrix si- ze MD X ME. 6. Dimension “b” is measured at the maximum ball diameter in a plane parallel to datum Z. 7. SD and SE are measured with respect to datums A and B and define the position of the center solder ball in the out- er row. When there is an odd number of solder balls in the outer row parallel to the D or E dimension, respectively, SD or SE = 0.000 when there is an even number of solder balls in the outer row, SD or SE = e/2 8. “X” in the package variations denotes part is outer qualifi- cation. 9. “+” in the package drawing indicate the theoretical center of depopulated balls. 10. For package thickness A is the controlling dimension. 11. A1 corner to be indentified by chamfer, ink mark, metalli- zed markings indention or other means. HF EG DCB A D A E A1 CORNER INDEX MARK 11 B SE PIN 1 ID. SD 76 A Z 0.20 0.08 Z 0.25 Z (4x) b

0.15 M Z A B

0.08 M Z

e PHYSICAL DIMENSIONS 48-Ball FBGA (6 x 8 mm)

46 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. ORDERNG INFORMATION Standard Products ESI standard products are available in several package and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the following: TEMPERATURE RANGE Blank : Commercial (0oC to + 70oC) I : Industrial (- 40oC to + 85oC) PACKAGE TYPE T : Standard TSOP (48-pin), W : FBGA(48-ball) SPEED OPTION 70 : 70ns 90 : 90ns SECTOR ARCHITECTURE Blank : Uniform sector T : Top sector B : Bottom sector EXCEL SEMICONDUCTOR COMPONENT GROUP 29 : Flash Memory TECHNOLOGY D : 0.18um E : 0.18um (2nd Gen.) F : 0.13um DENSITY & ORGANIZATION 400 : 4M ( x8 / x16) 800 : 8M ( x8 / x16) 160 : 16M ( x8 / x16) 320 : 32M ( x8 / x16) 640 : 64M ( x8 / x16) POWER SUPPLY AND INTERFACE F : 5.0V LV : 3.0V DL : 3.0V, Dual Bank DS : 1.8V, Dual Bank BDS : 1.8V, Burst mode, Dual Bank ES 29 LV 400 X X - XX X X X X Pb-free C : Pb product G : Pb-free product VOLTAGE RANGE Blank : 2.7 ~ 3.6V R : 3.0 ~ 3.6V

47 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Part No. ES29LV400ET-70TGI ES29LV400ET-70TCI ES29LV400EB-70TGI ES29LV400EB-70TCI ES29LV400ET-90TGI ES29LV400ET-90TCI ES29LV400EB-90TGI ES29LV400EB-90TCI Speed 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns Vcc 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V Boot Sector Top Top Bottom Bottom Top Top Bottom Bottom Package 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP Pb Pb-free Pb-free Pb-free Pb-free Ball Pitch/Size Body Size Product Selection Guide Industrial Device

48 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Part No. ES29LV400ET-70WGI ES29LV400ET-70WCI ES29LV400EB-70WGI ES29LV400EB-70WCI ES29LV400ET-90WGI ES29LV400ET-90WCI ES29LV400EB-90WGI ES29LV400EB-90WCI Speed 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns Vcc 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V Boot Sector Top Top Bottom Bottom Top Top Bottom Bottom Package 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA Pb Pb-free Pb-free Pb-free Pb-free Ball Pitch/Size 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm Body Size 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm Product Selection Guide Industrial Device

49 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Part No. ES29LV400ET-70TG ES29LV400ET-70TC ES29LV400EB-70TG ES29LV400EB-70TC ES29LV400ET-90TG ES29LV400ET-90TC ES29LV400EB-90TG ES29LV400EB-90TC Speed 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns Vcc 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V Boot Sector Top Top Bottom Bottom Top Top Bottom Bottom Package 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP Pb Pb-free Pb-free Pb-free Pb-free Ball Pitch/Size Body Size Product Selection Guide Commercial Device

50 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Part No. ES29LV400ET-70WG ES29LV400ET-70WC ES29LV400EB-70WG ES29LV400EB-70WC ES29LV400ET-90WG ES29LV400ET-90WC ES29LV400EB-90WG ES29LV400EB-90WC Speed 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns Vcc 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V Boot Sector Top Top Bottom Bottom Top Top Bottom Bottom Package 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA Pb Pb-free Pb-free Pb-free Pb-free Ball Pitch/Size 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm Body Size 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm Product Selection Guide Commercial Device

51 Rev.0B January 5, 2006ES29LV400E Excel Semiconductor inc. Excel Semiconductor Inc. 1010 Keumkang Hightech Valley, Sangdaewon1-Dong 133-1, Jungwon-Gu, Seongnam-Si, Kyongki-Do, Rep. of Korea. Zip Code : 462-807 Tel : +82-31-777-5060 Fax : +82-31-740-3798 / Homepage : www.excelsemi.com The attached datasheets are provided by Excel Semiconductor.inc (ESI). ESI reserves the right to change the spec- ifications and products. ESI will answer to your questions about device. If you have any questions, please contact the ESI office. Document Title 4M Flash Memory

Revision History

Revision Number Data Items Rev. 0A Sep. 1, 2005 Initial release version. Rev. 0B Jan. 5, 2006 Add RoHS-Compliant Package Option.