ES29LV320D EXCELSEMI | Alldatasheet

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1 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. ES29LV320D 32Mbit(4M x 8/2M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory GENERAL FEATURES

  • Single power supply operation - 2.7V -3.6V for read, program and erase operations
  • S e c t o r S t r u c t u r e - 8Kbyte x 8 boot sectors - 64Kbyte x 63 sectors - 256byte security sector
  • Top or Bottom boot block - ES29LV320DT for Top boot block device - ES29LV320DB for Bottom boot block device
  • A 256 bytes of extra sector for security code - Factory lockable - Customer lockable
  • Package Options - 48-pin TSOP - Pb-free packages - All Pb-free products are RoHS-Compliant
  • Low Vcc write inhibit
  • Manufactured on 0.18um process technology
  • Compatible with JEDEC standards - Pinout and software compatible with single-power supply flash standard DEVICE PERFORMANCE
  • Read access time - 90ns/120n for normal Vcc range ( 2.7V - 3.6V ) - 80ns for regulated Vcc range ( 3.0V - 3.6V )
  • Program and erase time - Program time : 9us/byte, 11us/word ( typical ) - Accelerated program time : 8us/word ( typical ) - Sector erase time : 0.7sec/sector ( typical )
  • Power consumption (typical values) - 200nA in standby or automatic sleep mode - 10 mA active read current at 5 MHz - 15mA active write current during program or erase
  • Minimum 100,000 program/erase cycles per sector
  • 20 Year data retention at 125 oC SOFTWARE FEATURES
  • Erase Suspend / Erase Resume
  • Data# poll and toggle for Program/erase status
  • CFI ( Common Flash Interface) supported
  • Unlock Bypass program
  • Autoselect mode
  • Auto-sleep mode after t ACC + 30ns HARDWARE FEATURES
  • Hardware reset input pin ( RESET#) - Provides a hardware reset to device - Any internal device operation is terminated and the device returns to read mode by the reset
  • Ready/Busy# output pin ( RY/BY#) - Provides a program or erase operational status about whether it is finished for read or still being progressed
  • WP#/ACC input pin - Two outermost boot sectors are protected when WP# is set to low, regardless of sector protection - Program speed is accelerated by raising WP#/ACC to a high voltage (12V)
  • Sector protection / unpr otection ( RESET# , A9 ) - Hardware method of locking a sector to prevent any program or erase operation within that sector - Two methods are provided : - In-system method by RESET# pin - A9 high-voltage method for PROM programmers
  • Temporary Sector Un protection ( RESET# ) - Allows temporary unprotection of previously protected sectors to change data in-system

2 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. The ES29LV320 is a 32 megabit, 3.0 volt-only flash memory device, organized as 4M x 8 bits (Byte mode) or 2M x 16 bits (Word mode) which is config- urable by BYTE#. Eight boot sectors and sixty three main sectors with uniform size are provided : 8Kbytes x 8 and 64Kbytes x 63. The device is man- ufactured with ESI’s proprietary, high performance and highly reliable 0.18um CMOS flash technology. The device can be programmed or erased in-sys- tem with standard 3.0 Volt Vcc supply ( 2.7V-3.6V) and can also be programmed in standard EPROM programmers. The device offers minimum endur- ance of 100,0 00 program/erase cycles and more than 10 years of data retention. The ES29LV320 offers access time as fast as 80ns or 90ns, allowing operation of high-speed micropro- cessors without wait states. Three separate control pins are provided to eliminate bus contention : chip enable (CE#), write enable (WE#) and output enable (OE#). All program and erase operation are automatically and internally performed and controlled by embed- ded program/erase algorithms built in the device. The device automatically generates and times the necessary high-voltage pulses to be applied to the cells, performs the verification, and counts the num- ber of sequences. Some status bits (DQ7, DQ6 and DQ5) read by data# po lling or toggling between consecutive read cycles provide to the users the internal status of program/erase operation: whether it is successfully done or still being progressed. Extra Security Sector of 256 bytes In the device, an extra security sector of 256 bytes is provided to customers. This extra sector can be used for various purposes such as storing ESN (Electronic Serial Number) or customer’s security codes. Once after the extra sector is written, it can be permanently locked by the device manufacturer( factory-locked) or a customer( customer-lock- able). At the same time, a lock indicator bit (DQ7) is permanently set to a 1 if the part is factory- locked, or set to 0 if it is customer-lockable. Therefore, this lock indicator bit (DQ7) can be properly used to avoid that any customer-l ockable part is used to replace a factory-locked part. The extra security sector is an extra memory space for customers when it is used as a customer-lockable version. So, it can be read and written like any other sectors. But it should be noted that the number of E/W(Erase and Write) cycles is limited to 300 times (maximum) only in the Security Sector. Special services such as ESN and factory-lock are available to customers ( ESI’s Special-Code ser- vice ) The ES29LV320 is completely compatible with the JEDEC standard command set of single power supply Flash. Commands are written to the internal command register using standard write timings of microprocessor and data can be read out from the cell array in the device with the same way as used in other EPROM or flash devices. GENERAL PRODUCT DESCRIPTION

3 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. PRODUCT SELECTOR GUIDE Family Part Number ES29LV320 Voltage Range 3.0 ~ 3.6V 2.7 ~ 3.6V Speed Option 80R 90 120 Max Access Time (ns) 80 90 120 CE# Access (ns) 80 90 120 OE# Access (ns) 35 40 50 Command Register Analog Bias Generator Address LatchBYTE# CE# OE# A<0:20> RESET# Vcc Vss Chip Enable Output Enable Logic Vcc Detector Timer/ Counter Y-Decoder X-Decoder Y-Decoder Cell Array Data Latch/ Sense Amps Input/Output Buffers Sector Switches DQ0-DQ15(A-1) RY/BY# Write State Machine WE# FUNCTION BLOCK DIAGRAM

4 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. PIN DESCRIPTION Pin Description A0-A20 21 Addresses DQ0-DQ14 15 Data Inputs/Outputs DQ15/A-1 DQ15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) CE# Chip Enable OE# Output Enable WE# Write Enable WP#/ACC Hardware Write Protect/Acceleration Pin RESET# Hardware Reset Pin, Active Low BYTE# Selects 8-bit or 16-bit mode RY/BY# Ready/Busy Output Vcc 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) Vss Device Ground NC Pin Not Connected Internally LOGIC SYMBOL DQ0 ~ DQ15 (A-1) RY/BY#BYTE# RESET# OE# CE# A0 ~ A20 WP#/ACC WE# 16 or 8

5 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. CONNECTION DIAGRAM A15 A14 A13 A12 A11 A10 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# 48-Pin Standard TSOP ES29LV320

6 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. Several device operational modes are provided in the ES29LV320 device. Commands are used to ini- tiate the device operations . They are latched and stored into internal registers with the address and data information needed to execute the device operation. The available device operational modes are listed in Table 1 with the required inputs, controls, and the resulting outputs. Each operational mode is described in further detail in the following subsec- tions. Read The internal state of the device is set for the read mode and the device is ready for reading array data upon device power-up, or after a hardware reset. To read the stored data from the cell array of the device, CE# and OE# pins should be driven to V IL while WE# pin remains at V IH. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. Word or byte mode of output data is determined by the BYTE# pin. No additional command is needed in this mode to obtain array data. Standard micro- processor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device stays at the read mode until another operation is activated by writing commands into the internal command register. Refer to the AC read cycle timing diagrams for further details ( Fig. 18 ). Word/Byte Mode Configuration ( BYTE# ) The device data output can be configured by BYTE# into one of two modes : word and byte modes . If the BYTE# pin is set at logic ‘1’, the device is configured in word mode, DQ0 - DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is configured in byte mode, and only data I/O pins DQ0 - DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8 - DQ14 are tri- stated, and the DQ15 pin is used as an input for the LSB (A-1) address. Standby Mode When the device is not se lected or activated in a system, it needs to stay at the standby mode, in which current consumption is greatly reduced with outputs in the high impedance state. DEVICE BUS OPERATIONS

7 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. The device enters the CMOS standby mode when CE# and RESET# pins are both held at Vcc +0.3V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within Vcc +0.3V, the device will be still in the standby mode, but the standby current will be greater than the CMOS standby current (0.2uA typi- cally). When the device is in the standby mode, only standard access time (t CE) is required for read access, before it is ready for read data. And even if the device is deselected by CE# pin during erase or programming operation, the device draws active cur- rent until the operation is completely done. While the device stays in the standby mode, the output is placed in the high impedance state, independent of the OE# input. The device can enter the deep power-down mode where current consumption is greatly reduced down to less than 0.2uA typically by the following three ways: - CMOS standby ( CE#, RESET# = Vcc + 0.3V ) - During the device reset ( RESET# = Vss + 0.3V ) - In Autosleep Mode ( after tACC + 30ns ) Refer to the CMOS DC characteristics Table11 for further current specification. Autosleep Mode The device automatically enters a deep power-down mode called the autosleep mode when addresses remain stable for t ACC+30ns. In this mode, current consumption is greatly reduced ( less than 0.2uA typical ), regardless of CE#, WE# and OE# control signals. Writing Commands To write a command or command sequences to ini- tiate some operations such as program or erase, the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin deter- mines whether the device accepts program data in bytes or words. Refer to “BYTE# timings for Write Operations” in the Fig. 21 for more information. Unlock Bypass Mode To reduce more the programming time, an unlock- bypass mode is provided. Once the device enters this mode, only two write cycles are required to ini- tiate the programming operation instead of four cycles in the normal program command sequences which are composed of two unlock cycles, program set-up cycle and the last cycle with the program data and addresses. In this mode, two unlock cycles are saved ( or bypassed ). Sector Addresses The entire memory space of cell array is divided into a many of small sectors: 8kbytes x 8 boot sec- tors and 64Kbytes x 63 main sectors. In erase operation, a single sector, multiple sectors, or the entire device (chip erase) can be selected for erase. The address space that each sector occu- pies is shown in detail in the Table 3-4. Accelerated Program Mode The device offers accelerated program operations through the ACC function. Th is is one of two func- tions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH (11.5~12.5V) on this pin, the device automatically enters the previously mentioned Unlock Bypass mode, temporarily unprotects any protected sec- tors, and uses the higher voltage on the pin to reduce the time required for program operations. Only two-cycle program command sequences are required because the unlock bypass mode is auto- matically activated in th is acceleration mode. The device returns to the normal operation when V HH is removed from the WP#/ACC pin. It should be noted that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the WP#/ ACC pin must not be left floating or unconnected; inconsistent or undesired behavior of the device may result. Autoselect Mode Flash memories are intended for use in applica- tions where the local CPU alters memory contents. In such applications, manufacturer and device identification (ID) code s must be accessible while the device resides in the target system ( the so called “in-system program”). On the other hand, signature codes have been typically accessed by raising A9 pin to a high voltage in PROM program- mers. However, multiplexing high voltage onto address lines is not the generally desired system design practice. Therefore, in the ES29LV320 device an autoselect command is provided to allow the system to access the signature codes without any high voltage. The conventional A9 high-voltage method used in the PROM program- ers for signature codes ar e still supported in this device.

8 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. If the system writes the autoselect command sequence, the device enters the Autoselect mode. The system can then read some useful codes such as manufacturer and device ID from the internal reg- isters on DQ7 - DQ0. Standard read cycle timings apply in this mode. In the Autoselect mode, the fol- lowing four informations can be accessed through either autoselect command method or A9 high-volt- age autoselect method. Refer to the Table 2. Manufacturer ID - Device ID - Security Sector Lock-indicator - Sector protection verify Hardware Device Reset ( RESET# ) The RESET# pin provides a hardware method of resetting the device to read array data. When the RESET# pin is driven low for at least a period of t RP , the device immediately te rminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once after the device is ready to accept another command sequence, to ensure data integrity. CMOS Standby during Device Reset Current is reduced for the duration of the RESET# pulse. When RESET# is held at Vss + 0.3V, the device draws the greatly reduced CMOS standby current ( I CC4 ) . I f R E S E T # i s h e l d a t VIL but not within Vss+0.3V, the standby current will be greater. RY/BY# and Terminating Operations If RESET# is asserted dur ing a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is completed, which requires a time of t READY (during Embedded Algo- rithms). The system can thus monitor RY/BY# to determine whether the reset operation is completed. If RESET# is asserted wh en a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo rithms). The system can read data after the RESET# pin returns to VIH, which requires a time of tRH. RESET# tied to the System Reset The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.Refer to the AC Characteristics ta bles for RESET# parame- ters and to Fig. 19 for the timing diagram. SECTOR GROUP PROTECTION The ES29LV320 features hardware sector group protection. A sector group consists of two or more adjacent sectors that are protected or unprotected at the same time. In the de vice, sector protection is performed on the group of sectors previously defined in the Table 3-4. Once after a group of sec- tors are protected, any pr ogram or erase operation is not allowed in the protected sector group. The previously protected sect ors must be unprotected by one of the unprotect methods provided here before changing data in those sectors. Sector pro- tection can be implemented via two methods. In-system protection - A9 High-voltage protection To check whether the sect or group protection was successfully executed or not, another operation called “ protect verification ” needs to be per- formed after the protection operation on a group of sectors. All protection and protect verifications pro- vided in the device are summarized in detail at the Table 1. In-System Protection “In-system protection”, the primary method, requires V ID (11.5V~12.5V) on the RESET# with A6=0, A1=1, and A0=0. This method can be imple- mented either in-system or via programming equip- ment. This method uses standard microprocessor bus cycle timing. Refer to Fig. 29 for timing diagram and Fig. 3 for the protection algorithm. A9 High-Voltage Protection “High-voltage protection”, the alternate method intended only for programming equipment, must force V ID (11.5~12.5V) on address pin A9 and con- trol pin OE# with A6=0, A1=1 and A0=0. Refer to Fig. 31 for timing diagram and Fig. 5 for the protec- tion algorithm. SECTOR UNPROTECTION The previously protected sectors must be unpro- tected before modifying any data in the sectors. The sector unprotection al gorithm unprotects all sectors in parallel. All unprotected sectors must first

sectors will need to be individually re-protected. and Fig. 4 for the unprotection algorithm. ously protected sectors to change data in-system. shows the timing diagrams for this feature. highest addresses in a top-boot-configured device.

  1. All protected sectors are unprotected (If WP#/ACC = VIL,

outermost boot sectors will remain protected).

  1. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect

10 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. SECURITY SECTOR The security sector of the ES29LV320 device pro- vides an extra flash memory space that enables permanent part identification through an Electronic Serial Number (ESN). The security sector uses a security lock-Indicator Bit (DQ7) to indicate whether or not the security sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which pre- vents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. Note that the ES29LV320 has a security sector size of 256 bytes. Security Lock-Indicator Bit (DQ7) In the device, the security sector can be provided in either factory lo cked version or cu stomer lockable version. The factory-locked version is always pro- tected when shipped from the factory, and has the security lock-Indicator Bit permanently set to a “1”. The customer-lockable version is shipped with the security sector unprotected, allowing customers to utilize the sector in any manner they choose. The customer-lockable version has the security lock- Indicator Bit permanently set to a “0”. Thus, the security lock-Indicator Bi t prevents customer-lock- able devices from being used to replace devices that are factory locked. Access to the Security Sector The security sector can be accessed through a command sequence: Enter security and Exit security sector commands. After the system has written the Enter secu rity sector command sequence, it may read the security sector by using the addresses normally occupied by the boot sec- tors. This mode of operation continues until the sys- tem issues the Exit security sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device returns to read mode in which the nor- mal boot sectors can be accessed, instead of the security sector. Factory-Locked Device In a factory-locked device, the security sector is protected when the device is shipped from the fac- tory. The security sector cannot be modified in any way. The device is available preprogrammed with one of the following: - A random, secure ESN (16 bytes ) only - Customer code through the ESI’s Special-Code service - Both a random, secure ESN and customer code through the ESI’s Special-Code service. ESN ( Electronic Serial Number ) In devices that have an ESN, a Bottom Boot device will have the 16-byte (8-w ord) ESN in sector 0 at addresses 000000h-00000Fh in byte mode (or 000000h-000007h in word mode). In the Top Boot device the ESN will be in sector 70 at addresses 3FFF00h-3FFF0Fh in byte mode (or 1FFF80h- 1FFF87h in word mode). Note that in upcoming top boot versions of this devi ce, the ESN will be located in sector 70 at addresses 3FFF00h-3FFF0Fh in byte mode (or 1FFF80h-1FFF87h in word mode). ESI’s Special-Code Service Customers may opt to have their code programmed by ESI through the ESI’s Special-Code service. ESI programs the customer’s code, with or without the random ESN. The devices are then shipped from ESI’s factory with the Security Sector permanently locked. Contact an ESI representative for details on using ESI’s Special-Code service. Customer-Lockable Device The customer lockable ve rsion allows the security sector to be freely programmed or erased and then permanently locked. Note that the ES29LV320 has a security sector size of 256 bytes (128 words). Note that the accelerated programming (ACC) and unlock bypass functions are not available when program- ming the security sector. Protection of the Security Sector The security sector area can be protected using the following procedures: Write the three-cycle “Enter security sector command” sequence, and then fol- lowing the in-system sector protect algorithm as shown in Fig. 2, exce pt that RESET# may be at either V IH or VID. This allows in-system protection of the security sector without raising any device pin to a high voltage. Note that this method is only appli- cable to the security sect or. To verify the protect/ unprotect status of the security sector. follow the algorithm shown in Fig. 2.

reading and writing the remainder of the array. memory space can be modified in any way. Figure 2. Security Sector Protect Verify abled, and the device resets to the read mode. when Vcc is greater than VLKO. or WE# do not initiate a write cycle. ically reset to the read mode on power-up.

Table 1. ES29LV320 Device Bus Operations

  1. Addresses are A20:A0 in word mode (BYTE#=VIH) , A20:A-1 in byte mode (BYTE#=VIL).
  2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section. Unprotection”. If WP#/ACC=VHH, all sectors will be unprotected.

  1. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.

Table 2. Autoselect Codes (A9 High-Voltage Method)

Table 3. Top Boot Sector Addresses (ES29LV320DT)

Table 3. Top Boot Sector Addresses (ES29LV320DT) Continued The addresses range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).

Table 4. Bottom Boot Sector Addresses (ES29LV320DB)

Table 4. Bottom Boot Sector Addresses (ES29LV320DB) Continued The addresses range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).

Table 5. CFI Query Identification String ing interfaces for long-term compatibility. CFI data at the addresses given in Tables 5-8. Table 6. System Interface String

Table 7. Device Geometry Definition

Table 8. Primary Vendor-Specific Extended Query

22 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Note that writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is required to return the device to normal operation. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever hap- pens first. Refer to the AC Characteristics section for timing diagrams. READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend com- mand, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next sectio n, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more informa- tion.The Read-Only Operati ons table provides the read parameters, and Fig. 18 shows the timing dia- gram RESET COMMAND Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to which the system was writ ing to the read mode. Once erasure begins, how ever, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to which the system was writing to the read mode. If the program command sequence is written to a sec- tor that is in the Erase Suspend mode, writing the reset command returns the device to the erase-sus- pend-read mode. Once programming begins, how- ever, the device ignore s reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend- read mode. If DQ5 goes high during a program or erase opera- tion, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase-Suspend). COMMAND DEFINITIONS

Table 9. ES29LV320 Command Definitions

90 X00 4A

90 XXX 00

55 SA 30

RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A20-A12 uniquely select any sector.

  1. The data is 99h for factory locked and 19h for not factory
  2. The data is 00h for an unprotected sector and 01h for a
  3. The Unlock Bypass command is required prior to the Unlock-
  4. The Unlock Bypass Reset command is required to return
  5. The system may read and program in non-erasing sectors,
  6. The Erase Resume command is valid only during the Erase
  7. Command is valid when device is ready to read array data

or when device is in autoselect mode.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

  1. Data bits DQ15-DQ8 are don’t care in command sequences,
  2. Unless otherwise noted, address bits A20-A11 are don’t cares.
  3. No unlock or command cycles required when device is in
  4. The Reset command is required to return to the read mode

goes high (while the device is providing status information).

  1. The fourth cycle of the autoselect command sequence

Autoselect Command Sequence section for more information.

locked or customer lockable version. Table 9 shows the address and data requirements. write cycle that contains the autoselect command. used for reading the manufacturer code. the device was previously in Erase Suspend). sequence returns the device to normal operation. Fig. 7 for the security sector operation. Figure 7. Security Sector Operation

byte, depending on the state of the BYTE# pin . pulses and verifies the programmed cell margin. gramming operation is in progress. returned to the read mode, to ensure data integrity. Figure 8. Program Operation

26 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. During the unlock-bypass mode, only the unlock- bypass program and unlo ck-bypass reset com- mands are valid. To exit the unlock-bypass mode, the system must issue the two-cycle unlock-bypass reset command sequence. The first cycle must con- tain the data 90h. The second cycle need to only contain the data 00h. The device then returns to the read mode. - Unlock Bypass Enter Command - Unlock Bypass Reset Command - Unlock Bypass Program Command Unlock Bypass Program during WP#/ACC Accelerated Program Mode The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device auto- matically enters the unlock bypass mode. The sys- tem may then write the two-cycle unlock bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH in any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Fig. 8 illustra tes the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Fig. 22 for timing diagrams. CHIP ERASE COMMAND To erase the entire memory, a chip erase command is used. This command is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up com- mand. Two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The chip erase command erases the entire memory includ- ing all other sectors except the protected sectors, but the internal erase operation is performed on a single sector base. Embedded Erase Algorithm The device does not require the system to prepro- gram prior to erase. The Embedded Erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to pro- vide any controls or ti mings during these opera- tions. Table 9 shows the address and data requirements for the chip erase command sequence. Note that the autoselect, security sector, and CFI modes are unavailable while an erase operation is in progress Erase Status Bits : DQ7, DQ6, DQ2, or RY/BY# When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section Table 10 for information on these status bits. Commands Ignored during Erase Operation Any command written during the chip erase opera- tion are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data. to ensure data in tegrity. Fig. 9 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section fo r parameters, and Fig. 23 section for timing diagrams. SECTOR ERASE COMMAND By using a sector erase command, a single sector or multiple sectors can be erased. The sector erase command is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 9 shows the address and data requirements for the sector erase command sequence. Note th at the autoselect, secu- rity sector, and CFI modes are unavailable while an erase operation is in progress. Embedded Sector Erase Algorithm The device does not require the system to prepro- gram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire mem- ory for an all zero data pattern prior to electrical erase. The system is not required to provide any con- trols or timings these operations.

system can read data from the non-erasing sector. reading array data, to ensure data integrity. ters, and Fig. 23 section for timing diagrams. program operations can be performed by the system. out period and suspends the erase operation. Figure 9. Erase Operation

  1. See Table 9 for erase command sequence
  2. See the section on DQ3 for information on the sector erase timer

28 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. Read and Program during Erase-Suspend- Read Mode After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors pro- duces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to deter- mine if a sector is actively erasing or is erase-sus- pended. Refer to the Write Operation Status section for information on these status bits (Table 10). After an erase-suspended program operation is complete, the device returns to the erase-suspend- read mode. The system can determine the status for the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to the Write Operation Status section for more information. Autoselect during Erase-Suspend- Read Mode In the erase-suspend-read mode, the system can also issue the autoselected command sequence. Refer to the Autoselect Mode and Autoselect Com- mand Sequence section for details (Table 9). Erase Resume Command To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

Figure 10. Command Diagram

30 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. In the ES29LV320 device, several bits are provided to determine the status of a program or erase oper- ation: DQ2, DQ3, DQ5, DQ6, DQ7 and RY/BY#. Table 10 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/ BY#, to determine whether an Embedded Program or Erase operation is in progress or has been com- pleted. DQ7 (DATA# POLLING) The Data# Polling bit, DQ7, indicates to the host system whether an Embedde d Program or Erase algorithm is in progress or completed, or whether a device is in Erase Sus pend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During Programming During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is com- plete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 250ns, then the device returns to the read mode. During Erase During the Embedded Erase algorithm, Data# Poll- ing produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. Erase on the Protected Sectors After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is acti ve for approximately 1.8us, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. How- ever, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Data# Polling Algorithm Just prior to the completion of an Embedded Program or Ease operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable(OE#) is asserted low. That is, this device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ7 will appear on successive read cycles. Table 10 shows the outputs for Data# Polling on DQ7. Fig. 11 shows the Data# Polling algorithm. Fig. 24 in the AC Characteristics section shows the Data# Polling timing diagram. WRITE OPERATION STATUS

standby mode, or in the erase-suspend-read mode. Table 10 shows the outputs for RY/BY#. use either OE# or CE# to control the read cycles. which sectors are erasing or erase-suspended. Table 10 shows the outputs for Toggle Bit I on DQ6. the subsection on DQ2 : (Toggle Bit II). ten, then returns to reading array data.

  1. VA = Valid address for programming. During a sector erase

any non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because

Figure 11. Data# Polling Algorithm

because the toggle bit may stop toggling as DQ5 changes to “1”. See the subsections on DQ6 and DQ2 for more information. those sectors that have been selected for erasure. Table 10 to compare outputs for DQ2 and DQ6. Fig. tion. Fig. 25 shows the toggle bit timing diagram. Figure 12. Toggle Bit Algorithm

status bits, DQ7, DQ6, DQ5, and DQ2. has exceeded a specified in ternal pulse count limit. Table 10. Write Operation Status

  1. DQ5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the

section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage

may overshoot to Vcc+2.0V for periods up to 20ns. See Fig. 13.

  1. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#

+12.0V for periods up to 20ns.

  1. No more than one output may be shorted to ground at a time. Du-

ration of the short circuit should not be greater than one second. ditions for extended periods may affect device reliability. nality of the device is guaranteed. Figure 13. Maximum Overshoot Waveform

Table 11. CMOS Compatible

  1. The Icc current listed is typically less than 2 mA/MHz, with OE# at VIH , Typical condition : 25oC, Vcc = 3V
  2. Maximum ICC specifications are tested with Vcc = Vcc max.
  3. Icc active while Embedded Erase or Embedded Program is in progress.
  4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current is

Table 13. Read-Only Operations Figure 18. Read Operation Timings

Figure 19. Reset Timings Table 14. Hardware Reset ( RESET #) Description All Speed Options UnitJEDEC Std.

Table 16. Erase and Program Operations Description 80R 90 120 UnitJEDEC Std.

  1. See the “Erase And Programming Performance” section for more information.
  1. PA = program address, PD = program data, Dout is the true data at the program address.
  2. Illustration shows device in word mode.

Figure 22. Program Operation Timings

  1. SA = sector address(for Sector Erase), VA = valid address for reading status data(see “Write Operation Status”).
  2. These waveforms are for the word mode.

Figure 23. Chip/Sector Erase Operation Timings

Figure 24. Data# Polling Timings (During Embedded Algorithms)

Figure 29. Sector/Sector Group Protect & Unprotect Timing Diagram

Table 18. Alternate CE# Controlled Erase and Program Operations Description 80R 90 120 UnitJEDEC Std.

  1. See the “Erase And Programming Performance” section for more information.

Figure 30. Alternate CE# Controlled

  1. Figure indicates last two bus cycles of a program or erase operation.
  2. PA = program address, SA = sector address, PD = program data
  3. DQ7# is the complement of the data written to the device. Dout is the data written to the device.
  4. Waveforms are for the word mode.

Figure 31. Sector Protection timings (A9 High-Voltage Method) Table 19. AC CHARACTERISTICS

Figure 32. Sector Unprotection timings (A9 High-Voltage Method) NOTE : It is recommended to verify for all sectors.

  1. Typical program and erase times assume the following conditions: 25oC, 3.0V Vcc, 10,000 cycles. Additionally, programming

typicals assume checkerboard pattern.

  1. Under worst case conditions of 90oC, Vcc = 2.7V, 100,000 cycles.
  2. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

  1. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
  2. System-level overhead is the time required to execute the two-or-four-bus-cycle sequence for the program command. See

Table 9 for further information on command definitions.

  1. The device has a minimum erase and program cycle endurance of 100,000 cycles.

Table 21. LATCHUP CHARACTERISTICS Table 22. TSOP AND BGA PACKAGE CAPACITANCE

  1. Test conditions TA = 25oC, f=1.0MHz.

Table 23. DATA RETENTION Table 20. ERASE AND PROGRAMMING PERFORMANCE

53 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. PARALLEL TO SEATING PLANE L R c 0.25MM (0.0098”) BSC B B A SEE DETAIL A DETAIL A -A- -B-SEE DETAIL B D N 2---- N 2---- 1+ 0.10 C e -C- SEATING PLANE GAUGE PLANE -X- e/2 X = A OR B b (c) WITH PLATING BASE METAL DETAIL B SECTION B-B 0.08MM (0.0031”) M C A-B S 1 N E Package TS 48 JEDEC MO-142 (B) DD Symbol MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 - 0.16 c 0.10 - 0.21 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 E 11.90 12.00 12.10 e 0.50 BASIC L 0.50 0.60 0.70 R 0.08 - 0.20 N4 8 θ 0° 5°3° NOTES: 1. Controlling dimensions are in millimeters(mm). (Dimensioning and tolerancing conforms to ANSI Y14.5M-1982) 2. Pin 1 identifier for standard pin out (Die up). 3. Pin 1 identifier for reverse pin out (Die down): Ink or Laser mark 4. To be determined at the seating plane. The seating plane is def- ined as the plane of contact that is made when the package lea- ds are allowed to rest freely on a flat horizontal surface. 5. Dimension D1 and E do not include mold protrusion. Allowable mold protrusion is 0.15mm (0.0059”) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.0031”) total in excess of b dimension at max. material condition. Minimum space between protrusion and an adjacent lead to be 0.07mm (0.0028”). 7. These dimensions apply to the flat section of the lead between 8. Lead coplanarity shall be within 0.10mm (0.004”) as measured from the seating plane. 9. Dimension “e” is measured at the centerline of the leads. PHYSICAL DIMENSIONS 48-Pin Standard TSOP (measured in millimeters)

54 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc.

55 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. ORDERNG INFORMATION Standard Products ESI standard products are available in several package and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the following: TEMPERATURE RANGE Blank : Commercial (0oC to + 70oC) I : Industrial (- 40oC to + 85oC) PACKAGE TYPE T : Standard TSOP (48-pin) W : FBGA (48-ball) SPEED OPTION 70 : 70ns 80 : 80ns 90 : 90ns 12 : 120ns SECTOR ARCHITECTURE Blank : Uniform sector T : Top sector B : Bottom sector EXCEL SEMICONDUCTOR COMPONENT GROUP 29 : Flash Memory TECHNOLOGY D : 0.18um E : 0.15um F : 0.13um DENSITY & ORGANIZATION 400 : 4M ( x8 / x16) 800 : 8M ( x8 / x16) 160 : 16M ( x8 / x16) 320 : 32M ( x8 / x16) 640 : 64M ( x8 / x16) POWER SUPPLY AND INTERFACE F : 5.0V LV : 3.0V DL : 3.0V, Dual Bank DS : 1.8V, Dual Bank BDS : 1.8V, Burst mode, Dual Bank ES 29 LV 320 X X - XX X X X X Pb-free C : Pb product G : Pb-free product VOLTAGE RANGE Blank : 2.7 ~ 3.6V R : 3.0 ~ 3.6V

56 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. Part No. ES29LV320DT-80RTGI ES29LV320DT-80RTCI ES29LV320DB-80RTGI ES29LV320DB-80RTCI ES29LV320DT-90TGI ES29LV320DT-90TCI ES29LV320DB-90TGI ES29LV320DB-90TCI ES29LV320DT-12TGI ES29LV320DT-12TCI ES29LV320DB-12TGI ES29LV320DB-12TCI Speed 80ns 80ns 80ns 80ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns Vcc 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V Boot Sector Top Top Bottom Bottom Top Top Bottom Bottom Top Top Bottom Bottom Package 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP Pb Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Ball Pitch/Size Body Size Product Selection Guide Industrial Device

57 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. Part No. ES29LV320DT-80RTG ES29LV320DT-80RTC ES29LV320DB-80RTG ES29LV320DB-80RTC ES29LV320DT-90TG ES29LV320DT-90TC ES29LV320DB-90TG ES29LV320DB-90TC ES29LV320DT-12TG ES29LV320DT-12TC ES29LV320DB-12TG ES29LV320DB-12TC Speed 80ns 80ns 80ns 80ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns Vcc 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V Boot Sector Top Top Bottom Bottom Top Top Bottom Bottom Top Top Bottom Bottom Package 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP Pb Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Ball Pitch/Size Body Size Product Selection Guide Commercial Device

58 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. Document Title 32M Flash Memory

Revision History

Revision Number Data Items Rev. 0A Nov. 10, 2003 Initial Release Version. Rev. 0B Nov. 26, 2003 1. The typical program/erase current value changed from 30mA to 15mA. 2. The Table 6 for manufacture ID is changed to 4Ah. 3. The extended temperature range is removed and the commer- cial temperature range is added. Rev. 0C Feb. 4, 2004 1. E/W cycle number is changed from 1,000,000 to 100,000. 2. CFI code is changed : 45h : 04h ----> 45h : 00h Rev. 1A Mar. 1, 2004 1. The format of datasheet is entirely changed and updated 2. 70ns product is removed 3. 80R product ( 80ns : Vcc = 3.0 ~ 3.6V) is newly added. 4. A command diagram is added. 5. Sector protection / unprotection algorithm by A9 high-voltage method is described. 6. A limitation to the maximum number of E/W cycles in the Secu- rity Sector is described (300 E/W cycles at Max.). 7. A product selection table is added. 8. Test condtions for the typical performance of program/erase : after 100,000 E/W cycles ----> after 10,000 E/W cycles Rev. 1B Apr. 23, 2004 1. The bias condition of RESET# in Table 1 for A9 high-Voltage is changed from V ID to H. 2. The bias condition of A9 in Table 1 for A9 high-Voltage method is added.

59 Rev. 2D Jan 5, 2006ES29LV320D Excel Semiconductor inc. Excel Semiconductor Inc. 1010 Keumkang Hightech Valley, Sangdaewon1-Dong 133-1, Jungwon-Gu, Seongnam-Si, Kyongki-Do, Rep. of Korea. Zip Code : 462-807 Tel : +82-31-777-5060 Fax : +82-31-740-3798 / Homepage : www.excelsemi.com The attached datasheets are provided by Excel Semiconductor.inc (ESI). ESI reserves the right to change the spec- ifications and products. ESI will answer to your questions about device. If you have any questions, please contact the ESI office. Document Title 32M Flash Memory Revision Number Data Items Rev. 2A Dec. 1, 2004 1. The preliminary is removed from the datasheet. 2. The Icc3 (max) is changed from 5uA to 10uA. 3. The Icc4 (max) is changed from 5uA to 10uA. 4. The Icc5 (max) is changed from 5uA to 10uA. 5. The size of FBGA is changed from 8mm x 9mm to 7mm x 8mm. 6. The overall thickness of FBGA , A (max), is changed from 1.20 to 1.10. Therefore, ball height (A1) and body thickness (A2) also is changed accordingly. 7. The ball diameter of FBGA, b(min), b(nom), b(max), is changed Rev. 2B Dec. 13, 2004 1. The arrow from Erase Suspend Read to Read is changed to Sector Erase. 2. V LKO(min), 2.3V is added Rev. 2C Apr. 1, 2005 1. Remove FBGA Package Type. Rev. 2D Jan. 5, 2005 1. Add RoHS-Compliant Package Option.