ES25P16 EXCELSEMI | Alldatasheet
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1 Rev. 0E May 11 , 2006ES25P16 Excel Semiconductor inc.ADVANCED INFORMATION ES25P16 16Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface ARCHITECTURAL ADVANTAGES
- Single power supply operation - 2.7V -3.6V for read and program operations
- Memory Architecture - Thirty-two sectors with 512 Kb each
- Program - Page program ( up to 256 bytes) in 1.5ms (typical) - Program cycles are on a page by page basis
- E r a s e - 0.5s typical sector erase time - 12s typical bulk erase time
- Endurance - 100,000 cycles per sector (typical)
- Data Retention - 20 years (typical)
- Parameter Page - 256 Byte page independent from main memory for parameter storage - Seperate from array, erase time < 20ms
- Device ID - JEDEC standard two-byte electronic signature - RES instruction one-byte electronic signature for backward compatibility - Manufacturer and device type ID
- Process Technology - Manufactured on 0.18um process technology
- Package Option - Industry Standard Pinouts - 8-pin SO (208mil) package - All Pb-Free devices are RoHS Compliant PERFORMANCE CHARACTERISTICS
- S p e e d - 75Mhz clock rate (maximum)
- Power Saving Standby Mode - Standby mode 50uA (max) - Deep Power Down Mode 1uA (typical) MEMORY PROTECTION FEATURES
- Memory Protection - W# pin works in conjunction with Status Register Bits to protect specified memory areas - Status Register Block Protection Bits (BP2, BP1, BP0) in status register configure parts of memory as read only SOFTWARE FEATURES
- SPI Bus Compatible Serial Interface
2 Rev. 0E May 11 , 2006ES25P16 Excel Semiconductor inc.ADVANCED INFORMATION The ES25P16 device is a 3.0 volt (2.7V to 3.6V) single power flash memory device. ES25P16 con- sists of thirty-two sector s, each with 512 Kb mem- ory. Data appears on SI input pin when inputting data into the memory and on the SO output pin when outputting data from the memory. The devices are designed to be programmed in-system with the standard system 3.0 volt Vcc supply. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory supports Sector Erase and Bulk Erase instructions. Each device requires only a 3.0 volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and regulated voltages are pro- vided for program operations. This device does not require Vpp supply. GENERAL PRODUCT DESCRIPTION BLOCK DIAGRAM PS Logic IO DATA PATH Array - RArray - L RD SRAM XDEC CS# SCK SI SO GND VCC HOLD#
3 Rev. 0E May 11 , 2006ES25P16 Excel Semiconductor inc.ADVANCED INFORMATION PIN DESCRIPTIONS Pin Description SCK Serial Clock Input SI Serial Data Input SO Serial Data Output CS# Chip Select Input W# Write Protect Input HOLD# Hold Input Vcc Supply Voltage Input GND Ground Input HOLD#SO CS# GND VCC SCK SI Connection Diagrams 8-pin Plastic Small Outline Package (SO)
4 Rev. 0E May 11 , 2006ES25P16 Excel Semiconductor inc.ADVANCED INFORMATION SIGNAL DESCRIPTION Serial Data Output (SO) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK). Serial Data Input (SI) This input signal is used to transfer data serially into the device. It receives in structions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (SCK). Serial Clock (SCK) This input signal provides the timing of the serial interface. Instructions, addresses, and data present at the Serial Data Input (SI) are latched on the ris- ing edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes after the falling edge of Serial Clock (SCK). Chip Select (CS#) When this input signal is high, the device is dese- lected and Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in Standby mode. Driving Chip Select (CS#) Low enables the devi ce, placing it in the active power mode. After power-up, a falling edge on Chip Select (CS#) is required prior to the start of any instruction. Hold (HOLD#) The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the device. During the Hold instruction, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (CS#) driven Low. Write Protect (W#) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two fol- lowing modes : CPOL = 0, CPHA = 0 CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is available from the falling edge of Serial Clock (SCK). The difference between the two modes, as shown in Figure 1, is the clock polarity when the bus master is in Standby and not transferring data: SCK remains at 0 for (CPOL = 0, CPHA = 0) SCK remains at 1 for (CPOL = 1, CPHA = 1) OPERATING FEATURES All data into and out of the device is shifted in 8-bit chunks. Page Programming To program one data byte, two instructions are required : Write Enable (W REN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the inter- nal program cycle. To spre ad this overhead, the Page Program (PP) instru ction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase, or Bulk Erase The Page Program (PP) inst ruction allows bits to be programmed from 1 to 0. Before this can be applied, the bytes of the memory need to be first erased to all 1’s (FFh) before any programming. This can be achieved in two ways :1) a sector at a time using the Sector Erase (SE) instruction, or 2) throughout the entire memory, using the Bulk Erase (BE) instruc- tion.
Write, Program, or Erase instructions. tus of the internal Write Enable Latch. protected against Program and Erase instructions. (SRWD, BP2, BP1, BP0) become read-only bits. Program or Erase cycle that is currently in progress. (SCK) being Low (as shown in Figure 3). with Serial Clock (SCK) being Low. Figure 3. Hold Condition Activation
the Software Protected Mode (SPM). before they are accepted for execution. Serial Clock (SCK) next goes Low (Figure 3). and Serial Clock (SCK) are Don’t Care. of entering the Hold condition. Table 1. Protected Area Sizes
- Each page can be individually programmed (bits are programmed from 1 to 0).
Table 2. Sector Address
9 Rev. 0E May 11 , 2006ES25P16 Excel Semiconductor inc.ADVANCED INFORMATION INSTRUCTIONS All instructions, addresses, and data are shifted in and out of the device, starting with the most signifi- cant bit. Serial Data Input (SI) is sampled on the first rising edge of Serial Clo ck (SCK) after Chip Select (CS#) is driven Low. Then, the one byte instruction code must be shifted in to the device, most signifi- cant bit first, on Serial Data Input (SI), each bit being latched on the rising edges of Serial Clock (SCK). The instruction set is listed in Table 3. Every instruction sequence starts with a one byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Sta- tus Register (RDSR), Re ad Data Bytes at higher speed (FAST_READ), Read Identification (RDID) , Read Manufacturer and Device ID (RDMD), Read Parameter Page (RDPARA) and Fast Read Parame- ter Page (FRDPARA) instructions, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out to ter- minate the transaction. In the case of a Page Program (PP), Program Parameter Page (PPP), Se ctor Erase (SE), Bulk Erase (BE), Parameter Page Erase(PE), Write Sta- tus Register (WRSR), Write Enable (WREN), Deep Power Down (DP) or Write Disable (WRDI) instruc- tion, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle con- tinues unaffected.
Table 3. Instruction Set
Erase, or Write Status Register cycle is in progress. ously, as shown in Figure 6. protected against Program and Erase instructions. if, all Block Protect (BP2, BP1, BP0) bits are 0. longer accepted for execution. Figure 6. Read Status Register (RDSR) Instruction Sequence
set by a Write Enable (WREN) instruction. not accepted for execution). the Status Register Write Disable (SRWD) bit. bits of the Status Register, can be used. Table 4. Protection Modes
- As defined by the values in the Block Protected (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
The instruction sequence is shown in Figure 10. The first byte addressed can be at any location. a single FAST_READ instruction. having any effects on the cycle that is in progress. Figure 9. Read Data Bytes (READ) Instruction Sequence
by two bytes of the device identification. JEDEC, and has a value of 4Ah for ESI products. device in the second byte (15h). effect on the cycle that is in progress. on SI during the rising edge of SCK. during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 11. Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence Figure 12. Read Manufacturer ID & Device ID (RDMD) Instruction Sequence and
3 Dummy bytes
The instruction sequence is shown in Figure 13. programmed correctly within the same page. BP0) bits (see Table 1) is not executed. Figure 13. Page Program (PP) Instruction Sequence
device sets the Write Enable Latch (WEL). the entire duration of the sequence. The instruction sequence is shown in Figure 14. (BP2, BP1, BP0) bits (see Table 1) is not executed. Figure 14. Sector Erase (SE) Instruction Sequence
Figure 15. Bulk Erase ( BE ) Instruction Sequence driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. ignored if one or more sectors are protected.
device in the lowest current mode of 1uA typical. The instruction sequence is shown in Figure 16. Figure 16. Deep Power Down ( DP ) Instruction Sequence
device out of Deep Power Down mode. entire duration of the sequence. The instruction sequence is shown in Figure 17. The instruction sequence is shown in Figure 18. Figure 17. Release from Deep Power Down Instruction Sequence
tronic Signature to be output repeatedly. receive, decode and execute instructions. This makes it convenient for more frequent updates. Figure 18. Release from Deep Power Down and Read Electronic
instruction while data is be ing sent to the device. eter Page Program instru ction will not be executed. Figure 21. Program Parameter Page (PPP) Instruction Sequence
Deep Power Down mode) and the WEL bit is reset. capacitor is generally of the order of 0.1uF). tion sequence is shown in Figure 22. still be accessed to check th e status of the WIP bit. Block Protect(BP2, BP1, BP0) bits. Figure 22. Erase Parameter Page( PE ) Instruction Sequence
Figure 23. Power-Up Timing Table 5. Power-Up Timing 00h (all Status Register bits are 0).
28 Rev. 0E May 11 , 2006ES25P16 Excel Semiconductor inc.ADVANCED INFORMATION DC CHARACTERISTICS This section summarizes the DC and AC Characteristics of the device. De signers should check that the oper- ating conditions in their circuit matc h the measurement conditions specified in the Test Specifications in Table 7, when relying on the quoted parameters. Symbol Description Test Conditions Min. Typ. Max. Unit Vcc Supply Voltage 2.7 3 3.6 V ILI Input Leakage Current V IN = GND to Vcc 1 uA ISB Standby Current CS# = Vcc 50 uA IDP Deep Power Down Current CS# = Vcc 1 10 uA ILO Output Leakage Current V IN = GND to Vcc 1 uA ICCI Active Read Current SCK = 0.1 Vcc / 0.9 Vcc SO = Open 40MHz 6 mA SCK = 0.1Vcc / 0.9 Vcc SO= Open
75 MHz 12
ICC2 Active Page Program Current CS# = Vcc 24 mA ICC3 Active WRSR Current CS# = Vcc 24 mA ICC4 Active Sector Erase Current CS# = Vcc 24 mA ICC5 Active Bulk Erase Current CS# = Vcc 24 mA VIL Input Low Voltage - 0.3 0.3 Vcc V VIH Input High Voltage 0.7 Vcc Vcc + 0.5 V VOL Output Low Voltage I OL = 1.6 mA, Vcc = Vcc min 0.4 V VOH Output High Voltage I OH = -0.1mA, Vcc - 0.2 V Notes: 1. Typical values are at TA = 25oC and Vcc = 3V Table.6 DC Characteristics
Table 7. Test Specifications Figure 24. AC Measurements I/O Waveform
- Typical program and erase times assume the following conditions : 25’C, Vcc = 3.0V ; 10,000 cycles ; checkerboard data pattern
- Under worst-case conditions of 90’C ; Vcc = 2.7V ; 100,000 cycles.
Table 8. AC Characteristics
33 Rev. 0E May 11 , 2006ES25P16 Excel Semiconductor inc.ADVANCED INFORMATION PHYSICAL DIMENSIONS S08 wide - 8 pin Plastic Small Outline 208 mils Body Width Package b (c) WITH PLATING BASE METAL SECTION A-A A 0.10 C
0.10 C//
C SEATING PLANE GAUGE PLANE L 0.07 R MIN. A A SEE DETAIL B θ L2C H DETAIL B H E E/2 b E1/2 A 5 D 3 4 e B 5 D 3 4 0.33 C
0.20 C A-B
0.25 M C A-B D
NOTES: 1. All dimensions are in both inches and millimeters. 2. Dimensioning and tolerancing per ASME Y 14.5M - 1994. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion interlead flash or protrusion shall not exceed 0.25mm per side. D and E1 dimensions are determined at datum H. 4. The package top may be smaller than the package bottom. Dime- -nsions D and E1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. But including any mismatch between the top and bottom of the plastic body. 5. Datums A and B to be determined at datum H. 6. “N” is the maximum number of terminal positions for the specified package length H. 7. The dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. Dimension “b” does not include dambar protrusion. Allowable dam- bar protrusion shall be 0.10 mm total in excess of the “b” dimension at maximum material condition. The dambar cannot not be located on the lower radius of the lead foot. 9. This chamfer feature is optional. If it is not present, then a pin 1 idenfifier must be located within the index area indicated. 10.Lead coplanarity shall be within 0.10 mm. As measured from the seating plane. Package SOC 008 (inches) SOC 008 (mm) JEDEC Symbol MIN MAX MIN MAX A 0.069 0.085 1.753 2.159 A1 0.002 0.0098 0.051 0.249 A2 0.067 0.075 1.70 1.91 b 0.014 0.018 0.356 0.483 b1 0.013 0.018 0.330 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.008 0.152 0.203 D 0.208 BSC 5.283 BSC E 0.315 BSC 8.001 BSC E1 0.208 BSC 5283 BSC e 0.050 BSC 1.27 BSC L 0.020 0.030 0.508 0.762 L1 0.055 REF 1.40 REF L2 0.010 BSC 0.25 BSC N8 8 0’ 8’ 0’ 8’ 5’ 15’ 5’ 15’ 0’ 0’ θ
Table 1. ES25P Valid Combinations Contact your local sales office for availability.
35 Rev. 0E May 11 , 2006ES25P16 Excel Semiconductor inc.ADVANCED INFORMATION Excel Semiconductor Inc. 1010 Keumkang Hightech Valley, Sangdaewon1-Dong 133-1, Jungwon-Gu, Seongnam-Si, Kyongki-Do, Rep. of Korea. Zip Code : 462-807 Tel : +82-31-777-5060 Fax : +82-31-740-3798 / Homepage : www.excelsemi.com The attached datasheets are provided by Excel Semiconductor.inc (ESI). ESI reserves the right to change the spec- ifications and products. ESI will answer to your questions about device. If you have any questions, please contact the ESI office. Document Title 16M Serial Flash Memory
Revision History
Revision Number Data Items Rev. 0A JUN. 27,2005 Initial Release Version. Rev.0B JAN. 18,2006 Added Parameter Page data to Features, and Read Manufac- turer ID & Device ID Rev.0C Mar. 14, 2006 Device Name Changed Rev.0D May. 01, 2006 The Clock Frequency was changed from 66MHz to 75MHz Rev.0E May.11, 2006 WSON package not supported