SI32172 SKYWORKS | Alldatasheet
Document overview
- Manufacturer or author: Skyworks, Inc.
- PDF pages: 46
Technical content
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 31, 2021 PRO SLIC ® S INGLE -C HIP FXS S OLUTION WITH I NTEGRATED SERIAL I NTERFACE (ISI) Si32172/3/5 Features
Applications
Description
The Si32172/3/5 devices are pin-compatible single-channel ProSLIC products that implement a complete foreign exchange station (FXS) telephony interface solution in accord ance with all relevant LSSGR, ITU, and ETSI specifications. The Si32172/3/5 ProSLIC ICs operate from a 3.3 V supply and use Skyworks Solutions’ proprietary three-wire digital Integrated Serial Interface (ISI) with 3.3 V or 1.8 V I/O to connect to SoCs with the ISI pre-integrated. The Si32172/3/5 integrated dc-dc controller automatically generates the optimal battery voltages required for each linestate. Si32172/3/5 ICs are available with voltage ratings of –110 V or –140 V to support a wide range of ringing voltages. See the Ordering Guide for the voltage rating of each Si32172/3/5 version. The Si32172/3/5 devices are available in a 5x7 mm 42-pin QFN package. Complete FXS solution in 5 x 7 mm 3-wire ISI combines PCM, SPI, and interrupt data Performs all BORSCHT functions Ideal for short to medium loops Global programmability Internal balanced or unbalanced ringing Patented low power ringing Simplified configuration and diagnostics Supported by ProSLIC API Ultra low power consumption Integrated tracking dc-dc controller with direct connection to MOSFET Wideband voice support (Si32172/3) On-hook transmission Loop or ground start operation Smooth polarity reversal A-Law/µ-Law companding, linear PCM Software-programmable parameters: Ringing frequency, amplitude, cadence, and waveshape Two-wire ac impedance Transhybrid balance DC current loop feed (10-45 mA) Loop closure and ring trip thresholds Ground key detect threshold DTMF generation DTMF detection (Si32175) Pulse metering 3.3 V operation Support for 1.8 V I/O Maximum battery up to –140 V Pb-free/RoHS-compliant packaging Customer Premise Equipment (CPE) VoIP DSL Gateways and Routers Wireless Local Loop (WLL) Integrated Access Devices (IAD) Analog Terminal Adapters (ATA) Small Office/Home Office PBX Patents pending
Ordering Information
See page 37. Pin Assignments Si32172/3/5 14 15 16 17 18 19 20 21 22 3536 37 38 39 40 41VDDIO NC NC NC NC PSCLK MISO MOSI DCFF SDCH SDCL DCDRV VDD VDDREG RST SVDC SVBAT CAPLB CAPP CAPM IREF QGND VDD STIPDC STIPAC SRINGAC SRINGDC GPIO2/SRINGC GPIO1/STIPC NC VBAT NC NC RING TIP NC EPAD2 EPAD2 EPAD1 1 42 NC NC NC NC NC Si32172/3/5
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- Electrical Specifications
Table 1. Recommended Operating Conditions1
- All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
- Operation at minimum voltage dependent upon loop conditions and dc-dc converter configuration.
Table 2. Power Supply Characteristics TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
- All specifications are for a single channel of Si3217x with a tracking flyback dc-dc converter.
- ILOOP is the dc current in the subscriber loop during the off-hook state.
Table 3. AC Characteristics for FXS TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
- The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
- Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
- The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
- VDD, VDDIO =3 . 3V , VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register
- The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
- 0 dBm 0 is equal to 0 dBm into 600 .
Table 2. Power Supply Characteristics (Continued) TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
- All specifications are for a single channel of Si3217x with a tracking flyback dc-dc converter.
- ILOOP is the dc current in the subscriber loop during the off-hook state.
1014 Hz, Any gain setting
Table 3. AC Characteristics for FXS (Continued) TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
- The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
- Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
- The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
- VDD, VDDIO =3 . 3V , VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register
- The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
- 0 dBm 0 is equal to 0 dBm into 600 .
Table 4. Linefeed Characteristics for FXS TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
20 V dc offset, ITH =1 3m A
48 V DC offset, Rloop = 1500
15 VOFFSET, 0–5 REN
48 VOFFSET, 0–5 REN
*Note: Ringing amplitude is set for 108 or 128 V peak and measured at TIP-RING using no series protection resistance. Table 5. Digital I/O Characteristics TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted. Table 6. Charge Pump Characteristics TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted. *Note: Peak drive current capability is >60 mA. Table 4. Linefeed Characteristics for FXS (Continued) TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
Table 7. Switching Characteristics—General Inputs * TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted. VIH =V DD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
Figure 1. ISI Timing Diagram Table 8. Switching Characteristics—ISI TA = 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
Table 9. Thermal Conditions
- The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
from Skyworks Solutions EVBs.
- Operation above 125 °C junction temperature may degrade device reliability. Thermal resistance values are empirical
measurements taken from Skyworks Solutions EVBs.
- The linefeed is equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction temperature
the linefeed above 150 °C junction temperature should be avoided. Table 10. Absolute Maximum Ratings1
- Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet.
- The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.
- Specification requires circuit for surge event as shown in typical application circuit.
Figure 2. Transmit and Receive Path SNDR
Figure 3. Overload Compression Performance
Figure 4. Receive Path Frequency Response
Figure 5. Transmit Path Frequency Response
Figure 8. Top Level Schematic
Figure 9. Flyback DC DC Option
Q120 does not have an alternate supplier. Figure 10. BJT Buck Boost DC-DC Option
Figure 11. PMOS Buck Boost DC-DC Option
Figure 12. Protection
Table 11. Top Level Bill of Materials
Table 12. Flyback Bill of Materials
75 V 200mW 75 Zener SOD-323 BZX384C75-V Vishay
Table 13. BJT Buck Boost Bill of Materials D120 ES1D 1.0A 200 Single DO-214AC ES1D Diodes Inc. D121 BAS16-7-F 300mA 75 Single SOT23-AXK BAS16-7-F Diodes Inc.
Table 14. PMOS Buck Boost Bill of Materials Table 15. Protection Bill of Materials
Figure 13. Si32172/3/5 Functional Block Diagram codec, hybrid, and test (BORSCHT) functions; it also supports extensive metallic loop testing capabilities. Guide‚" on page 37 for the voltage rating of each Si32172/3/5 version. an integrated monitoring ADC. to reduce external controller requirements. are software-programmable, allowing a single hardware design to meet global requirements.
ProSLIC internal linefeed circuitry provides completely programmable dc feed characteristics. low resistance, typically 160 . The constant-current region approximates infinite resistance. Figure 14. Dual ProSLIC DC Feed Characteristics automatically enter the open state in the event of a linefeed fault condition. register locations for further processing. The ADC updates all registers at a rate of 2 kHz or greater.
- Power Monitoring and Power Fault Detection
The Si32172/3/5 line monitoring functi ons are used to continuously protect against excessive power conditions. the device when a preset threshold is exceeded. state and generates a "power alarm" interrupt. supporting automatic intervention are described below.
- Excessive foreign current or voltage on TIP and/or RING.
power cross event, where 50 Hz or 60 Hz, 600 V, is connected to TIP and/or RING. Table 16. Linefeed Operating States TIP lead. Loop closure and ground key detect circuitry are active. lead is more positive than the TIP lead. detect circuitry are active. detect circuitry are active. Ringing Drives programmable ringing signal onto TI P and RING leads with or without dc offset.
maskable interrupt bit is also provided. continuous status, and a maskable interrupt bit is also provided. fundamental differences between the three ringing modes. can be programmed for a smooth or abrupt transition to accommodate different application requirements. be generated with appropriate register coefficients. reflected receive path signal from the transmit path. can be directed to either receive or transmit paths. Figure 15. Ringing Modes
30 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc .com • www.skyworksinc.com Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 31, 2021 6.9. DTMF Detection (Si32175 Only) In DTMF, two tones generate a DTMF digit. One tone is chosen from four possible row tones, and one tone is chosen from four possible column tones. The sum of these tones constitutes one of 16 possible DTMF digits. 6.10. Pulse Metering (Si32175 Only) The pulse metering system for the Si32175 is designed to inject a 12 or 16 kHz billing tone into the audio path with maximum amplitude of 0.5 V RMS at TIP and RING into a 200 ac load impedance. The tone is generated in the DSP via a table lookup that guarantees spectral purity by not allowing drift. The tone will ramp up until it reaches a host-programmed threshold, at which poin t it will maintain that level until instructed to ramp down, thus creating a trapezoidal envelope. The amplitude is controlled by an automatic gain control circuit (AGC). While the tone is ramping up, the AGC takes the feedback audio and applies it to a band pass f ilter, which is programmed for the 12 or 16 kHz frequency of interest. When the peak is detected, the ramp is stopped. See AN340 section 2.3.9 for additional details and considerations on Pulse Metering. 6.11. DC-DC Controller The Si32172/3/5 devices integrate a dc -dc controller to control an external tracking dc-dc converter which generates the high voltage supply (VBAT) to the SLIC. The tracking VBAT voltage generated from a single positive dc input is optimized to minimize power consumption by closely tracking the SLIC state, even tracking the ringing waveforms. The dc-dc controller output DCDRV is driven by an internal charge pump which allows it to connect directly to the gate of the MOSFET switch of the dc-dc converter. This eliminates the need for the MOSFET predrive circuit that is typically required when other SLICs are used with a MOSFET with VTH greater than VDD. See Table 7. 6.12. Wideband Audio Select Si32172/3 ICs support a software-selectable wideband (50 Hz–7 kHz) and narrowband (200 Hz–3.4 kHz) audio codec. The wideband mode provides an expanded audio band at a 16-bit, 16 kHz sample rate for enhanced audio quality while maintaining standar d telephony audio compat ibility. Wideband audio samples are transmitted and received on the PCM interface using two consecutive 8 kHz frames.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 31 Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 31, 2021 6.13. In-Circuit and Metallic Loop Testing (MLT) A rich set of features is provided for in-circuit testing of the FXS system and the connected telephone line (MLT): Tone generators Audio diagnostic filters Digital and analog loop-back modes Internal test load Monitor ADC DSP algorithms Using these facilities, it is possible to test the Si32172/3/5’s dc-dc conver ter, codec, line-feed, ISI bus interface, DSP, and call progress state-machine as well as testing the connected telephone line and external protection circuitry. The audio diagnostic filters on the FXS are intended to provide programmable filtering of the TX digital audio signal and calculate the peak and/or average signal power of the filters’ outputs. The signal powers are then compared to programmable thresholds. The programmable filters can be used to band-pass filter a certain tone or notch out certain tones, so that the signal power measurements are frequency selective. This filtering is useful in a telephony system because it can measure harmonic distortion, intermodulation, noise, etc. The Si32172/3/5 incorporates an internal test load with a 2.2 k nominal value that can be connected across Tip/Ring (Figure 16). The audio diagnostics system and built -in test load can be used to test the FXS interface (Si32172/3/5) itself without requiring an external lo ad, a connected line, or any rela ys. This facility can be used for production and in-service testing of such things as: Dial tone draw/break Audio quality measurements Pulse digit detection DC feed Ringtrip Polarity reversal Transmission loss MLT, e.g., GR-909, is facilitated by the built-in DSP, monitor ADC, and test load. They provide the ability to detect multiple fault conditions within the CPE as well as on the Tip/Ring pair (T-R). Thirteen different measured and/or calculated parameters are reported by the Monitor ADC. Host software for use in conjunction with the ProSLIC API is available from Skyworks Solutions. Typical MLT tests include: Hazardous Potential Test – This checks for ac voltage > 50 VRMS or dc voltage > 135 V between Tip and Ground (T-G) or Ring and Ground (R-G). Foreign Electromotive Force Test – Checks T-G or R-G for ac voltage > 10 VRMS or dc voltage > 6 V. Uses same threshold as for hazardous voltage test. Resistive Faults Test – Checks for dc resistance from T-R, T-G or R-G. Any measurement < 150 k is considered a resistive fault. Receiver-Off-Hook Test – Distinguishes between a T-R resistive fault and an off-hook condition. Ringers Test – Measures the magnitude of the connected ring load (REN) across T-R. Results are > 0.175 REN and < 5 REN for a valid load AC Line Impedance (line length) – T-R, T-G, and R-G. Generates a tone at several specific frequencies (audio band) and measures the reflected signal amplitude (complex spectrum) that comes back (with transhybrid balance filter disabled). The reflected signal is then used to calculate the line impedance based on certain assumptions of wire gauge, etc. Line Capacitance – T-R, T-G, R-G. Generates a linear ramp function with polarity reversal, and measures the time constant.
is required and this sensing path inherently meets Dielectric Withstand per GR-49 (> 1000 V). Figure 16. Internal Test Load Circuit
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 33 Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 31, 2021 7. System Interfaces 7.1. Integrated Serial Interface The Si32266/7/8/9 devices' integrated serial interface (ISI) is a three-wire proprietary interface which serializes SPI and PCM communications and interrupts, reducing the SoC interface from nine wires to three (PSCLK, MISO, MOSI). SPI communications and PCM data transfers are em bedded in the serial data. The host side of the ISI is integrated onto selected SoCs from several vendors. ISI is a point to point interface, it is not possible to daisy chain more than one ISI ProSLIC device. Both µ-255 Law (µ-Law) and A-law companding formats are supported in addition to 16-bit linear data mode with no companding. 7.2. Input/Output Voltage Selection Revision C devices have the ability to gluelessly interface directly to 1.8 V devices via the ISI and RST pins (PSCLK, MISO, MOSI, RST). The I/O voltage selection is made by attaching the desired voltage (3.3 V or 1.8 V) to the VDDIO pin (pin 1). To avoid power supply sequencing issues, VDDIO should be connected to the same supply as VDD in 3.3 V interface designs and VDDIO should be connected to VDDREG in 1.8 V interface designs. Other voltages between 1.8 V and 3.3 V can also be used for VDDIO (for example 2.5 V), but steps must be taken to ensure that the VDDIO supply comes up after the VDD supply if VDDIO is not connected to VDD or VDDREG.
34 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc .com • www.skyworksinc.com Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 31, 2021 8. Pin Descriptions: Si32172/3/5 Pin # Pin Name Description 1V D D I O IO Voltage Supply (3.3 V or 1.8 V) 2N C No Connection. Do not connect. 3N C No Connection. Do not connect. 4N C No Connection. Do not connect. 5N C No Connection. Do not connect. 6N C No Connection. Do not connect. 7N C No Connection. Do not connect.
8 PSCLK ISI Clock Input
Clock input for ISI bus timing. 9N C No Connection. Do not connect.
10 NC No Connection
11 NC No Connection
12 MISO ISI Data Output
Output data to ISI. 14 15 16 17 18 19 20 21 22 3536 37 38 39 40 41VDDIO NC NC NC NC PSCLK MISO MOSI DCFF SDCH SDCL DCDRV VDD VDDREG RST SVDC SVBAT CAPLB CAPP CAPM IREF QGND VDD STIPDC STIPAC SRINGAC SRINGDC GPIO2/SRINGC GPIO1/STIPC NC VBAT NC NC RING TIP NC EPAD2 EPAD2 EPAD1 1 42 NC NC NC NC NC
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13 MOSI ISI Data Input
Input data from ISI.
14 DCFF
DC Feed-Forward/High Current General Purpose Output Feed-forward drive of external bipolar transistors to improve dc-dc converter effi- ciency
15 SDCH
DC-DC converter monitor input used to detect overcurrent situations in the con- verter
16 SDCL
DC-DC converter monitor input used to detect overcurrent situations in the con- verter.
17 DCDRV DC Drive/Battery Switch
DC-DC converter control signal output which drives external bipolar transistor.
18 VDD IC Voltage Supply
3.3 V supply for internal circuitry.
19 VDDREG Regulated Core Power Supply
20 RST
Active low input. Hardware reset used to place all control registers in the default state.
21 SVDC DC-DC Input Voltage Sensor
Senses VDC input to dc-dc converter.
22 SVBAT VBAT Sense
Analog current input used to sense voltage on dc-dc converter output voltage lead.
23 CAPLB Calibration Capacitor
24 CAPP SLIC Stabilization Capacitor
Capacitor used in low pass filter to stabilize SLIC feedback loops.
25 CAPM SLIC Stabilization Capacitor
Capacitor used in low pass filter to stabilize SLIC feedback loops.
26 IREF Current Reference Input
Connects to an external resistor used to provide a high accuracy reference current.
27 QGND Quiet Ground Reference Input
28 VDD IC Voltage Supply
3.3 V supply for internal circuitry.
29 STIPDC TIP DC Sense
Analog current input used to sense voltage on the TIP lead.
30 STIPAC TIP AC Sense Input
Analog ac input used to detect voltage on the TIP lead. Pin # Pin Name Description
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31 SRINGAC RING AC Sense Input
Analog ac input used to detect voltage on the RING lead
32 SRINGDC RING DC Sense Input
Analog current input used to sense voltage on the RING lead.
33 GPIO2
RING Coarse Sense Input. Voltage sensing outside protection circuit.
34 GPIO1
TIP Coarse Sense Input. Voltage sensing outside protection circuit.
35 NC No Connect
This pin should be left unbiased.
36 VBAT Battery Voltage Supply
Connect to battery supply from dc-dc converter.
37 NC No Connect
This pin should be left unbiased.
38 RING RING Terminal
Connect to the RING lead of the subscriber loop.
39 NC No Connect
This pin should be left unbiased.
40 TIP TIP Terminal
Connect to the TIP lead of the subscriber loop.
41 NC No Connect
This pin should be left unbiased.
42 NC No Connect
This pin is internally connected to EPAD2 and should be left unbiased. —E P A D 1 Exposed Paddle Connect to ground. —E P A D 2 Exposed Paddle Connect to electrically-isolated low thermal impedance inner layer and/or backside thermal plane using multiple thermal vias. Pin # Pin Name Description
Table 17. Si32172/3/5 Ordering Guide
- Adding the suffix "R" to the part number (e.g., Si32172-B-FM1R) denotes tape and reel.
Table 18. Evaluation Kit Ordering Guide
110 V Flyback (MOSFET transformer based) dc-dc converter EVB
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Table 20. PCB Land Pattern
- All dimensions shown are in millimeters (mm).
- This Land Pattern Design is based on the IPC-7351 guidelines.
- All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
42 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc .com • www.skyworksinc.com Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 31, 2021 12.1. QFN PCB Design 1. PCB design must ensure sufficient thermal relief for high power operation of the device. See layout guidelines in application note AN340 for further details. 2. A minimum of four vias are required under each E-Pad. Eight or more vias are recommended. 3. Via diameter should be between 0.20 and 0.31 mm. 4. Vias should either be filled or tented on the top side of the board to prevent solder thieving under the device. 12.2. QFN Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 12.3. QFN Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 1x2 array of 1.40 mm square openings on 1.7 mm pitch should be used for the top center pad and a 2x2 array of 1.35 mm square openings on 1.7 mm pitch should be used for the bottom center pad (as shown below). 12.4. QFN Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components.
43 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc .com • www.skyworksinc.com Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 31, 2021 13. Top Markings 13.1. Top Marking 13.2. Top Marking Explanation Line 1 Marking: Device Part Number e.g., 32172-FM1 Line 2 Marking: YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the assembly release. TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. Line 3 Marking: Circle = 0.5 mm Diameter Lower Left-Justified Pin 1 Identifier Circle = 1.3 mm Diameter Center-Justified “e4” Pb-Free Symbol Country of Origin ISO Code Abbreviation e.g., KR
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