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SI32260 SKYWORKS | Alldatasheet

Document overview

• Manufacturer or author: Skyworks Solutions, Inc.
• PDF pages: 59

Technical content

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 Si32260/1 SINGLE -C HIP D UAL P RO SLIC ® Si32260/1 Features

Applications

Description

The Si32260/1 Dual ProSLIC® device s, in a single package, implement two complete foreign exchange statio n (FXS) telephony interfaces. The Si32260/1 devices operate from a 3.3 V supply and have standard PCM/SPI or GCI (8x8 mm package only) bus digital interfaces. A pair of built-in dc-dc converter controllers c an be used to automatically generate the optimal battery voltage required for each line-state, optimizing efficiency and minimizing heat generation. The Si32260/1 devices are designed to operate not only with a tracking battery supply for each channel for lowest power consumption, but also with shared battery supplies, for lowest cost. When used with shared battery supplies, the internal dc-dc controller operates in Tracking Shared Supply (TSS) mode to deliver power consumption lower than typical fixed voltage shared rail designs (shared supplies are not currently supported by the 6 x 8 mm package option). Self-testing and metallic loop testing (MLT) (e.g., GR-909) is facilitated by the built-in DSP, monitor ADC, and test load. The devices are available with linefeed voltage ratings of –110 V (Si32260) or –140 V (Si32261) to support high voltage ringing, and both devices support wideband audio for better-than-PSTN voice quality. The Si32260/1 devices are available in a 6 x 8 mm 47-pin QFN package or an 8 x 8 mm 60-pin QFN package.  Two complete FXS channels in a single 6 x 8 mm or 8 x 8 mm package  Performs all BORSCHT functions  Ideal for short- or long-loop applications  Ultra low power consumption  Internal balanced or unbalanced ringing  Patented low power ringing  Adaptive ringing  Simplified configuration and diagnostics Supported by ProSLIC API GR-909 loop diagnostics Audio diagnostics with loopback Integrated test load  Wideband voice support  On-hook transmission  Loop or ground start operation  Smooth polarity reversal  Pulse metering  PCM and SPI bus digital interfaces with programmable interrupts  Software-programmable parameters: Ringing frequency, amplitude, cadence, and waveshape Two-wire ac impedance Transhybrid balance DC current loop feed (10–45 mA) Loop closure and ring trip thresholds Ground key detect threshold  Integrated dc-dc controllers with direct connection to MOSFET  Three high voltage supply options Full tracking Tracking shared supplies Fixed rail  DTMF generator/decoder  A-Law/µ-Law companding, linear PCM  GCI/IOM-2 mode support  3.3 V operation  Pb-free/RoHS-compliant packaging  VoIP gateways and routers  xDSL IADs  Optical Network Terminals/Units (ONT/U)  Analog Terminal Adapters (ATA)  Cable eMTA  Wireless Fixed Terminals (WFT)  Wireless Local Loop (WLL)  WiMAX CPE  Private Branch Exchange (PBX)  VoIP MDU gateways Patents pending

Ordering Information

See page 45. Pin Assignments Si32260/1 8x8 mm 60TIPa N/C GPIO2A / SRINGCa GPIO1a / STIPCa SRINGDCa SRINGACa STIPACa STIPDCa CAPPa CAPMa SVBATa SVDC RSTB INTB / DTXENB FSYNC SDITHRU PCLK DATAo DATAi SDCHa SDCLa DCDRVa AUXoi AUXdrv DCDRVb SDCLb SDCHb VDDD VDDREG CSB SCLK SDO SDI SVBATb CAPMb CAPPb IREF STIPDCb STIPACb SRINGACb SRINGDCb GPIO1b / STIPCb GPIO2b / SRINGCb VDDA N/C TIPb N/C RINGb VBATb N/C BASEb N/C N/C N/C N/C N/C BAT_PO BASEa VBATa RINGa HVPAD GND PAD Si32260/1 6x8 mm HVPAD GNDPAD TIPa TIPb RINGb VBATb VBATa RINGa GPIO1a / STIPCa SRINGDCa SRINGACa STIPACa STIPDCa CAPPa CAPMa SVBATa SVDC RSTB INTB / DTXENB FSYNC PCLK DTX GPIO2A / SRINGCa DRX SDCHa SDCLa DCDRVa DCFFa DCFFb DCDRVb SDCLb SDCHb VDDD VDDREG CSB SCLK SDO SDI SVBATb CAPMb CAPPb IREF STIPDCb STIPACb SRINGACb SRINGDCb GPIO1b / STIPCb GPIO2b / SRINGCb VDDA

2 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 Functional Block Diagram SPI Control Interface PCM/ GCI Interface DSP DTMF & Tone Gen Programmable AC Impedance and Hybrid Caller ID Ringing Generator ADC DAC CODEC SLIC Linefeed Control Linefeed Monitor DC-DC Controller Line Diagnostics PLLPCLK FSYNC DRX DTX CS SDI SDO SCLK INT RST SPI Control Interface PCM/ GCI Interface DSP DTMF & Tone Gen Programmable AC Impedance and Hybrid Caller ID Ringing Generator ADC DAC CODEC DC-DC Controllers Line Diagnostics PLLPCLK FSYNC DRX DTX CS SDI SDO SCLK INT RST Si32260/1 DAC RING TIP Linefeed Channel A CODEC SLIC DAC RING TIP Linefeed Channel B CODEC SLIC ADC ADC Linefeed Control Linefeed Monitor Linefeed Control Linefeed Monitor

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 3 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 TABLE OF C ONTENTS Section Page

4 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021

1. Electrical Specifications

Table 1. Recommended Operating Conditions1

1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at

nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.

1. Operation at minimum voltage dependent upon loop conditions and dc-dc converter configuration.

Table 2. AC Characteristics

0 Hz – 12 kHz — — –28 dBm0

1014 Hz, any gain setting

1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
2. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
3. VDDD, VDDA =3 . 3V , VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600  synthesized using RS register
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5. 0 dBm0 is equal to 0 dBm into 600 .

Table 2. AC Characteristics (Continued)

1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
2. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
3. VDDD, VDDA =3 . 3V , VBAT = –52 V, no fuse resistors; RL = 600 , ZS = 600  synthesized using RS register
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5. 0 dBm0 is equal to 0 dBm into 600 .

Table 3. Power Supply Characteristics

1. All specifications are for a single channel of Si3226x with a tracking flyback dc-dc converter, when both channels are

in the same operating state.

1. ILOOP is the dc current in the subscriber loop during the off-hook state.

Table 4. Linefeed Characteristics

20 V dc offset, ITH =1 3m A —— 1m A

48 V DC offset, Rloop = 1500  —— 3m A

15 VOFFSET, 0–5 REN

48 VOFFSET, 0–5 REN

*Note: Ringing amplitude is set for 108 or 128 V peak and measured at TIP-RING using no series protection resistance.

Table 5. Digital I/O Characteristics Table 4. Linefeed Characteristics (Continued) *Note: Ringing amplitude is set for 108 or 128 V peak and measured at TIP-RING using no series protection resistance.

Figure 1. Reset Timing Diagram Table 6. Charge Pump Characteristics *Note: Peak drive current capability is >60 mA. Table 7. Switching Characteristics—General Inputs * VIH =V DD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform. Note: The count of PCLK rising edges during reset will be skewed by 1-2 clocks base d on the internal sampling of reset.

Figure 2. SPI Timing Diagram Table 8. Switching Characteristics—SPI

1. Characteristics for outputs specified with CL = 20 pF.

Table 9. Switching Characteristics—PCM Highway Interface 1

1. Characteristics for outputs specified with CL = 20 pF.
2. A constant PCLK and FSYNC are required.
3. FSYNC source is assumed to be 8 kHz under all operating conditions.
4. FSYNC Jitter Tolerance relative to PCLK.
5. Specification applies to PCLK fall to DTX tristate when that mode is selected.

Figure 5. Overload Compression Performance

Figure 6. Receive Path Frequency Response

Figure 7. Transmit Path Frequency Response

Table 10. Thermal Conditions

1. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout

from Skyworks Solutions EVBs.

1. Operation of the Si3226x above 125 °C junction temperature may degrade device reliability.
2. The Si3226x linefeed is equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction

term operation of the Si3226x linefeed above 150 °C junction temperature should be avoided. Table 11. Absolute Maximum Ratings1

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet.

1. Operation of the Si32260/1 low voltage die above 125 °C junction temperature may degrade device reliability.
2. Si32260/1 linefeed is equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction

temperature exceeds the thermal shutdown threshold.

1. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.
2. Specification requires circuit for surge event as shown in typical application circuit. Refer to “AN381: Si3226x ProSLIC

Table 11. Absolute Maximum Ratings1 (Continued)

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet.

1. Operation of the Si32260/1 low voltage die above 125 °C junction temperature may degrade device reliability.
2. Si32260/1 linefeed is equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction

temperature exceeds the thermal shutdown threshold.

1. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.
2. Specification requires circuit for surge event as shown in typical application circuit. Refer to “AN381: Si3226x ProSLIC

1. Typical Application Circuits

Figure 10. Flyback Tracking DC-DC Converter Top Level Schematic

Figure 11. Flyback Tracking DC DC1 Figure 12. Flyback Tracking DC DC2 Efficiency up to 85% depending on mode of operation.

15 C222

Efficiency up to 85% depending on mode of operation.

15 C122

Figure 15. Top Level Schematic—Low Cost Quasi Ćuk (LCQC)

Table 12. Flyback Tracking DC-DC Converter Bill of Materials—Top Level D2 (NI) DIO, DUAL Common ANODE, 200 V, 400 mA, SOT23 BAV23A Diodes Inc.

Table 13. Flyback Tracking DC-DC Converter Bill of Materials—DC-DC Table 14. Flyback Tracking DC-DC Converter Bill of Materials—Protection

Table 15. Low Cost Quasi Ćuk (LCQC) DC-DC Converter Bill of Materials—Top Level

Table 16. Low Cost Quasi Ćuk (LCQC) DC-DC Converter Bill of Materials—DC-DC D121 D221 BAV23C BAV23C Diodes Inc. D123 D223 ES1D ES1D Diodes Inc. Table 17. Low Cost Quasi Ćuk (LCQC) DC-DC Converter Bill of Materials—Protection

Figure 20. Functional Block Diagram needed for two complete analog telephone interfaces. mode provides standard telephony audio bandwidth. the optimal battery voltage required for each line-state. for the voltage rating of each version. and to reduce external controller requirements. integrated, including ac impedance and hybrid gain. single hardware design to meet global requirements.

programmable dc feed characteristics. region approximates infinite resistance. Figure 21. Dual ProSLIC DC Feed programmable operating stat es as listed in Table 18. stores the resulting values in individual RAM locations. ADC updates all registers at a rate of 2 kHz or greater. temperature threshold is exceeded. and generates a "power alarm" interrupt. automatic transition to open is not recommended. automatic intervention are described below.

1. Excessive foreign current or voltage on TIP and/or

Table 18. Linefeed Operating States TIP lead. Loop closure and ground key detect circuitry are active. lead is more positive than the TIP lead. detect circuitry are active. detect circuitry are active. Ringing Drives programmable ringing signal onto TI P and RING leads with or without dc offset.

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 33 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 5.6. Loop Closure Detection The Si32260/1 provides a completely programmable loop closure detection mechanism. The loop closure detection scheme provides two unique thresholds to allow hysteresis, and also includes a programmable debounce filter to eliminate false detection. A loop closure detect status bit provides continuous status, and a maskable interrupt bit is also provided. 5.7. Ground Key Detection The Si32260/1 provides a ground key detect mechanism using a programmable architecture similar to the loop closure scheme. The ground key detect scheme provides two unique thresholds to allow hysteresis and also includes a programmable debounce filter to eliminate false detection. A ground key detect status bit provides conti nuous status, and a maskable interrupt bit is also provided. 5.8. Ringing Generation The Si32260/1 prov ides the ability to generate a programmable sinusoidal or trapezoidal ringing waveform, with or without dc offset. The ringing frequency, wave shape, cadence, and offset are all register-programmable. Three ringing modes are supported: balanced, unbalanced, and low-power ringing (LPR). Figure 22 illustrates the fundamental differences between the three ringing modes. The dual ProSLIC’s adapti ve ringing capability allows further power savings to be realized in systems designed for long loop applications. In a long loop system, it may be necessary to generate a large ringing voltage to ensure that suffic ient voltage is presented to a phone at the far end of the loop. However, in situations when a short loop is connected to an FXS interface that was designed with the ability to ring long loops, the large ringing vo ltage in comb ination with a low resistance load will result in excessive and unnecessary power consumption. Skyworks Solutions’ Si32260/1 dual ProSLICs eliminate this unnecessary power consumption with their adaptive ringing capability. The ProSLIC aut omatically senses when excessive power is being consumed in the line feed circuit (due to the lower resistance of a short loop) and will iteratively reduce the ri nging amplitude to a voltage that is appropriate for the load.

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 35 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 5.9. Polarity Reversal The Si32260/1 supports polarity reversal for message waiting and various other signaling modes. The ramp rate can be programmed for a smooth or abrupt transition to accommodate different application requirements. 5.10. Two-Wire Impedance Synthesis The ac two-wire impedance synthesis is generated on- chip using a DSP-based scheme to optimally match the output impedance of the Si32260/1 to the reference impedance. Most real or complex two-wire impedances can be generated by using the coefficient generator software to simulate the desired line conditions and generate the required register coefficients. 5.11. Transhybrid Balance Filter The trans-hybrid balance function is implemented on- chip using a DSP-based scheme to effectively cancel the reflected receive path signal from the transmit path. The coefficient generator software is used to optimize the filter coefficients. 5.12. Tone Generators The Si32260/1 includes two digital tone generators that allow a wide variety of single- or dual-tone frequency and amplitude combinations. Each tone generator has its own set of registers that hold the desired frequency, amplitude, and cadence to allow generation of DTMF and call progress tones for different requirements. The tones can be directed to either receive or transmit paths. 5.13. DTMF Detection The Dual ProSLIC performs DTMF detection. 5.14. Pulse Metering The pulse metering system fo r the Si32260/1Si32260/1 is designed to inject a 12 or 16 kHz billing tone into the audio path with maximum amplitude of 0.5 V RMS at TIP and RING into a 200  ac load impedance. The tone is generated in the DSP via a table lookup that guarantees spectral purity by not a llowing drift. The tone will ramp up until it reaches a host-programmed threshold, at which point it will maintain th at level until instructed to ramp down, thus creating a trapezoidal envelope. See AN381 for additional details and considerations on Pulse Metering. 5.15. DC-DC Controller The Si3226x integrates two dc-dc controllers that can be used to control external dc-dc converters to generate high voltage supplies to the SLIC channels. The integrated line feeds are designed to work with either a single tracking high voltage input, one for each channel, or with two high voltage supplies shared by both channels. In tracking mode, the VBATa and VBATb inputs are each directly connected to the high voltage output of two tracking dc-dc converters, one for channel A and one for channel B. In tracking mode, the VBAT voltage for each channel is optimized to minimize power consumption by closely tracking the SLIC state, even tracking the ringing waveforms (see section 2.1 for schematics). In shared supply mode, a single flyback dc-dc converter generates two rails using two taps on the dc-dc converter's transformer. External power offloading transistors are used to lower the power dissipated inside the Si3226x device by shunting excess power away. In tracking shared supply (TSS) mode, in a two channel implementation, the dc-dc converter is controlled by the integrated dc-dc controller which allows the high voltage and low voltage outputs from the dc-dc converter to track the combined state of the two channels of the Si3226x ProSLIC, including the ringing waveforms. Using the same schematic, the TSS mode of operation reduces system power consumption significantly when compared to typical fixed rail shared supply designs (see section 2.2 for schematics). Both of the dc-dc contro ller outputs DCDRVa/b are driven by an internal charge pump which allows them to connect directly to the gate of the MOSFET switch of a flyback (transformer based) dc-dc converter. This connection eliminates the need for the MOSFET pre- drive circuit that is required when VTH is greater than VDD. See Table 7. 5.16. Wideband Audio The Si32260/1 dual ProSLIC devices support a software-selectable wideband (50 Hz–7 kHz) and narrowband (200 Hz–3.4 kHz) audio codec. The wideband mode provides an expanded audio band at a 16-bit, 16 kHz sample rate for enhanced audio quality while maintaining stand ard telephony audio compatibility. In wideband op eration, two time slots are used to transmit the wideband signal and each slot contains 8-bits of the 16-bit sample. These two time slots are transmitted and received half a frame apart, but within the same 8 kHz frame.

telephone line and external protection circuitry. the ProSLIC API is availabl e from Skyworks Solutions. Tip and Ground (T-G) or Ring and Ground (R-G). R-G for ac voltage > 10 VRMS or dc voltage > 6 V. Uses same threshold as for hazardous voltage test. considered a resistive fault. T-R resistive fault and an off-hook condition. based on certain assumptions of wire gauge, etc. Dielectric Withstand per GR-49 (> 1000 V). Figure 24. Si32260/1 Internal Test Load Circuit

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 37 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 6. System Interfaces 6.1. SPI Control Interface The controller interface to the Si32260/1 is a 4-wire interface modeled after microcontroller and serial peripheral devices. The inte rface consists of a clock (SCLK), chip select (CS), se rial data input (SDI), and serial data output (SDO). In addition, the ProSLIC devices feature a serial data through output (SDITHRU 8x8 mm package only) to support operation of up to 16 channels using a single chip select line. Each FXS port occupies one SPI channel. The device operates with both 8-bit and 16-bit SPI controllers. 6.2. PCM Interface and Companding The Si32260/1 contains a flexible, programmable interface for the transmission and reception of digital PCM samples. PCM data transf er is controlled by the PCM clock (PCLK) and frame sync (FSYNC) inputs as well as the PCM Mode Select, PCM Transmit Start, and PCM Receive Start settings. The interface can be configured to support from 8 to 128 8-bit time slots in each 125 µs frame, corresponding to a PCM clock (PCLK) frequency range of 512 kHz to 8.192 MHz. 1.544 MHz is also supported. The Si32260/1 supports both µ-255 Law (µ-Law) and A- law companding formats in addition to 16-bit linear data mode with no companding.

38 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 7. Pin Descriptions: Si32260/1 7.1. Si32260/61 6x8 mm Package Pin # Pin Name Description 1 GPIO2a/SRINGCa General Purpose I/O or RING Coarse Sense Input—Channel A. RING channel A Voltage sensing outside protection circuit. 2 GPIO1a/STIPCa General Purpose I/O or TIP Coarse Sense Input—Channel A. TIP channel A voltage sensing outside protection circuit. 3 SRINGDCa RING DC Sense Input—Channel A. Analog dc input to sense voltage on the channel A RING lead. 4S R I N G A C a RING AC Sense Input—Channel A. Analog ac input to sense voltage on the channel A RING lead. 5S T I P A C a TIP AC Sense Input—Channel A. Analog ac input to sense voltage on the channel A TIP lead. 6 STIPDCa TIP DC Sense Input—Channel A. Analog dc input to sense voltage on the channel A TIP lead. 7 CAPPa SLIC Stabilization Capacitor—Channel A. Capacitor used in low pass filter. 8C A P M a SLIC Stabilization Capacitor—Channel A. Capacitor used in low pass filter. 9 SVBATa VBAT Sense—Channel A. Input to sense voltage on VBAT. 10 SVDC DC-DC Input Voltage Sensor. Senses VDC input to dc-dc converters. HVPAD GNDPAD TIPa TIPb RINGb VBATb VBATa RINGa GPIO1a / STIPCa SRINGDCa SRINGACa STIPACa STIPDCa CAPPa CAPMa SVBATa SVDC RSTB INTB / DTXENB FSYNC PCLK DTX GPIO2A / SRINGCa DRX SDCHa SDCLa DCDRVa DCFFa DCFFb DCDRVb SDCLb SDCHb VDDD VDDREG CSB SCLK SDO SDI SVBATb CAPMb CAPPb IREF STIPDCb STIPACb SRINGACb SRINGDCb GPIO1b / STIPCb GPIO2b / SRINGCb VDDA

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 39 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021

11 RSTB

Reset Input. Active low input. Hardware reset used to place all control registers in the default state.

12 INTB/DTXENB

Interrupt Output or Transmit PCM Data Output Enable. Maskable interrupt output or output enable for PCM data output. Open drain output for wire-ORed operation.

13 FSYNC

Frame Sync Clock Input. 8 kHz frame synchronization signal for the PCM bus. May be short or long pulse format. 14 PCLK PCM Bus Clock Input. Clock input for PCM bus timing. 15 DTX Transmit PCM Data Output. Output data to PCM bus. 16 DRX Transmit PCM Data Input. Input data from PCM bus. 17 SDCHa DC Monitor—Channel A. DC-DC converter monitor input used to detect overcurrent situations. 18 SDCLa DC Monitor—Channel A. DC-DC converter monitor input used to detect overcurrent situations. 19 DCDRVa DC Drive—Channel A. DC-DC converter control signal output which drives external transistor. 20 DCFFa DC Flexible Function—Channel A. DC-DC controller flexible function I/O—channel A. 21 DCFFb DC Flexible Function—Channel B . DC-DC controller flexible function I/O—channel B. 22 DCDRVb DC Drive—Channel B. DC-DC converter control signal output which drives external transistor. 23 SDCLb DC Monitor—Channel B . DC-DC converter monitor input used to detect overcurrent situations. 24 SDCHb DC Monitor—Channel B. DC-DC converter monitor input used to detect overcurrent situations. 25 VDDD IC Voltage Supply. Digital power supply for internal digital circuitry. 26 VDDREG Regulated Core Power Supply.

27 CSB

Chip Select Input. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. 28 SCLK Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. 29 SDO Serial Port Data Output. Serial port control data output. Pin # Pin Name Description

40 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 30 SDI Serial Port Data Input. Serial port control data input. 31 SVBATb VBAT Sense—Channel B. Input to sense voltage on VBAT. 32 CAPMb SLIC Stabilization Capacitor—Channel B. Capacitor used in low pass filter. 33 CAPPb SLIC Stabilization Capacitor—Channel B. Capacitor used in low pass filter. 34 IREF Current Reference Input. Connects to an external resistor used to provide a high accuracy reference current. 35 STIPDCb TIP DC Sense Input—Channel B. Analog dc input to detect voltage on the channel B TIP lead. 36 STIPACb TIP AC Sense Input—Channel B. Analog ac input to sense voltage on the channel B TIP lead. 37 SRINGACb RING AC Sense Input—Channel B. Analog ac input to sense voltage on the channel B RING lead. 38 SRINGDCb RING DC Sense Input—Channel B. Analog dc input to sense voltage on the channel B RING lead. 39 GPIO1b/STIPCb General Purpose I/O or TIP Coarse Sense Input—Channel B. TIP channel A voltage sensing outside protection circuit. 40 GPIO2b/SRINGCb General Purpose I/O or RING Coarse Sense Input—Channel B. RING channel A Voltage sensing outside protection circuit. 41 VDDA Analog Supply Voltage. Analog power supply for internal analog circuitry. 42 TIPb TIP Terminal—Channel B. Connect to the TIP lead of the channel B subscriber loop. 43 RINGb RING Terminal—Channel B . Connect to the RING lead of the channel B subscriber loop. 44 VBATb Battery Voltage Supply—Channel B. Connect to battery supply for Channel B. 45 VBATa Battery Voltage Supply—Channel A. Connect to battery supply for Channel A. 46 RINGa RING Terminal—Channel A. Connect to the RING lead of the channel A subscriber loop. 47 TIPa TIP Terminal—Channel A. Connect to the TIP lead of the channel A subscriber loop.

48 HVPAD

Exposed paddle. Connect to electrically-isolated low thermal impedance inner layer and/or backside thermal plane using multiple thermal vias. 49 GNDPAD Exposed paddle. Connect to ground. Pin # Pin Name Description

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 41 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 7.2. Si32260/61 8x8 mm Package Pin # Pin Name Description 1T I P a TIP Terminal—Channel A. Connect to the TIP lead of the channel A subscriber loop. 2N / C No Connect. This pin should be left unconnected. 3 GPIO2a/SRINGCa General Purpose I/O or RING Coarse Sense Input—Channel A. RING channel A Voltage sensing outside protection circuit. 4 GPIO1a/STIPCa General Purpose I/O or TIP Coarse Sense Input—Channel A. TIP channel A voltage sensing outside protection circuit. 5 SRINGDCa RING DC Sense Input—Channel A. Analog dc input to sense voltage on the channel A RING lead. 6S R I N G A C a RING AC Sense Input—Channel A. Analog ac input to sense voltage on the channel A RING lead. 7S T I P A C a TIP AC Sense Input—Channel A. Analog ac input to sense voltage on the channel A TIP lead. 8 STIPDCa TIP DC Sense Input—Channel A. Analog dc input to sense voltage on the channel A TIP lead. 9 CAPPa SLIC Stabilization Capacitor—Channel A. Capacitor used in low pass filter. 60TIPa N/C GPIO2A / SRINGCa GPIO1a / STIPCa SRINGDCa SRINGACa STIPACa STIPDCa CAPPa CAPMa SVBATa SVDC RSTB INTB / DTXENB FSYNC SDITHRU PCLK DATAo DATAi SDCHa SDCLa DCDRVa AUXoi AUXdrv DCDRVb SDCLb SDCHb VDDD VDDREG CSB SCLK SDO SDI SVBATb CAPMb CAPPb IREF STIPDCb STIPACb SRINGACb SRINGDCb GPIO1b / STIPCb GPIO2b / SRINGCb VDDA N/C TIPb N/C RINGb VBATb N/C BASEb N/C N/C N/C N/C N/C BAT_PO BASEa VBATa RINGa HVPAD GND PAD

42 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 10 CAPMa SLIC Stabilization Capacitor—Channel A. Capacitor used in low pass filter. 11 SVBATa VBAT Sense—Channel A. Input to sense voltage on VBAT. 12 SVDC DC-DC Input Voltage Sensor. Senses VDC input to dc-dc converters.

13 RST

Reset Input. Active low input. Hardware reset used to place all control registers in the default state.

14 INTB/DTXENB

Interrupt Output or Transmit PCM Data Output Enable. Maskable interrupt output or output enable for PCM data output. Open drain output for wire-ORed operation.

15 FSYNC

Frame Sync Clock Input. 8 kHz frame synchronization signal for the PCM bus. May be short or long pulse format. 16 SDITHRU SDI Pass-Through. Cascaded SDI output signal for daisy-chain mode. 17 PCLK PCM Bus Clock Input. Clock input for PCM bus timing. 18 DTX Transmit PCM Data Output. Output data to PCM bus. 19 DRX Transmit PCM Data Input. Input data from PCM bus. 20 SDCHa DC Monitor—Channel A. DC-DC converter monitor input used to detect overcurrent situations. 21 SDCLa DC Monitor—Channel A. DC-DC converter monitor input used to detect overcurrent situations. 22 DCDRVa DC Drive—Channel A. DC-DC converter control signal output which drives external transistor. 23 DCFFa DC Flexible Function—Channel A. DC-DC controller flexible function I/O—channel A. 24 DCFFb DC Flexible Function—Channel B . DC-DC controller flexible function I/O—channel B. 25 DCDRVb DC Drive—Channel B. DC-DC converter control signal output which drives external transistor. 26 SDCLb DC Monitor—Channel B . DC-DC converter monitor input used to detect overcurrent situations. 27 SDCHb DC Monitor—Channel B. DC-DC converter monitor input used to detect overcurrent situations. 28 VDDD IC Voltage Supply. Digital power supply for internal digital circuitry. 29 VDDREG Regulated Core Power Supply. Pin # Pin Name Description

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 43 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021

30 CSB

Chip Select Input. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. 31 SCLK Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. 32 SDO Serial Port Data Output. Serial port control data output. 33 SDI Serial Port Data Input. Serial port control data input. 34 SVBATb VBAT Sense—Channel B. Input to sense voltage on VBAT. 35 CAPMb SLIC Stabilization Capacitor—Channel B. Capacitor used in low pass filter. 36 CAPPb SLIC Stabilization Capacitor—Channel B. Capacitor used in low pass filter. 37 IREF Current Reference Input. Connects to an external resistor used to provide a high accuracy reference current. 38 STIPDCb TIP DC Sense Input—Channel B. Analog dc input to detect voltage on the channel B TIP lead. 39 STIPACb TIP AC Sense Input—Channel B. Analog ac input to sense voltage on the channel B TIP lead. 40 SRINGACb RING AC Sense Input—Channel B. Analog ac input to sense voltage on the channel B RING lead. 41 SRINGDCb RING DC Sense Input—Channel B. Analog dc input to sense voltage on the channel B RING lead. 42 GPIO1b/STIPCb General Purpose I/O or TIP Coarse Sense Input—Channel B. TIP channel A voltage sensing outside protection circuit. 43 GPIO2b/SRINGCb General Purpose I/O or RING Coarse Sense Input—Channel B. RING channel A Voltage sensing outside protection circuit. 44 VDDA Analog Supply Voltage. Analog power supply for internal analog circuitry. 45 N/C No Connect. This pin should be left unconnected. 46 TIPb TIP Terminal—Channel B. Connect to the TIP lead of the channel B subscriber loop. 47 N/C No Connect. This pin should be left unconnected. 48 RINGb RING Terminal—Channel B . Connect to the RING lead of the channel B subscriber loop. 49 N/C No Connect. This pin should be left unconnected. Pin # Pin Name Description

44 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 50 VBATb Battery Voltage Supply—Channel B. Connect to battery supply for Channel B. 51 N/C No Connect. This pin should be left unconnected. 52 BASEb Offloading Base Control Output—Channel B . Output to control base of power offloading transistor (fixed rail). 53 N/C No Connect. 54 BAT_PO Power Offloading Battery Voltage Input. Output from fixed rail dc-dc converter. 55 BASEa Offloading Base Control Output—Channel A. Output to control base of power offloading transistor (fixed rail). 56 N/C No Connect. This pin should be left unconnected. 57 VBATa Battery Voltage Supply—Channel A. Connect to battery supply for Channel A. 58 N/C No Connect. This pin should be left unconnected. 59 RINGa RING Terminal—Channel A. Connect to the RING lead of the channel A subscriber loop. 60 N/C No Connect. This pin should be left unconnected.

61 HVPAD

Exposed paddle. Connect to electrically-isolated low thermal impedance inner layer and/or backside thermal plane using multiple thermal vias. 62 GNDPAD Exposed paddle. Connect to ground. Pin # Pin Name Description

Table 19. Si32260/61 Ordering Guide1

1. Adding the suffix "R" to the part number (e.g., Si32260-C-FM1R) denotes tape and reel.

Table 20. Evaluation Kit Ordering Guide *Note: Supports VBAT up to –125 V with minor component substitutions (see AN381).

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 47 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 9. Product Identification The product identification number is a finished goods part number or is specified by a finished goods part number, such as a special customer part number. Example: Si32260-C-FM1R Shipping Option Blank = Trays R = Tape and ReelProduct Revision Product Designator Package Type M2 = QFN/LGA-47 M1 = QFN/LGA-60 Part Type / Lead Finish F = Commercial / RoHS-Compliant G = Industrial / RoHS-Compliant

Figure 25. 47-pin QFN Package Table 21. 47-Pin QFN Package Diagram Dimensions

1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Figure 26. 60-Pin (QFN/LGA Package) Table 22. 60-Pin QFN/LGA Package Diagram Dimensions

1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 51 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 11. PCB Land Pattern—LGA Package 11.1. Land Pattern and Solder Mask Design–QFN-47 (6x8 mm) Dimension mm C1 5.90 C2 7.90 D2 3.02 D4 3.22 E0 . 5 0 F0 . 8 0 X1 0.30 X2 4.05 Y1 0.85 Y3 2.10 Y5 3.40 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Ma terial Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

52 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 11.2. Land Pattern and Solder Mask Design–QFN-60 (8x8 mm) Dimension mm C1 7.90 C2 7.90 D1 7.85 D2 7.85 E0 . 5 0 f0 . 6 5 X1 0.30 X2 6.35 Y1 0.85 Y2 2.46 Y3 3.39 Y4 6.37 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 53 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 11.3. Thermal via Layout–QFN-47 (6x8 mm) The thermal via layout rules in section “11.4. Ther mal via Layout–QFN-60 (8x8 mm)” for the QFN-60 package apply, except that it is not requir ed to meet the minimum dimension d > 1.0 mm for the via edge to pin pad metal spacing, as described in note 4. 11.4. Thermal via Layout–QFN-60 (8x8 mm) Dimension Min Max d1 . 0 0 — Kx — 5.05 Ky — 5.05 Notes: 1. High-Tg PCB materials (Tg ≥ 170 °C) are recommended for Pb-Free reflow profiles, per standard industry practice. 2. The customer’s PCB design must provide sufficient thermal dissipation for high power operation of the device. See layout guidelines in application note, “AN381: Si3226x ProSLIC Designer’s Guide”, for further details. 3. A minimum of eight thermal vias are required in each center pad. The recommended via diameter is 0.20–0.30 mm (8–12 mils). 4. Thermal vias placed in the center pads must have a minimum spacing of 1.0 mm from the edge of the via to the closest pin pad metal (d ≥ 1.0 mm). 5. Vias may be placed as desired within the non-hatched area of the center pads. 6. Vias placed within the center pad areas must be either filled, or tented on the top side of the board, to prevent solder thieving from under the device.

54 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 11.5. Stencil Aperture Design–QFN-47 (6x8 mm) Dimension mm C1 5.90 C2 7.90 E0 . 5 0 F0 . 8 0 G1 . 3 0 H1 . 8 0 P1 1.80 P2 0.73 P3 2.33 P4 2.08 X1 0.30 Y1 0.85 Notes: Stencil Design 1. A stainless steel, laser-cut and electr o-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). Card Assembly 3. A No-Clean, Type-3 solder paste is recommended. 4. The recommended card reflow prof ile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 55 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 11.6. Stencil Aperture Design–QFN-60 (8x8 mm) Dimension mm D1 7.85 D2 7.85 E0 . 5 0 f0 . 6 5 P1 2.50 P2 0.85 P3 2.38 P4 2.62 P5 1.76 P6 1.35 X1 0.30 X2 1.25 Y1 0.85 Y2 1.40 Y3 1.05 Notes: Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). Card Assembly 3. A No-Clean, Type-3 solder paste is recommended. 4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

56 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 12. Top Markings 12.1. Top Marking (47-Pin LGA) 12.2. Top Marking Explanation (47-pin LGA) Mark Method: Laser Font Size: 2.0 Point (28 mils) Right-Justified Line 1 Marking: Customer Part Number 32260-FM2 Line 2 Marking: YY = Year WW = Work Week Assigned by the Assembly House. Cor- responds to the year and work week of the assembly release. TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. Line 3 Marking: Circle = 0.75 mm Diameter Lower-Left Justified Pin 1 Identifier Circle = 1.3 mm Diameter Center-Justified “e4” Pb-Free Symbol Country of Origin ISO Code Abbreviation KR

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 57 Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 12.3. Top Marking (60-Pin LGA) 12.4. Top Marking Explanation (60-Pin LGA) 13. Si3226x Support Documentation  AN381: Si3226x ProSLIC Designer's Guide Note: Refer to www.skyworksinc.com for a current list of support documents for this product family. Mark Method: Laser Font Size: 2.0 Point (28 mils) Right-Justified Line 1 Marking: Device Part Number Si32260-FM1 Line 2 Marking: YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to the year and work week of the assembly release. TTTTTT = Mfg Code Manufacturing Code from the Assembly Pur- chase Order form. Line 3 Marking: Circle = 1.3 mm Diameter Center-Justified “e4” Pb-Free Symbol Country of Origin ISO Code Abbreviation KR Line 4 Marking: Circle = 0.75 mm Diameter Lower Left-Justified Pin 1 Identifier

58 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021 DOCUMENT CHANGE LIST: Revision 0.1 to Revision 0.2  Corrected (reversed) EPAD1 & EPAD2 in pin assignment drawings and pin descriptions  Added table of charge pump characteristics  Added PCLK jitter tolerance  Updated flyback dc-dc converter application schematics and BOM  Added fixed rail dc-dc converter application schematics and BOM  Updated ordering guide to revision B  Added package top markings information  Added PCB land pattern and soldering notes Revision 0.2 to Revision 0.3  Added Tracking Shared Supply (TSS) mode  Added thermal resistance and maximum continuous power dissipation  Completed Table 3 with power consumption data  Changed the name of the fixed rail dc-dc application circuit to Tracking Shared Supply (TSS)  Corrected description of wideband operation  Changed ordering information to revision C Revision 0.3 to Revision 0.31  Corrected IDD values in Table 3. They were showing IDD for two channels, now only one channel as specified. Revision 0.31 to Revision 1.0  Corrected Jitter Tolerance to be 8 nsRMS maximum.  Updated the protection schematics for the TSS dc- dc converter application. Pins "A" of the TISP61089BDR are now connected to GROUND, and the pin labeled "G" (the GATE) is now connected to VBAT.  Updated order of data sheet elements in accordance with new style guide SOPs.  Cosmetic updates to schematics and BOMs.  Changed test load impedance to 2.2 k (was listed as 5.3 k or 600   Increased SDITHRU and RST maximum leakage current to 80 µA.  Increased absolute maximum VBAT, TIP , and RING voltages to –142 V (was –140 V).  Added absolute maximum positive voltage specs for TIP and RING of +0.4 V. Revision 1.0 to Revision 1.1  Added LGA package information Revision 1.1 to Revision 1.2  Added 6x8 mm QFN/LGA-47 package option  Added theta jb and jc values (for all package sizes)  Corrected some text formatting in the Power Supply Characteristics table and changed the off hook line feed current condition to 20 mA for consistency with other ProSLIC data sheets.  Renamed EPADs to be more descriptive: HVPAD and GNDPAD.  Updated EVB part numbers and added PMOS buck boost dual footprint EVB.  Removed reset rise time spec from Table 7. Revision 1.2 to Revision 1.3  Corrected 6x8 mm package land pattern diagram in section 11.1 on p.52. Revision 1.3 to Revision 1.4  Updated EVB part numbers.  Changed RTEST (Test Load Impedance) specification in Table 4 to replace typical value with a range from minimum to maximum.  Removed notes specifying voltage and temperature conditions for Tables 2 through 9.  Replaced TSS DC-DC converter reference schematics and bill of materials with (Low Cost Quasi-Ćuk (LCQC) reference schematics and bill of materials.  Removed NBA Part Numbers from Ordering Guide.  Updated 6x8 LGA package dimension tolerances: Dimension E2 NOM changed from 3.00 to 3.10, and Max changed from 3.05 to 3.25. Dimension E3 NOM changed from 2.05 to 2.15, and Max from 2.10 to 2.30.  Added section listing support documentation.  Removed NBA package references throughout document.

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