ER3400

ER3400 ETC1 | Alldatasheet

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Technical content

4096 Bit Electrically Alterable Read Only Memory

FEATURES

@ Latched address and data inputs i uu

8 Word or block alterable Top View

@ 10 year data storage for ER3400 Voa(-20v) er 7 2B Ves (+8¥) @ 1 year data storage for ER34001R at +85°C. Voo (-12v) 2 2D as @ and ER3400HR at +95°C ap 3 20D aa = TTL compatible with pull-up resistors on inputs args Abd sled @ Tri-state outputs aes Sid oiled 1 Read access time: 900ns max. we vba 1 Write time: 1ms. Erase time: 10ms oo RBS '® 10° Read cycles/word between refreshes vetony do «Mb WE 10’ Read cycles/word tor ER34001R and ER3400HR: sq 8h 00 Feil © Two extended temperature ranges edu zbor pep DESCRIPTION ESP the £3400 is a 1024 x 4 bit fully decoded Electrically Alterable BLOCK DIAGRAM Po Read Only Memory fabricated in General Instrument's proven o e = f=tesil MNOS technology. Address, control and data inputs are latched PEGS on board the device thus releasing these lines during Erase and PR Write operations. Selection of one of the four modes of operation Fee and C1. CEis used for chip selection and latching of address and E=§ control lines. WE is used to sample and atch input data on D0-D3 le = during a Write operation. e oa Power sequencing protection circuitry is provided on the ER3400 or ute to protect against the accidental alteration of data during power ian ‘BUFFER Up/Down. However, due to the unpredictable nature of power up and power down sequences in some systems, itis important to apply and remove the programming voltage Vag only when Vss <— and Vo are within their specified limits. AO AT AD AD Ae “” For applications requiring extended temperature ranges the ERS4001, ERS4O0IR and ERS400HR are available, RELATED APPLICATION NOTES

1217 The ERS400: an easy to use 4K EAROM

1218 Interfacing the ER3400 to an eight bit microcomputer

1220 Generating EAROM programming voltages from a 5 volt supply

4210 Data retention testing of the E3400

0-03 Data input and output pins cE Chip Enable. Chip selected when CE is pulsed to logic "0". c0,C1 Mode Control Inputs co oct i) 1 Block Erase Mode: erase operation performed on all words. 1 1 Word Erase Mode: stored data is erased at addressed location. ° 0 Read Mode: addressed data read after leading edge of CE pulse. 1 0 Write Mode: input data written at addressed location. We Write Enable. Input data read when WE is pulsed to logic “0”. Vss ‘Substrate supply. Normally at +5 volts. Vor Ground Input Voo Power Supply Input. Normally at -12 volts. Veo Power Supply Input. Normally at -30 volts. 322

ER3400 @ ER34001/IR @ ER3400HR

ELECTRICAL CHARACTERISTICS

Maximum Ratings” All inputs and outputs except Vag (with respect to Vs)... -20V to +0.3V “Exceeding these ratings could cause permanent dam- ; implied—operating ranges are specified in Standard Standard Condition (unless otherwise noted) Conditions. Exposure to absolute maximum rating con- Vg = +5V to 5% ditions for extended periods may affect device reliability. Vop = ~12V 5% Data labeled “typical’ is presented for design guidance Voa = ~30V 45% only and is not guaranteed, Voi = GND Operating Temperature (T,) = 0°C to +70°C (ER3400) 40°C to +85°C (ER34001/1R) 55°C to +95°C (ER3400HR) [| erseoo | enssooivenssoonn Goncwine [om] mn [| oor | wm [9] wes [on] como DC CHARACTERISTICS Input Logic "1" Vow [Ves 1. ss +0.15|Vss —1.0 lVss+0.15} V Input Logic “0” vu { -10 08 10 os |v > Output Logic “1” Vou |Vss —1.5} — Wes 15] ~— |v | ton=2ma z= Output Logic “0” Vo | = 04 _ 05 | V | lo =2ma 4S Contro! Input Leakage ke | = -20 | — 2.0 | uA | Vow = Vss —15 Volts aS Data Input Leakage lo - 10.0 - 10.0 | uA | Vw = Vss —15 Volts a= Power Supply Current uy Veo Supply Current: Chip selected} too | — ~250 | — 30.0 | mA | Voo = Vss ~17 Volts ae Chip de-selected | Too | — -20 | — 15.0 | mA | Voo = Vss —17 Volts Ga Vos Supply Current: Write mode | Isc | — —40 | — 5.0 | mA | Voc = Ves ~35 Volts gs Vss Supply Current: Chip selected | Iss | — -310 | = -37.0 | mA | Voc = Ves —17V, Voc = Ves —35V fragt Chip de-selected | Iss | — —4s | — =18.0 | mA | Voo=Vss —17V, Voo = Vos ~35V MES AC CHARACTERISTICS Input capacitance—control inputs | Cc: | — 8 - 8 lot Input capacitance—data inputs | Co | — 10 - 10 | pf 323

ER3400 w ER34001/IR # ERS400HR READ MODE Vu ' ! y AOAG K__ STABLE CAN CHANGE rn (

1 H '

Vow 1 | co CAN CHANGE Vu 7 Vee 1 1 cor) CAN CHANGE Vi - y Pte tom! a = vm q \\ y, b n . bd Sa ti tol Vou VALID 00-03 HIGH Z HIGH Z Vou 4 4S | san aa | ERO4OOIR/HR | une | Er Charette [min warm | ar Conatone fapWWE Read Cycle Time tey 1700 - 1750 - ns EsPEM Address and Contro! to CE to, | 100 ] — | 10 | — ns Stal Address and Control Hold Time toe 250 = 350 — ns PEPE CE Rise to Data Tri-state tos | 50 | 300 | so | 350 | ns bape CE High tos 700 = 750 - ns REF Access Time th = | 900 | — | 1000 } ns | Load=2k + 100pf to Vss Em CE Pulse Width tee 1 50 1 so | us CE Rise, Fall Time tyaty 10 100 10 100 ns Number of Read Accesses per Location Between Refresh Ne | 1? | — wo | — - READ OPERATION ‘Address and control line inputs are latched on the falling edge of —_— data lines D0-D3. CE must be held high for a minimum of 700ns TE. With control lines CO and C1 both low a read cycle will be between memory read cycles. To reduce power consumption the initiated. After the access time t, the data read will be output on _—_-ER3400 may be operated with Vcg held at Vss in the read mode. 3.28

ER3400 = ERS4001/1R @ ERS400HR WORD ERASE ' 1 ' 1 { H Von j \\ i A0-A9 STABLE CANCHANGE | i Ve a

1 H i

' H i Vie t t i co ‘f \\__ CAN CHANGE CAN CHANGE Vu ' 1 i ' \\ ' i Vin q \\ cr (| CAN CHANGE CAN CHANGE v ton 1 tow 1 , Totou 1_tow y inaunat nae 1 ton peat toro be tos io rN f \\ /. \\ Van ' t i in H bo tee pte tet too yt Vo, ——$ > - ooDs ' HIGH Z t DATA OUT* | HIGH Z lo, $+ ' 1 1 1 * Data output during a Dummy Read is not valid. > us | sm fet ER34001R/HR un | Fefea Characteristics Conditions 52 | Min [wax [Min [ Max | 52 Address and Control to CE tor | 100 | — too | — ns oa Address and Control Hold Time tow } 250 = 250 - ns gS CE Rise to Data Tri-state tos 50 300 50 350 ns aS TE High (Dummy Read) tos | 1500 | — | 1500 | — | ns Ss CE Pulse Width ter 1 50 1 50 us Erase Time tt | 1 | 2 | 1 | 2 | ms WORD ERASE OPERATION An erase cycle is required prior toa write in order to precondition ing erase, therefore, the state of the address lines AO-A9 are the memory cells to be written. A word erase operation erases immaterial during the dummy read cycle. Data output during a ‘only the four bits of the addressed memory location. The falling dummy read cycle is not valid data. ‘edge of CE latches the control inputs and the address of the word to be erased. The rising edge of CE in the erase mode signals the BLOCK ERASE OPERATION start of the erase cycle which produces a positive shift in the Ablock erase oj oye re eration erases all 4096 bits of memory to the "1 threshold of the selected MNOS memory transistors. An erase State, in all other respects the operation is identical to the word operation must be terminated by a dummy read operation. The Siar.” a1 ames resbecte the oF dummy read need not occur on the same location as the preced- 3-25

ER3400 @ ER34001/IR # ER3400HR WRITE MODE 1 1 { 1 Von ey A0-AS x stas.e } CAN CHANGE v , 1 7 7 co CAN CHANGE CAN CHANGE Mie ! ' ‘ \\ ' ' 1 Vow ' ' ! 1 a CAN CHANGE \\ CAN CHANGE Vs y tone toe " ee ee a Yn \\ . y eNO \\ ft X Va i » i ' _——— ee es y Te Coal : Vn Ss WE oy rf | ' i ve Senet! we i, heen v, Lge tos bp et gt wey. | 1 1 0-03 CAN CHANGE 1 stad. DaTAIN K DATAIN KCAN CHANGE HIGHZX OMA, W High z = Vu b , Vo an == *Data output during a Dummy Read is not vati¢ Ss ER34001R/HR Ss Em = Address and Control to CE ton 100 - 100 - ns ‘Address and Control Hold Time tow | 250 | — | 350 | — ns | __ CE Fall to WE Fall Delay tow 0 = tC) - ns WE rise may overlap CE WE Rise to CE Rise Delay tow | ~s0 | — | -100 | — ns__| rise by 50ns maximum Data Stable to WE tows ° - t) - ns WE Rise to End of Data Stable tow | 100 | — ro | — ns CE Pulse Wiath te 1 50 1 so | us WE Pulse Width twe | soo | — 650 | — ns Write Time tw 1 2 1 2 ms CE Rise to Data Tristate ter | 50 | 300 | so | 350 | ns GE High (Oummy Read) tos | 1500 | — 1500 | — ns Unpowered Data Storage Time ts 10 - 1 — | YRS. | See Note 1 Number of Reprogramming Cycles Ny | 10% | — 1 | — — | See Note 1 Number of Read Accesses/Location between Refresh Neg | 10? | = we} — - NOTE 1: Does not imply end of useful lite. See “Write Operation” for further information. WRITE OPERATION Control lines CO and C1 along with address lines AO-A9 are occur on the same location as the previous write, therefore, latched on the falling edge of CE. Input data on DO-D3is latched ——_ address line A0-A9 may be allowed to change during the dummy on the rising edge of WE. WE may be tied to CE forall operations, read cycle however, this separate latching allows the ER3400 to be used in The specification of 10 years non-volatile data retention after a certain systems where address and data busses are multiplexed minimum of 10° reprogramming cyclesis merely one point on the The writing of the selected memory transistors is initiated by the curve of retention versus reprogramming cycles and does not rising edge of CE. CE must remain high for the duration of the imply e sudden cut-off or end of life. As the number of Erase/Write write time. A write operation can only be terminated byadummy cycles per address increases, a gradual, logarithmic reduction in read. To avoid bus contention, the data lines must be tri-stated data retention capability occurs with 1 year of retention being a prior to initiating the dummy read cycle. The data output by a typical figure after 10* cycles. dummy read cycle Is not valid data. The dummy read need not 326

TYPICAL CHARACTERISTIC CURVES on oh iT | Fig.3 TYPICAL access TIME vs. Fig.4 TYPICAL cyeue ‘TIME vs. POWER SUPPLY VOLTAGE POWER SUPPLY VOLTAGE ; ne — i Yopss-17¥ ss Fig.5 loo v8. Voo-Vss POWER SUPPLY VOLTAGE Fig.6 loo vs. OPERATING FREQUENCY a> IN READ MODE AND NOT SELECTED IN READ MODE AND SELECTED we z Fig.7 loo V8. Vco-Vss POWER SUPPLY VOLTAGE IN READ MODE AND NOT SELECTED oe