ER2055 ETC | Alldatasheet

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Technical content

INSTRUMENT ER2055 IR. ER2055 HR SSS

512 Bit Electrically Alterable Read Only Memory

FEATURES PIN CONFIGURATION

22 LEAD DUAL IN LINE top view

© 64 word x 8 bit organization on © G bit binary addressing a der 7 xbo © +5, -28V power supplies & G2 2p Dy ® Word Alterable on: a =i © 10 year data storage for ER2055 (at +70°C) ods weet @ 1 year data storage for ER2055 IR (at +85°C) vem de woes and ER2056 HR (at +125°C) dd? whe = TTL compatibie with pull-up resistors on inputs nde sbe @ Tri-state outputs ao 4B Vea -20 © Read Time: 2us (ER2055), 4us (ER2055 IR and ER2055 HA) adi 3B cx ® Write/Erase Time: 50ms (ER2055), 100ms (ER2055 HR) adn ba & No voltage switching required &@ 2 chip selects BLOCK DIAGRAM Fame ® Two extended temperature ranges: ee ao = —40°C to +85°C (Industrial) Part # ER20S5 IR 5 85°C to +125°C (Hi-Rel) Part # ER2055 HR

DESCRIPTION

The ER2055 is a fully decoded 64 x 8 electrically erasable and reprogrammable ROM. Write, erase, and read voltages are = 0° switched internally via a 2-bit code applied to C1 and C2, 1 vo Mewony Data is stored by applying negative writing pulses that selectively bo oar ae even tunnel charge into the oxide-nitride intertace of the gate insulator ppm Ri of the 512 MNOS memory transistors. When the writing voltage is os <> outrur removed the charge trapped at the interface Is manifested as a o negative shift in the threshold voltage of the selecte¢ memory transistors. eco0en OPERATION Anh Data is stored in a two transistor memory call. After the cell is Precongitioned by an erase signal (which causes a positive shift The ER2055 EAROM uses dynamic edge triggered circuits in the threshold of both transistors), datais written into one of the internally. This requires either a mode change, @ clock or @ transistors making its threshold more negative. A sensing flip transition of the chip selects between successive operations. flop is used to read the memory cell and presents a logic high or Thus successive operations in the same mode must be separated low to the output depending on which transistor is “written” by transition of one of these four lines. Clock pulses are not ‘The ER2055 EAROM may be operated with Ves between +5 and normally required during erase or write operations, but are needed for successive operations if the chip select is held high, +10 volts for either TTL or CMOS compatibility. The negative lies applications where ove EAROM te cons Power supply, Vaa. should be adjusted so that the difference 0 Aer a between Ves and Vea is always 33 volts. {In using the read clock to refresh the outputs during a read It is important to note two things: first, that an erase is required operation a animal frequency is eee mendedo insure that the before a write to precondition the cell, and second, that after an road Cycle liletime between writes (Nn) is kept to a maximum erase, both transistors will have the same threshold voltage and The ER20561R and ER205S HA are screened to Mil Std. 883B/me- valid data will not be present at he output, thod 5004.1/level B, pre-cap visual inspection, environmental testing, burn-in and external visual. They are available in 28 lead PN FUNCTIONS ceramic dual in line packages. Aehs 6-Bit Word Address Ded, Data input and output pins ost, CE Chip Selects Chip selected at logic “1” on CS1 and logic “0" on SZ. When chip is not selected, outputs are open circuit, read: write and erase are disabled. Power is reduced. 1.02 ‘Mode Control Inputs ot oe 0 1 Erase Mode: stored data is orased at addressed location. 1 0 Read Mode: addressed data read after clock pulse. Output data retained at output pins until next read operation © 0 Write Mode: input data written at addressed location. Clock not required. cuK Clock input, Pulse to logic "1" for read operation. Data will remain valid for 20 to 60 seconds: the outputs willthen become ‘open circuit until another clock pulse is received. Vas ‘Substrate supply. Normally at +5 volts. . Vou Ground input Vea Power Supply Input. Normally at -28 volts. “12

Eg ER2055 @ ER2055 IR # ER2055 HR TIMING DIAGRAM Ve ERASE WRITE READ DESELECT cs te tw t Va — Von co Va Vn Ve Vn cLock sal Va — s rm mel eue| Vow -— Va -— Vm cata a a Va wae _—— > — TYPICAL OUTPUT CHARACTERISTICS TYPICAL SUPPLY CURRENT VS POWER SUPPLY VOLTAGE a5 as np READ wasre ERASE veseLecteD a0 ° so ” oc Ler |e ; 2s 1 AB, as . ee wc y iz uw & . ree /| NS | 3 TY ZZ rc JE TTT TON, ° 8 a0 35 40 «sso Ee a vet Veetv) eet Vea) ou

ER2055 @ ER2055 IR # ER2055 HR ES

ELECTRICAL CHARACTERISTICS

. *Exceeding these ratings could cause Maximum Ratings’ Permanent damage. Functional operation of ‘Standard Conditions (for TTL Compatibility) Vos = +8V25% Voo = ~28V25% Vai GND Operating Temperature Ta = 0*C to +70°C for ER2055 Ta = 40°C to +85°C for ER2055 IR Ta = 55°C to +125°C for ER2055 HR Output Load = 100pF, 1 TTL load DC CHARACTERISTICS Input Logic “1” Vw |Vas-1.5| — |Vos +0.9 Vas -1.5| — |Vse +03) Vv . Input Logic “0” Va |Vae-15] — | 08 | Vss-10] — | 06 v Output Logic "1" Vow |Vss —1.5] — — | Vss -1.5] — - Vo | Ton = 100uA Output Logic “o” Vo | — | — | 06 -— |—| o6 V_ | Tou = 1.6mA for Ves = 5V Input Leakage nk} -— | 2] 10 — | 2] 10 | uA | Vw = Ves —15 Output Leakage wb] — | 2] 10 — | 2 | 10 | uA | Chip deselected Power Supply Current Read loo | — | 8 | 10 — | 8 | 13 | mA | tas approx. loa Write lo | — | 6] 7 -— |e] oe mA | Tee approx. loa Erase le} — | 4] 6 - |4]e mA | Iss approx. loa Deselected lo | — | 3 | 4 — |3].6 mA | las approx. Ioa AC CHARACTERISTICS Clock Pulse width tw | 20 | — | 200] 20 | — | 200 | us Erase Cycle Time te | 50 | — | 2000] 100 | — | 2000 | ms Write Cycle Time tw | 50 | — | 2000] 100 | — | 2000 | ms Read Cycle Time ta | 50 | —| 240} 60 | — | 250 | us Data Set Up Time tos | 50 | — | — so |—| —- ns Data Hold Time tw | 50 [ — | — so |-—] — ns Number of Reads/Word Refresh | Nea | 10"! | — | — wry - | = Number of Erase/Write Cycles | Nw | 10° - - 10° - - - Input Capacitance, all pins Co} — | 6] 10 - |6| pF Unpowered Data Storage Time | ts | 10 | — | — 1 | — | — | Years | at max. temperature Power Dissipation Read Cycle | Po | — | 450] 500 | — | 450] 500 | mW | at 25°C Vas = +8, Voo = —29 Po | not applicable — | =] 500 | mw | at 125°C Vas = +5, Voo = -28 Po | — not applicable — | =] 600 | mw | at-55°C vss = +5, Voo = —20 Pulse Rise, fall time trte] to | — | 100 | 10 | - | 100 | ns **Typical values are at +-25°C and nominal voltages.