EPA1130_15 PCA | Alldatasheet

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Technical content

*These two values are inter-dependent. Recommended Operating Conditions Min Max Unit VCC DC Supply Voltage 4.5 5.5 Volt VI DC Input Voltage Range 0 V CC Volt VO DC Output Voltage Range 0 V CC Volt PW* Pulse Width % of Total Delay 40 % D* Duty Cycle 40 % TA Operating Free Air Temperature 0 70 °C IO DC Output Source/Sink Current 25 mA Schematic Input Pulse Test Conditions @ 25°C Unit EIN Pulse Input Voltage 3.2 Volts PW Pulse Width % of Total Delay 150 % TRI Input Rise Time (0.75 - 2.4 Volts) 2.0 nS PRR Pulse Repetition Rate @ PW £ 500nS 1.0 MHz Pulse Repetition Rate @ PW > 500nS 100 KHz VCC Supply Voltage 5.0 Volts Test Conditions Min Max Unit VIH High Level Input Voltage VCC = 4.5 to 5.5 2.0 Volt VIL Low Level Input Voltage VCC = 4.5 to 5.5 0.8 Volt VOH High Level Output Voltage VCC = 4.5V,IO =-4.0mA 4.0 Volt @VIH or VIL VOL Low Level Output Voltage VCC = 4.5V,IO = 4.0mA 0.3 Volt @VIHor VIL IL Input Leakage Current V CC = 5.5V @VIH or VIL ±1.0 uA ICC Supply Current V CC = 5.5V, VIN=0 15 mA TRO Output Rise Time (.75 - 2.4 Volts) 4 nS Parameter NH High Fanout LSTTL Load VCC = 5.5V, VOH = 4.0V 10

8 Pin 5 Tap High Speed CMOS (HCT)

Compatible Active Delay Lines 12* 17 22 27 32 EPA1130-32 EPA1130G-32 12* 18 24 30 36 EPA1130-36 EPA1130G-36 12* 19 26 33 40 EPA1130-40 EPA1130G-40 12* 20 28 36 44 EPA1130-44 EPA1130G-44 12* 21 30 39 48 EPA1130-48 EPA1130G-48 12* 22 32 42 52 EPA1130-52 EPA1130G-52 12* 24 36 48 60 EPA1130-60 EPA1130G-60 15 30 45 60 75 EPA1130-75 EPA1130G-75 Delays are ±5% or ±2 nS†DIP Part SMD Part Tap Total Number Number Delays are ±5% or ±2 nS†DIP Part SMD Part Tap TotalNumber Number 20 40 60 80 100 EPA1130-100 EPA1130G-100 25 50 75 100 125 EPA1130-125 EPA1130G-125 30 60 90 120 150 EPA1130-150 EPA1130G-150 35 70 105 140 175 EPA1130-175 EPA1130G-175 40 80 120 160 200 EPA1130-200 EPA1130G-200 50 100 150 200 250 EPA1130-250 EPA1130G-250 60 120 180 240 300 EPA1130-300 EPA1130G-300 70 140 210 280 350 EPA1130-350 EPA1130G-350 †Whichever is greater. Delay times referenced from input to leading edges at 25°C, 5.0V. * Inherent Delay DSA1130/G Rev. B 3/27/01 QAF-CSO1a Rev. B 8/25/94 Unless Otherwise Noted Dimensions in Inches Tolerances: Fractional = ± 1/32 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 TEL: (818) 892-0761 FAX: (818) 894-5791 E L E C T R O N I C S I N C . 29 EPA1130-500 EPA1130-500500400300200 100 72635 OUTPUT GROUND INPUT

8 VCC

.365 Max. .500 Max. .280 Max. PCA EPA1130-32 D.C. .010 Typ. .120 Min, .020 Typ..250 Max. .020 Typ. White Dot Pin#1 .100 .100 PCA EPA1130G-32 D.C. .280 Max. .500 Max. .250 Max. .01 Typ. .400 Max. .02 .050 .300 .100 .055 .410 .03 Pad Layout