EP610JC-25

EP610 ROCHESTER | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

Features

Figure 1. EP610 Package Pin-Out Diagrams Package outlines not drawn to scale. Windows in ceramic packages only.

Specification Number EP610-CI (AT) REV - Page 2 of 9 Rochester Part Number Altera Part Number Package Temperature EP610DC-25 EP610DC-25 CDIP-24 0° to +70°C EP610DC-30 EP610DC-30 CDIP-24 0° to +70°C EP610DC-35 EP610DC-35 CDIP-24 0° to +70°C EP610DI-30 EP610DI-30 CDIP-24 -40° to +85°C EP610DI-35 EP610DI-35 CDIP-24 -40° to +85°C EP610DM-35 EP610DM-35 CDIP-24 -55° to +125°C EP610DM/B EP610DM883B CDIP-24 -55° to +125°C EP610JC-25 EP610JC-25 LDCC-28, Ceramic 0° to +70°C EP610JC-30 EP610JC-30 LDCC-28, Ceramic 0° to +70°C EP610JC-35 EP610JC-35 LDCC-28, Ceramic 0° to +70°C EP610JI-30 EP610JI-30 LDCC-28, Ceramic -40° to +85°C EP610JI-35 EP610JI-35 LDCC-28, Ceramic -40° to +85°C EP610JM-35 EP610JM-35 LDCC-28, Ceramic -55° to +125°C EP610JM-40 EP610JM-40 LDCC-28, Ceramic -55° to +125°C EP610LC-15 EP610LC-15 LDCC-28, Plastic 0° to +70°C EP610LC-20 EP610LC-20 LDCC-28, Plastic 0° to +70°C EP610LC-25 EP610LC-25 LDCC-28, Plastic 0° to +70°C EP610LC-30 EP610LC-30 LDCC-28, Plastic 0° to +70°C EP610LI-20 EP610LI-20 LDCC-28, Plastic -40° to +85°C EP610LI-30 EP610LI-30 LDCC-28, Plastic -40° to +85°C EP610LI-35 EP610LI-35 LDCC-28, Plastic -40° to +85°C EP610PC-15 EP610PC-15 PDIP-24 0° to +70°C EP610PC-20 EP610PC-20 PDIP-24 0° to +70°C EP610PC-25 EP610PC-25 PDIP-24 0° to +70°C EP610PC-30 EP610PC-30 PDIP-24 0° to +70°C EP610PC-35 EP610PC-35 PDIP-24 0° to +70°C EP610PI-30 EP610PI-30 PDIP-24 -40° to +85°C EP610PI-35 EP610PI-35 PDIP-24 -40° to +85°C EP610SC-15 EP610SC-15 SOP-24, Plastic 0° to +70°C EP610SC-20 EP610SC-20 SOP-24, Plastic 0° to +70°C EP610SC-25 EP610SC-25 SOP-24, Plastic 0° to +70°C EP610SC-30 EP610SC-30 SOP-24, Plastic 0° to +70°C Rochester Ordering Guide *Most products can also be offered as RoHS compliant, designated by a –G suffix. Please contact factory for more information.

Specification Number EP610-CI (AT) REV - Page 3 of 9 Table 1 summarizes EP610 device features Table 1. EP610 Device Features

Description

Figure 2. EP610 Block Diagram Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages. registers in macrocells 1 through 8.

Specification Number EP610-CI (AT) REV - Page 4 of 9 Absolute Maximum Ratings Recommended Operating Conditions EP610 EP610T EP610-XX/B EP610I Symbol Parameter Conditions Min Max Min Max Unit VCC Supply voltage With respect to GND VI DC input voltage -2.0 7.0 -0.5 VCC+ 0.5 V IMAX DC VCC or GND current -175 175 mA IOUT DC output current, per pin -25 25 mA PD Power dissipation 1000 mW TSTG Storage temperature No bias -65 150 -65 150 °C TAMB Ambient temperature Under bias -65 135 (125) -10 85 °C TJ Junction temperature Under bias (150) °C EP610 EP610T EP610-XX/B EP610I Symbol Parameter Conditions Min Max Min Max Unit VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V TA Operating Temperature For commerical use 0 70 0 70 °C TA Operating Temperature For industrial use -40 85 -40 85 °C TC Case Temperature For military use -55 125 °C tR Input rise time 100 (50) 500 ns tF Input fall time 100 (50) 500 ns Recommended Operating Conditions Symbol Parameter Conditions Min Typ Max Unit VIH High-level input voltage 2.0 VCC + 0.3 V VIL Low-level input voltage -0.3 0.8 V VOH High-level TTL output voltage IOH = -4 mA DC 2.4 V VOH High-level CMOS output voltage IOH = -2 mA DC 3.84 V VOL Low-level output voltage IOL = 4 mA DC 0.45 V II Input leakage output VI = VCC or GND -10 10 µA IOZ Tri-state output leakage current VO = VCC or GND -10 10 µA

Specification Number EP610-CI (AT) REV - Page 5 of 9 Capacitance EP610 EP610T EP610-XX/B EP610I Symbol Parameter Conditions Min Max Min Max Min Max Unit CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 10 20 8 pF CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 12 20 8 pF CCLK1 CLK1 pin capacitance VIN = 0 V, f = 1.0 MHz 20 20 10 pF CCLK2 CLK2 pin capacitance VIN = 0 V, f = 1.0 MHz 20 20 12 pF ICC Supply Current: EP610 & EP610T ICC Supply Current: EP610-XX/B & EP610I EP610 EP610T Symbol Parameter Conditions Speed Grade Min Typ Max Min Typ Max Unit ICC1 VCC supply current (non-turbo, standby) VI = VCC or GND, No load 20 150 µA ICC2 VCC supply current (non-turbo, active) VI = VCC or GND, No load, f = 1.0 MHz 5 10 (15) mA ICC3 VCC supply current (turbo, active) -15, -20 60 90 (115) 60 90 mA -25, -30, -35 45 60 (75) 60 90 mA EP610-XX/B EP610I Symbol Parameter Conditions Min Typ Max Min Typ Max Unit ICC1 VCC supply current (non-turbo, standby) VI = VCC or GND, No load 900 20 150 µA ICC2 VCC supply current (non-turbo, active) VI = VCC or GND, No load, f = 1.0 MHz 25 3 8 mA ICC3 VCC supply current (turbo, active) VI = VCC or GND, No load, f = 1.0 MHz 140 65 105 mA

Specification Number EP610-CI (AT) REV - Page 6 of 9 AC Operating Conditions: EP610-15 & EP610-20 EP610-15 EP610-15T EP610-20 EP610-20T Non-Turbo Adder Symbol Parameter Conditions Min Max Min Max Unit tPD1 Input to non-registered output C1 = 35 pF 15 20 20 ns tPD2 I/O input to non-registered output C1 = 35 pF 17 22 20 ns tPZX Input to output enable C1 = 35 pF 15 20 20 ns tPXZ Input to output disable C1 = 5 pF 15 20 20 ns tCLR Asynchronous output clear time C1 = 35 pF 15 20 20 ns tIO I/O input pad and buffer delay 2 2 0 ns fMAX Maximum clock frequency 83.3 62.5 0 MHz tSU Global clock input setup time 9 11 20 ns tH Global clock input hold time 0 0 0 ns tCH Global clock high time 6 8 0 ns tCL Global clock low time 6 8 0 ns tCO1 Global clock to output delay 11 13 0 ns tCNT Global clock minimum period 12 16 0 ns fCNT Global clock internal maximum frequency 83.3 62.5 0 MHz tASU Array clock input setup time 6 8 20 ns tAH Array clock input hold time 6 8 0 ns tACH Array clock high time 7 9 0 ns tACL Array clock low time 7 9 0 ns tACO1 Array clock to output delay 15 20 20 ns tACNT Array clock minimum period 14 18 0 ns fACNT Array clock internal maximum frequency 71.4 55.6 0 MHz

Specification Number EP610-CI (AT) REV - Page 7 of 9 AC Operating Conditions: EP610-15 & EP610-20 Note (1) EP610-25 EP610-25T EP610-20 EP610-20T EP610-35 Non- Turbo Adder Symbol Parameter Conditions Min Max Min Max Min Max Unit tPD1 Input to non-registered output C1 = 35 pF 25 30 35 30 ns tPD2 I/O input to non-registered output 27 32 37 30 ns tPZX Input to output enable 25 30 35 30 ns tPXZ Input to output disable C1 = 5 pF Note (2) 25 30 35 30 ns tCLR Asynchronous output clear time C1 = 35 pF 27 32 37 30 ns tIO I/O input pad and buffer delay 2 2 2 0 ns fMAX Maximum clock frequency Note (3) 47.6 41.7 37.0 0 MHz tSU Global clock input setup time 21 24 27 30 ns tH Global clock input hold time 0 0 0 0 ns tCH Global clock high time 10 11 12 0 ns tCL Global clock low time 10 11 12 0 ns tCO1 Global clock to output delay 15 17 20 0 ns tCNT Global clock minimum period 25 30 35 0 ns fCNT Global clock internal maximum frequency Note (4) 40.0 33.3 28.6 0 MHz tASU Array clock input setup time 8 8 8 30 ns tAH Array clock input hold time 12 12 12 0 ns tACH Array clock high time 10 11 12 0 ns tACL Array clock low time 10 11 12 0 ns tACO1 Array clock to output delay 27 32 37 30 ns tACNT Array clock minimum period 25 30 35 0 ns fACNT Array clock internal maximum frequency Note (4) 40.0 33.3 28.6 0 MHz Notes to tables: (1) Operating conditions: VCC = 5 V ± 5%, TA = 0° C to 70° C for commercial use. VCC = 5 V ± 10%, TA = -40° C to 85° C for industrial use. VCC = 5 V ± 10%, TC = -55° C to 125° C for military use. (2) Sample-tested only for an output change of 500 mV. (3) The fMAX values represent the highest frequency for pipelined data. (4) Measured with a device programmed as a 16-bit counter. ICC measured at 0° C.

Specification Number EP610-CI (AT) REV - Page 8 of 9 AC Operating Conditions: EP610-XX/B Note (1) Symbol Parameter Conditions Min Max Unit tPD1 Input to non-registered output C1 = 35 pF Notes (2), (3) 35 ns tPD2 I/O input to non-registered output 37 ns tPZX Input to output enable 35 ns tPXZ Input to output disable C1 = 5 pF Notes (2), (3), (4), (5) 35 ns tCLR Asynchronous output clear time C1 = 35 pF Notes (2), (3) 37 ns fMAX Maximum clock frequency Note (2), (6), (7) 37.0 MHz tSU Global clock input setup time Note (2), (3) 27 ns tH Global clock input hold time Note (3) 0 ns tCH Global clock high time Note (4) 12 ns tCL Global clock low time Note (4) 12 ns tCO1 Global clock to output delay 20 ns tCNT Global clock minimum period Note (4), (8) 35 ns fCNT Global clock internal maximum frequency Note (8) 28.5 MHz tASU Array clock input setup time Notes (2), (3), (4) 8 ns tAH Array clock input hold time Notes (2), (3), (4) 12 ns tACH Array clock high time Notes (3), (4) 12 ns tACL Array clock low time Notes (3), (4) 12 ns tACO1 Array clock to output delay Notes (2), (3) 37 ns tACNT Array clock minimum period Notes (4), (8) 35 ns fACNT Array clock internal maximum frequency Notes (4), (8) 28.6 MHz Notes to tables: (1) Screening and characterization of AC delay parameters are conducted at 10 MHz or less. Operating conditions: VCC = 5 V ± 10%, TC = -55° C to 125° C for military use. (2) All array-dependent delays are specified for an XOR pattern. This pattern includes two product terms and two pure inputs; all other product terms in the macrocell are held low by one EPROM cell. Other patterns may result in longer delays. Delays for patterns involving only one product term (such as tPXZ ) are specified for an XOR pattern in which only one pure input switches at a time. (3) When the Turbo Bit is not set (non-turbo mode), a non-turbo adder of 30 ns (maximum) is added to this parameter to determine worst-case timing. Parameters may not be tested in non-turbo mode, but are guaranteed to the limits specified. Devices operating in non-turbo mode require one input or I/O transition to guarantee that the device will enter the correct power-up state. (4) These parameters may not be tested, but are guaranteed to the limits specified in the table under “Absolute Maximum Ratings” on page 3. (5) Not tested directly, but guaranteed by testing tPD. (6) The fMAX values represent the highest frequency for pipelined data. (7) Not tested directly, but derived from tSU. (8) Specified with device programmed as a 16-bit counter with no output loading.

Specification Number EP610-CI (AT) REV - Page 9 of 9 AC Operating Conditions: EP610I Note (1) EP610I-10 EP610I-15 EP610I-25 Non-Turbo Adder Symbol Parameter Min Max Min Max Min Max Unit tPD1 Input to non-registered output, Note (2) 10 15 25 25 ns tPD2 I/O input to non-registered output, Note (2) 10 15 25 25 ns tPZX Input to output enable 15 18 25 25 ns tPXZ Input to output disable, Note (3) 13 18 25 25 ns tCLR Asynchronous output clear time 13 18 25 25 ns fMAX Maximum clock frequency 111 83.3 66 0 MHz tSU Global clock input setup time 7 12 15 25 ns tH Global clock input hold time 0 0 0 0 ns tCH Global clock high time 5 6 7.5 0 ns tCL Global clock low time 5 6 7.5 0 ns tCO1 Global clock to output delay 6.5 8 10 0 ns tCNT Global clock minimum period 10 15 25 25 ns fCNT Global clock internal maximum frequency, Note (4) 100 66 40 0 MHz tASU Array clock input setup time 2 4 5 25 ns tAH Array clock input hold time 3 6 8 0 ns tACH Array clock high time 5 7.5 10 0 ns tACL Array clock low time 5 7.5 10 0 ns tACO1 Array clock to output delay 12 16 25 25 ns tACNT Array clock minimum period, Note (4) 10 15 25 25 ns fACNT Array clock internal maximum frequency, Note (4) 100 66 40 0 MHz Notes to tables: (1) Operating conditions: VCC = 5 V ± 5%, TA = 0° C to 70° C for commercial use. VCC = 5 V ± 10%, TA = -40° C to 85° C for industrial use. (2) Measured with eight outputs switching. (3) Sample-tested only for an output change of 500 mV. (4) Measured with a device programmed as a 16-bit counter. Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves the right to make changes without further notice to any specification herein.