EP5362Q

EP5352Q ENPIRION | Alldatasheet

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03132 4/28/2009 Rev:B *Optimized PCB layout Gerber files downloadable from the Enpirion website to assure first pass design success. EP5352Q/EP5362Q/EP5382Q 500/600/800mA Synchronous Buck Regulators With Integrated Inductor RoHS Compliant Voltage Select DAC Switch VREF (+) (-) Error Amp VSENSE VFB VOUT VS0 VS1 VS2 Package Boundry P-Drive N-Drive UVLO Thermal Limit Current Limit Soft Start Sawtooth Generator (+) (-) PWM Comp VIN ENABLE GND Logic Compensation Network Product Highlights

• Revolutionary integrated inductor
• Very small solution foot print*
• Fully RoHS compliant; MSL 3 260°C reflow
• Only two low cost components required
• 5mm x 4mm x1.1mm QFN package
• Wide 2.4V to 5.5V input range
• 500, 600, 800 mA output current versions
• Less than 1 μA standby current
• 4 MHz switching frequency
• Fast transient response
• Very low ripple voltage; 5mVp-p typical
• 3 Pin VID Output Voltage select
• External divider option
• Dynamically adjustable output
• Designed for Low noise/EMI
• Short circuit, UVLO, and thermal protection Product Overview The Ultra-Low-Profile EP53X2Q product family is targeted to applications where board area and profile are critical. EP53X2Q is a complete power conversion solution requiring only two low cost ceramic MLCC caps. Inductor, MOSFETS, PWM, and compensation are integrated into a tiny 5mm x 4mm x 1.1 mm QFN package. The EP53x2Q family is engineered to simplify design and to minimize layout constraints. High switching frequency and internal type III compensation provides superior transient response. With a 1.1 mm profile, the EP53x2 is perfect for space and height limited applications. A 3-pin VID output voltage select scheme provides seven pre-programmed output voltages along with an option for external resistor divider. Output voltage can be programmed on-the-fly to provide fast, dynamic voltage scaling. Typical Application Circuit VIN VSense Vin VS1 VS2 VS0 10μF2.2uF VOUT Vout GND ENABLE VFB Voltage Select

Figure 1. Typical application circuit.

Applications

• Area constrained applications
• Mobile multimedia, smartphone & PDA
• Mobile and Cellular platforms
• VoIP and Video phones
• Personal Media Players
• FPGA, DSP, IO & Peripherals

03132 4/28/2009 Rev:B EP5382Q/EP5362Q/EP5352Q ©Enpirion 2009 all rights reserved, E&OE 2 www.enpirion.com Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute ma ximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN MAX UNITS Input Supply Voltage VIN -0.3 7.0 V Voltages on: ENABLE, VSENSE, VS0-VS2 -0.3 V IN + 0.3 V Voltage on: VFB -0.3 2.7 V Storage Temperature Range TSTG -65 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C ESD Rating (based on Human Body Model) 2000 V Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS Input Voltage Range VIN 2.4 5.5 V Output Voltage Range VOUT 0.6 V IN-0.45 V Operating Ambient Temperature TA -40 +85 °C Operating Junction Temperature TJ -40 +125 °C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient (0 LFM) θJA 65 °C/W Thermal Resistance: Junction to Case (0 LFM) θJC 15 °C/W Thermal Shutdown TJ-TP +150 °C Thermal Shutdown Hysteresis 15 °C

Electrical Characteristics

NOTE: TA = 25°C unless otherwise noted. Typical values are at VIN = 3.6V. EP5352QI, EP5362QI: CIN = 2.2μF, COUT=10uF. EP5382QI: CIN = 4.7μF, COUT=10uF. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Operating Input Voltage V IN 2.4 5.5 V Under Voltage Lockout V UVLO VIN going low to high 2.2 2.3 V UVLO Hysteresis 0.145 V VOUT Initial Accuracy VOUT 2.4V ≤ VIN ≤ 5.5V, ILOAD = 100mA; VOUT Variation for all Causes VOUT 2.4V ≤ VIN ≤ 5.5V, ILOAD = 0 - 1A, Feedback Pin Voltage V FB 2.4V ≤ VIN ≤ 5.5V, ILOAD = 100mA VSO=VS1=VS2=1 0.591 0.603 0.615 V Feedback Pin Input Current I FB 1 nA Feedback Pin Voltage V FB 2.4V ≤ VIN ≤ 5.5V, ILOAD = 0-800mA, TA = -40°C to +85°C VSO=VS1=VS2=1 0.585 0.603 0.621 V Dynamic Voltage Slew Rate Vslew 3 mV/μS

03132 4/28/2009 Rev:B EP5382Q/EP5362Q/EP5352Q ©Enpirion 2009 all rights reserved, E&OE 3 www.enpirion.com PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Continuous Output Current EP5352QI IOUT EP5352Q 500 mA Continuous Output Current EP5362QI I OUT EP5362Q 600 mA Continuous Output Current EP5382QI IOUT EP5382Q 800 mA Shut-Down Current ISD Enable = Low 0.75 μA Quiescent Current No switching 800 μA PFET OCP Threshold I LIM 2.4V ≤ VIN ≤ 5.5V, 0.6V ≤ VOUT ≤ VIN – 0.6V 1.4 2 A VS0-VS1 Voltage Threshold Pin = Low Pin = High 0.0 1.4 0.4 V IN V VS0-VS2 Pin Input Current I VSX 1 nA Enable Voltage Threshold Logic Low Logic High 0.0 1.4 0.2 V IN V Enable Pin Input Current I EN V IN = 3.6V 2 μA Operating Frequency F OSC 4 MHz PFET On Resistance R DS(ON) 340 mΩ NFET On Resistance R DS(ON) 270 mΩ Internal Inductor DCR .110 Ω Soft-Start Operation Time to 90% Vout Tss Vout = 3.3V 1 mS

Figure 4. Functional block diagram.

03132 4/28/2009 Rev:B EP5382Q/EP5362Q/EP5352Q ©Enpirion 2009 all rights reserved, E&OE 6 www.enpirion.com Typical Performance Characteristics 50 150 250 350 450 550 Efficiency vs Output Current VOUT = 3.3V Load Current (mA) VIN = 5.0V VOUT = 3.0V VOUT = 2.7V VOUT = 2.5V VOUT = 1.8V Efficiency -% 50 150 250 350 450 550 Efficiency vs Output Current VOUT = 3.3V Load Current (mA) VIN = 5.0V VOUT = 3.0V VOUT = 2.7V VOUT = 2.5V VOUT = 1.8V Efficiency -% 100 50 150 250 350 450 550 Efficiency vs Output Current VOUT = 1.2V Load Current (mA) VIN = 3.3V VOUT = 3.0V VOUT = 2.7V VOUT = 2.5V VOUT = 1.8V Efficiency -% 100 50 150 250 350 450 550 Efficiency vs Output Current VOUT = 1.2V Load Current (mA) VIN = 3.3V VOUT = 3.0V VOUT = 2.7V VOUT = 2.5V VOUT = 1.8V Efficiency -% Transient Response Vout 50mV/Div ILoad 500mA/Div VIN = 5.0V VOUT = 3.3V Iload = 100mA to 800mA 20μs/Div Transient Response Vout 50mV/Div ILoad 500mA/Div VIN = 5.0V VOUT = 3.3V Iload = 100mA to 800mA 20μs/Div Transient Response Vout 50mV/Div ILoad 500mA/Div VIN = 3.3V VOUT = 1.8V Iload = 100mA to 800mA 20μs/Div Transient Response Vout 50mV/Div ILoad 500mA/Div VIN = 3.3V VOUT = 1.8V Iload = 100mA to 800mA 20μs/Div 100 50 150 250 350 450 550 Efficiency vs Output Current VOUT = 3.3V Load Current (mA) VIN = 3.6V VOUT = 3.0V VOUT = 2.7V VOUT = 2.5V VOUT = 1.8V Efficiency -% 100 50 150 250 350 450 550 Efficiency vs Output Current VOUT = 3.3V Load Current (mA) VIN = 3.6V VOUT = 3.0V VOUT = 2.7V VOUT = 2.5V VOUT = 1.8V Efficiency -% Start up Waveform Vout 1V/Div Enable 2V/Div VIN = 5.0V VOUT = 3.3V 200μs/Div Start up Waveform Vout 1V/Div Enable 2V/Div VIN = 5.0V VOUT = 3.3V 200μs/Div Output Ripple Vout 10mV/Div VIN = 3.6V VOUT = 3.3V Output Cap = 2 x 10 μF 0805 200ns/Div Output Ripple Vout 10mV/Div VIN = 3.6V VOUT = 3.3V Output Cap = 2 x 10 μF 0805 200ns/Div Output Ripple Vout 10mV/Div VIN = 3.6V VOUT = 3.3V Output Cap = 10 μF 0805 200ns/Div Output Ripple Vout 10mV/Div VIN = 3.6V VOUT = 3.3V Output Cap = 10 μF 0805 200ns/Div

03132 4/28/2009 Rev:B EP5382Q/EP5362Q/EP5352Q ©Enpirion 2009 all rights reserved, E&OE 7 www.enpirion.com Detailed Description Functional Overview The EP53x2Q family is a complete DCDC converter solution requiri ng only two low cost MLCC capacitors. MOSFET switches, PWM controller, Gate-drive, compensation, and inductor are integrated into the tiny 5mm x 4mm x 1.1mm package to provide the smallest footprint possible wh ile maintaining high efficiency and high performance. The converter uses voltage mode control to provide the simplest implementation and high noise immunity. The device operates at a 4 MHz switching frequency. The high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. The 4 MHz switching frequency enables the use of very small components making possible this unprecedented level of integration. Enpirion’s proprietary power MOSFET technology provides very low switching loss at frequencies of 4 MHz and higher, allowing for the use of very small internal components, and very wide control loop bandwidth. Unique magnetic design allows fo r integration of the inductor into the very low profile 1.1mm package. Integration of the inductor virtually eliminates the design/ layout issues normally associated with switch-mode DCDC converters. All of this enables much easier and faster integration in to various applications to meet demanding EMI requirements. Output voltage is chosen from seven preset values via a three pi n VID voltage select scheme. An external divider option enables the selection of any vo ltage in the 0.6 to V IN - Vdropout. This reduces the number of components that must be qualified and reduces inventory problems. The VID pins can be toggled on the fly to implement glitch free dynamic voltage scaling. Protection features in clude under-voltage lock- out (UVLO), over-current protection (OCP), short circuit protection, and thermal overload protection. Integrated Inductor Enpirion has introduc ed the world’s first product family featuring integrated inductors. The EP53x2Q family utilizes a low loss, planar construction inductor. The use of an internal inductor localizes the noises associated with the output loop currents. The inherent shielding and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board. Further, the package layo ut is optimized to reduce the electrical path length for the AC ripple currents that are a major source of radiated emissions from DCDC converters. The integrated inductor significantly reduces parasitic effects that can harm loop stability, and makes layout very simple. Soft Start Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the “ENABLE” pin is asserted “high”. Digital control circuitry limits the V OUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The soft start ramp rate is nominally 3.3mV/μSec. Over Current/Short Circuit Protection The current limit function is achieved by sensing the current flowing through a sense P- MOSFET which is compared to a reference current. When this level is exceeded the P- FET is turned off and the N-FET is turned on, pulling V OUT low. This condition is maintained for a period of 1mS and then a normal soft start is initiated. If the ov er current condition still persists, this cycle will repeat in a “hiccup” mode.

03132 4/28/2009 Rev:B EP5382Q/EP5362Q/EP5352Q ©Enpirion 2009 all rights reserved, E&OE 8 www.enpirion.com Under Voltage Lockout During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the in put voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. Enable The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low wil l disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. In shutdown mode, the devic e quiescent current will be less than 1 uA. The ENABLE pin must not be left floating. Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature t he thermal shutdown circuit turns off the co nverter output voltage thus allowing the device to cool. When the junction temperature decreases by 15C °, the device will go through the normal startup process.

Application Information

To provide the highest degree of flexibility in choosing output voltage, the EP53x2Q family uses a 3 pin VID, or Voltage ID, output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage di vider. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. Table 1 shows the vari ous VS0-VS2 pin logic states and the associated output voltage levels. A logic “1” indicates a connection to V IN or to a “high” logic voltage level. A logic “0” indicates a connection to ground or to a “low” logic voltage level. These pins can be either hardwired to V IN or GND or alternatively can be driven by standard logic levels. Logic low is defined as V LOW ≤ 0.4V. Logic high is defined as VHIGH ≥ 1.4V. Any level between these two values is indeterminate. These pins must not be left floating. VS2 VS1 VS0 V OUT 0 0 0 3.3 0 0 1 2.5 0 1 0 2.8 0 1 1 1.2 1 0 0 3.0 1 0 1 1.8 1 1 0 2.7 1 1 1 External External Voltage Divider As described above, the external voltage divider option is chosen by connecting the VS0, VS1, and VS2 pins to V IN or logic “high”. The EP53x2Q uses a separate feedback pin, V FB, when using the external divider. VSENSE must be connected to V OUT as indicated in Figure 5. Table 1. Voltage select settings.

Figure 5. External Divider. start slew rate of 3.3mV/uS. settings and the external divider is not allowed. input and output filter applications. input and output filter applications.

03132 4/28/2009 Rev:B EP5382Q/EP5362Q/EP5352Q ©Enpirion 2009 all rights reserved, E&OE 10 www.enpirion.com LAYOUT CONSIDERATIONS* *Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success Recommendation 1: Input and output filter capacitors should be pl aced as close to the EP53x2QI package as possible to reduce EMI from input and output loop AC currents. This reduces the physical area of the Input and Output AC current loops. Recommendation 2: DO NOT connect GND pins 3 and 4 toge ther. Pin 3 should be used for the Input capacitor local ground and pi n 4 should be used for the output capacitor ground. The ground pad for the input and output filt er capacitors should be isolated ground islands and should be connected to system ground as indicated in recommendation 3 and recommendation 5. Recommendation 3: Multiple small vias (0.25mm after c opper plating) should be used to connect ground terminals of the Input capacit or and the output capacitor to the system ground plane. This provides a low inductance path for the high-frequen cy AC currents, thereby reducing ripple and suppressing EMI (see Fig. 5, Fig. 6, and Fig. 7). Recommendation 4: The large thermal pad underneath the co mponent must be connected to the system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for heat dissipation from the converter. Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer (PCB layer 2). This ground plane should be continuous and un-interrupted below the converter and the input and output capacitors that carry large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an uninterrupted ground “island” should be created on PCB laye r 2 immediately underneath the EN5312QI and its input and output capac itors. The vias that connect the input and output capacitor grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as well. Recommendation 6: As with any switch-mode DC/DC converte r, do not run sensitive signal or control lines underneath the converter package. Figure 6 shows an example schematic for the EP53x2Q using the internal voltage select. In this example, the device is set to a V OUT of 1.2V (VS2=0, VS1=1, VS0=1).

Figure 8. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter capacitor local grounds, and thermal pad, to PCB system ground. are attached. This results in several small pads being exposed on the bottom of the package. metal (traces, vias, or planes), on the top layer of the PCB. adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10.

Figure 11. Recommended PCB Solder Mask Openings.

Figure 12. Package mechanical dimensions.

03132 4/28/2009 Rev:B EP5382Q/EP5362Q/EP5352Q ©Enpirion 2009 all rights reserved, E&OE 16 www.enpirion.com Contact Information Enpirion, Inc.

685 US Route 202/206 Suite 305

Bridgewater, NJ 08807 Phone: 908-575-7550 Fax: 908-575-0775 Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information fur nished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsi bility for its use or for infringement of patents or other th ird party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life su pport systems or equipment used in hazardous environment without the express written authority from Enpirion.