Power Management

EP5357HUI

Enpirion, Inc.

600mA Synchronous Buck Regulator with Integrated Inductor

Manufacturer: Enpirion, Inc.

Document: 17 Pages / 291Kb

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EP5357LUI ENPIRION | Alldatasheet

Document overview

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PDF pages: 17

Technical content

Features

Integrated Inductor Technology
2.5mm x 2.25mm x 1.1mm package
Total Solution Footprint 10mm
Low V OUT ripple for RF compatibility
High efficiency, up to 93%
600mA continuous output current
55µA quiescent current
Less than 1µA standby current
5 MHz switching frequency
3 pin VID for glitch free voltage scaling
V OUT Range 0.6V to VIN – 0.25V
Short circuit and over current protection
UVLO and thermal protection
IC level reliability in a PowerSOC solution Application
Wireless and RF applications
Wireless broad band data cards
Smart phone and portable media players
Advanced Low Power Processors, DSP, IO, Memory, Video, Multimedia Engines AVIN PVIN ENABLE VSENSE VOUT AGND PGND 10uF4.7uF EP5357LUI VS2 VS1 VSO VFB LLM Figure 2: Typical Application Schematic.

03409 September 12, 2012 Rev: D

Ordering Information

Part Number Comment Package EP5357LUI LOW VID Range 16-pin QFN T&R EP5357HUI HIGH VID Range 16-pin QFN T&R EP5357LUI-E EP5357LUI Evaluation Board EP5357HUI-E EP5357HUI Evaluation Board Pin Assignments (Top View) PVIN AVIN ENABLE VS0 VS1 VS2 NC(SW) PGND LLM VFB VSENSE AGND VOUT VOUT NC(SW) NC(SW) EP5357LUI 16 15 Figure 3: EP5357LUI Pin Out Diagram (Top View) PVIN AVIN ENABLE VS0 VS1 VS2 NC(SW) PGND LLM NC VSENSE AGND VOUT VOUT NC(SW) NC(SW) EP5357HUI 16 15 Figure 4: EP5357HUI Pin Out Diagram (Top View) Pin Description PIN NAME FUNCTION 1, 15,

16 NC(SW)

NO CONNECT – These pins are internally connected to the common switching node of the internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage to the device. 2 PGND Power ground. Connect this pin to the ground electrode of the Input and output filter capacitors.

3 LLM

LLM (Light Load Mode – “LLM”) pin. Logic-High enables automatic LLM/PWM and logic- low places the device in fixed PWM operation. LLM pin should be connected to ENABLE, or should be disabled before ENABLE is pulled low. 4 VFB/NC EP5357LUI: Feed back pin for external divider option. EP5357HUI: No Connect 5 VSENSE Sense pin for preset output voltages. Refer to application section for proper configuration.

©Enpirion 2012 all rights reserved, E&OE 3 www.enpirion.com PIN NAME FUNCTION 6 AGND Analog ground. This is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider 7, 8 VOUT Regulated Output Voltage. Refer to ap plication section for proper layout and decoupling. 9, 10, VS2, VS1, VS0 Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11. EP5357LUI: Selects one of seven preset output voltages or an external resistor divider. EP5357HUI: Selects one of eight preset output voltages. (Refer to section on output voltage select for more details.) 12 ENABLE Output Enable. Enable = logic high; Disable = logic low 13 AVIN Input power supply fo r the controller circuitry. 14 PVIN Input Voltage for the MOSFET switches. Absolute Maximum Ratings CAUTION: Absolute Maximum ratings ar e stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may cause permanent damage to the device. Exposur e to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN MAX UNITS Input Supply Voltage VIN -0.3 6.0 V Voltages on: ENABLE, VSENSE, VSO – VS2 -0.3 V IN+ 0.3 V Voltages on: VFB (EP5357LUI) -0.3 2.7 V Maximum Operating Junction Temperature TJ-ABS 150 °C Storage Temperature Range TSTG -65 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C 260 °C ESD Rating (based on Human Body Mode) 2000 V Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS Input Voltage Range VIN 2.4 5.5 V Operating Ambient Temperature TA -40 +85 °C Operating Junction Temperature TJ -40 +125 °C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient –0 LFM (Note 1) θJA 85 °C/W Thermal Overload Trip Point TJ-TP +155 °C Thermal Overload Trip Point Hysteresis 25 °C Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards

Electrical Characteristics

NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V. CIN = 4.7µF MLCC, COUT = 10µF MLCC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Operating Input Voltage Range VIN 2.4 5.5 V Under Voltage Lock-out – V IN Rising VUVLO_R 2.0 V Under Voltage Lock-out – V IN Falling VUVLO_F 1.9 V Drop Out Resistance R DO Input to Output Resistance 350 500 m Ω Output Voltage Range VOUT EP5357LUI (VDO = ILOAD X RDO) EP5357HUI 0.6 1.8 VIN-VDO 3.3 V Dynamic Voltage Slew Rate V SLEW EP5357LUI (VID MODE) EP5357HUI (VID MODE) 4

8 V/mS

Accuracy ΔVOUT TA = 25°C, VIN = 3.6V; ILOAD = 100mA ; 0.8V ≤ VOUT ≤ 3.3V -2 +2 % Line Regulation ΔVOUT_LINE 2.4V ≤ VIN ≤ 5.5V 0.03 %/V Load Regulation ΔVOUT_LOAD 0A ≤ ILOAD ≤ 600mA 0.48 %/A Temperature Variation ΔVOUT_TEMPL -40°C ≤ TA ≤ +85°C 24 ppm/°C Output Current IOUT 600 mA Shut-down Current I SD Enable = Low 0.75 µA EP5357HUI Operating Quiescent Current I Q ILOAD=0; Preset Output Voltages, LLM=High 55 µA EP5357LUI Operating Quiescent Current I Q ILOAD=0; Preset Output Voltages, LLM=High 65 µA OCP Threshold ILIM 2.4V ≤ VIN ≤ 5.5V 0.6V ≤ VOUT ≤ 3.3V 1.25 1.4 A Feedback Pin Voltage Initial Accuracy V FB TA = 25°C, VIN = 3.6V; ILOAD = 100mA ; 0.8V ≤ VOUT ≤ 3.3V .588 0.6 0.612 V Feedback Pin Voltage variation over Line, Load, and Temperature V FB 2.4V ≤ VIN ≤ 5.5V 0mA ≤ ILOAD ≤ 600mA .582 0.6 0.618. V Feedback Pin Input Current IFB Note 1 <100 nA VS0-VS2, Pin Logic Low V VSLO 0.0 0.3 V VS0-VS2, Pin Logic High V VSHI 1.4 VIN V VS0-VS2, Pin Input Current I VSX Note 1 <100 nA Enable Pin Logic Low V ENLO 0.3 V Enable Pin Logic High V ENHI 1.4 V Enable Pin Current I ENABLE Note 1 <100 nA

©Enpirion 2012 all rights reserved, E&OE 5 www.enpirion.com PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS LLM Engage Headroom Minimum VIN-VOUT to ensure proper LLM operation 600 mV LLM Pin Logic Low V LLMLO 0.3 V LLM Pin Logic High V LLMHI 1.4 V LLM Pin Current ILLM <100 nA Operating Frequency F OSC 5 MHz Soft Start Operation Soft Start Slew Rate ΔVSS EP5357HUI (VID MODE) EP5357LUI (VID MODE) 8

4 V/mS

VOUT Rise Time TRISE Time to 90% V OUT (VFB MODE) 180 250 uSec Note 1: Parameter guaranteed by design Typical Performance Characteristics 10 100 1000 Load Current (mA) Efficiency (%) Efficiency vs. Load Current: VIN = 5.0V, VOUT (from top to bottom) = 3.3, 2.5, 1.8, 1.2V 10 100 1000 Load Current (mA) Efficiency (%) Efficiency vs. Load Current: VIN = 3.7V, VOUT (from top to bottom) = 2.5, 1.8, 1.2V 10 100 1000 Load Current (mA) Efficiency (%) Efficiency vs. Load Current: VIN = 3.3V, VOUT (from top to bottom) = 2.5, 1.8, 1.2V LLM LLM PWM PWM LLM PWM

©Enpirion 2012 all rights reserved, E&OE 6 www.enpirion.com Start Up Waveform: VIN = 5.0V, VOUT = 3.3V; ILOAD = 10mA (VID MODE) Start Up Waveform: VIN = 5.0V, VOUT = 3.3V; ILOAD = 1000mA (VID MODE) Shut-down Waveform: VIN = 5.0V, VOUT = 3.3V; ILOAD = 10mA, PWM Shut-down Waveform: VIN = 5.0V, VOUT = 3.3V; ILOAD = 500mA, PWM Output Ripple: VIN = 5.0V, VOUT = 1.2V, Load = 10mA LLM enabled Output Ripple: VIN = 5.0V, VOUT = 1.2V, Load = 500mA 50mV/Div 5mV/Div

©Enpirion 2012 all rights reserved, E&OE 7 www.enpirion.com Output Ripple: VIN = 5.0V, VOUT = 3.3V, Load = 10mA LLM enabled Output Ripple: VIN = 5.0V, VOUT = 3.3V, Load = 500mA Output Ripple: VIN = 3.3V, VOUT = 1.8V, Load = 10mA LLM enabled Output Ripple: VIN = 3.3V, VOUT = 1.8V Load = 500mA Output Ripple: VIN = 3.3V, VOUT = 1.2V, Load = 10mA LLM enabled Output Ripple: VIN = 3.3V, VOUT = 1.2V, Load = 500mA 5mV/Div 50mV/Div 5mV/Div 50mV/Div 50mV/Div 5mV/Div

©Enpirion 2012 all rights reserved, E&OE 8 www.enpirion.com Load Transient: VIN = 5.0V, VOUT = 1.2V Load stepped from 0mA to 500mA, LLM enabled Load Transient: VIN = 5.0V, VOUT = 1.2V Load stepped from 10mA to 500mA Load Transient: VIN = 3.3V, VOUT = 1.8V Load stepped from 0mA to 500mA, LLM enabled Load Transient: VIN = 3.3V, VOUT = 1.8V Load stepped from 10mA to 500mA

©Enpirion 2012 all rights reserved, E&OE 9 www.enpirion.com Functional Block Diagram DAC Switch VREF (+) (-) Error Amp VSENSE VFB VOUT Package Boundry P-Drive N-Drive UVLO Thermal Limit Current Limit Soft Start Sawtooth Generator (+) (-) PWM Comp PVIN ENABLE PGND Logic Compensation Network NC(SW) Voltage Select VS0 VS1AVIN VS2AGND Mode Logic LLM Figure 5: Functional Block Diagram

©Enpirion 2012 all rights reserved, E&OE 10 www.enpirion.com Detailed Description Functional Overview The EP5357xUI require s only 2 small MLCC capacitors for a complete DC-DC converter solution. The device integrates MOSFET switches, PWM controller, Gate-drive, compensation, and inductor into a tiny 2.5mm x 2.25mm x 1.1mm QFN package. Advanced package design, along with the high level of integration, provides very low output ripple and noise. The EP5357xUI uses voltage mode control for high noise immunity and load matching to advanced ≤90nm loads. A 3-pin VID allows the user to choose from one of 8 output voltage settings. The EP5357xUI comes with two VID output voltage ranges. The EP5357HUI provides V OUT settings from 1.8V to 3.3V, the EP 5357LUI provides VID settings from 0.8V to 1.5V, and also has an external resistor divi der option to program output setting over the 0.6V to V IN-0.25V range. The EP5357xUI pr ovides the industry’s highest power density of any 600mA DCDC converter solution. The key enabler of this revolutionary integration is Enpiri on’s proprietary power MOSFET technology. The advanced MOSFET switches are implement ed in deep-submicron CMOS to supply very low switching loss at high switching frequencies and to allow a high level of integration. The semiconductor process allows seem-less integrat ion of all switching, control, and compensation circuitry. The proprietary magnetics design provides high-density/high-value magnetics in a very small footprint. Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. Protection features in clude under-voltage lock- out (UVLO), over-current protection (OCP), short circuit protection, and thermal overload protection. Integrated Inductor The EP5357xUI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly simplifies the power supply design process. The inherent shielding and compact construction of the integrated inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board. Further, the package layout is optimized to reduce the electrical path length for the high di/dT input AC ripple currents that are a major source of radiated emissions from DC-DC converters. The integrated inductor provides the optimal solution to the complexity, output ripple, and noise that plague low power DCDC converter design. Voltage Mode Control The EP5357xUI utilizes an integrated type III compensation network. Voltage mode control is inherently impedance matched to the sub 90nm process technology that is used in today’s advanced ICs. Voltage mode control also provides a high degr ee of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. The very high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. Light Load Mode (LLM) Operation The EP5357xUI uses a proprietary light load mode to provide high effi ciency in the low load operating condition. When the LLM pin is high, the device is in automatic LLM/PWM mode. When the LLM pin is low, the device is in PWM mode. In automatic LLM/PWM mode, when a light load condition is detected, the device will (1) step V OUT up by approximat ely 1.5% above the nominal operating output voltage setting, VNOM, and then (2) shut down unnecessary circuitry, and (3) monitor VOUT. When VOUT falls below VNOM, the device will repeat (1), (2), and (3). The voltage step up, or pre-positioning, improves transient droop when a load transient causes a transition from LLM mode to PWM mode. If a load transient occurs, causing V OUT to fall below the threshold V MIN, the device will

©Enpirion 2012 all rights reserved, E&OE 11 www.enpirion.com exit LLM operation and begin normal PWM operation. Figure 6 demonstrates V OUT behavior during transition into and out of LLM operation. VOUT IOUT LLM Ripple PWM Ripple VMAX VNOM VMIN Load Step Figure 6: VOUT Behavior in LLM Operation Figure 7: VOUT Droop during Periodic LLM Exit Many multi-mode DCDC converters suffer from a condition that occurs when the load current increases only slowly so that there is no load transient driving V OUT below the VMIN threshold. In this condition, the device would never exit LLM operation. This could adversely affect efficiency and cause unwanted ripple. To prevent this from occurring, the EP5357xUI periodically exits LLM mode into PWM mode and measures the load cu rrent. If the load current is above the LLM threshold current, the device will remain in PWM mode. If the load current is below the LLM threshold, the device will re-enter LLM operation. There will be a small droop in V OUT at the point where the device exits and re-enters LLM, as shown in Figure 7. LLM Threshold Current vs. VOUT 100 150 200 250 VOUT (V) LLM Threshold (mA) VIN=5V (top curve) VIN=4.2V VIN=3.7V VIN=3.3V (bottom curve) Figure 8: Typical load current for LLM engage and disengage versus VOUT for selected input voltages Table 1: Load current below which the device can be certain to be in LLM operation. These values are guaranteed by design 3.3 3.7 4.3 5.0 3.30 105 147 3.00 62 122 156 2.90 89 126 158 2.60 56 106 136 162 2.50 69 111 138 162 2.20 101 120 141 160 2.10 105 122 141 158 1.80 111 124 138 150 1.50 111 120 130 138 1.45 111 119 128 136 1.20 105 111 117 122 1.15 103 108 114 119 1.10 101 106 111 116 1.05 99 104 108 113 0.80 87 89 92 94 VIN VOUT The load current at which the device will enter LLM mode is a function of input and output voltage. Figure 8 shows the typical value at which the device will enter LLM operation. The actual load current at which the device will enter LLM operation can vary by +/-30%. Table 1 shows the minimum load current below which the device is guaranteed to be in LLM operating mode. To ensure normal LLM operation, LLM mode should be enabled/dis abled with specific sequencing. For applications with explicit LLM pin control, enable LLM after VIN ramp up is complete; disable LLM before VIN ramp down. Device exits LLM, tests load current

©Enpirion 2012 all rights reserved, E&OE 12 www.enpirion.com For applications with ENABLE control, tie LLM to ENABLE; enable device after VIN ramp up is complete and disable device before VIN ramp down begins. For devices with ENABLE and LLM tied to VIN, contact Enpirion Applications engineering for specific recommendations Increased output filter capacitance and/or increased bulk capacitance at the load will decrease the magnitude of the LLM ripple. Refer to the section on output filter capacitance for maximum values of output filter capacitance and the Soft-Start section for maximum bulk capacitance at the load. NOTE: For proper LLM operation the EP5357xUI requires a minimum difference between V IN and V OUT of 600mV. If this condition is not met, the device cannot be assured proper LLM operation. NOTE: Automatic LLM/PWM is not available when using the external resistor divider option for VOUT programming. Soft Start Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the “ENABLE” pin is asserted “high”. Digital control circuitry limits the V OUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The EP5357HUI has a soft- start slew rate that is twice that of the EP5357LUI. When the EP5357LUI is c onfigured in external resistor divider mode, the device has a fixed VOUT ramp time. Therefore, the ramp rate will vary with the output volt age setting. Output voltage ramp time is gi ven in the Electrical Characteristics Table. Excess bulk capacitance on the output of the device can cause an over-current condition at startup. The maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as: EP5357LUI: C OUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 200uF EP5357HUI: COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 100uF EP5357LUI in external divider mode: COUT_TOTAL_MAX = 2.25x10-4/VOUT Farads The nominal value for C OUT is 10uF. See the applications section for more details. Over Current/Short Circuit Protection The current limit function is achieved by sensing the current flowing through a sense P- MOSFET which is compared to a reference current. When this level is exceeded the P- FET is turned off and the N-FET is turned on, pulling V OUT low. This condition is maintained for approximately 0.5mS and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat. Under Voltage Lockout During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the in put voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. Enable The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. NOTE: The ENABLE pin must not be left floating. Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature t he thermal shutdown circuit turns off the co nverter output voltage thus allowing the device to cool. When the junction temperature dec reases by 15C°, the device will go through the normal startup process.

Application Information

10μF4.7μF VOUT VOUT AGND ENABLE PGND AVIN LLM Figure 9: Application Circuit, EP5357HUI, configured for LLM Enabled. Note that all control signals should be connected to AVIN or AGND. VIN VSENSE PVIN VS1 VS2 VS0 10μFμF VOUT VOUT AGND ENABLE VFB PGND AVIN LLM Figure 10: Application Circuit, EP5357LUI, configured for LLM Enabled, showing the VFB function. Output Voltage Programming The EP5357xUI utilizes a 3-pin VID to program the output voltage value. The VID is available in two sets of output VID programming ranges. The VID pins should be connected either to AVIN or to AGND to avoi d noise coupling into the device. The “Low” range is optim ized for low voltage applications. It comes with preset VID settings ranging from 0.80V and 1.5V. This VID set also has an external divider option. To specify this VID range, order part number EP5357LUI. The “High” VID set pr ovides output voltage settings ranging from 1.8V to 3.3V. This version does not have an external divider option. To specify this VID range, order part number EP5357HUI. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. NOTE: The VID pins must not be left floating. EP5357L Low VID Range Programming The EP5357LUI is designed to provide a high degree of flexibility in powering applications that require low V OUT settings and dynamic voltage scaling (DVS). The device employs a 3-pin VID architecture that allows the user to choose one of seven (7) preset output voltage settings, or the user can select an external voltage divider option. The VID pin settings can be changed on the fly to implement glitch- free voltage scaling. Table 2: EP5357LUI VID Voltage Select Settings VS2 VS1 VS0 VOUT 000 1 . 5 0 001 1 . 4 5 010 1 . 2 0 011 1 . 1 5 100 1 . 1 0 101 1 . 0 5 110 0 . 8

111 E X T

Table 2 shows the VS2-VS0 pin logic states for the EP5357LUI and the associated output voltage levels. A lo gic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to AGND or to a “low” logic voltage level. These pins can be either ha rdwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate.

©Enpirion 2012 all rights reserved, E&OE 14 www.enpirion.com EP5357LUI External Voltage Divider The external divider option is chosen by connecting VID pins VS2-VS0 to V IN or a logic “1” or “high”. The EP5357LUI uses a separate feedback pin, V FB, when using the external divider. V SENSE must be connected to V OUT as indicated in Figure 11 . The output voltage is selected by the following formula: () Rb Ra OUT V V+ =1 6 . 0 Ra must be chosen as 237KΩ to maintain loop gain. Then Rb is given as: Ω−= 6 . 0 10 2 . 1423 OUT b V x R VOUT can be programmed ov er the range of 0.6V to (VIN – 0.25V). NOTE: Dynamic Voltage Scaling is not allowed between internal preset voltages and external divider. NOTE: LLM is not functional when using the external divider option. Tie the LLM pin to AGND. VIN VSense VS0 VS2 EP5357L 10μF4.7uF VOUT VOUT AGND ENABLE Ra Rb VFB VS1 PGND AVIN PVIN Figure 11: EP5357LUI using external divider EP5357HUI High VID Range Programming The EP5357HUI V OUT settings are optimized for higher nominal voltages such as those required to power IO, RF , or IC memory. The preset voltages range from 1.8V to 3.3V. There are eight (8) pr eset output voltage settings. The EP5357HUI does not have an external divider option. As with the EP5357LUI, the VID pi n settings can be changed while the device is enabled. Table 3 shows the VS0-VS2 pin logic states for the EP5357HUI and the associated output voltage levels. A lo gic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to AGND or to a “low” logic voltage level. These pins can be either ha rdwired to AVIN or AGND or alternatively can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level between the logic high and logic low is indeterminate. These pins must not be left floating. Table 3: EP5357HUI VID Voltage Select Settings VS2 VS1 VS0 VOUT 000 3 . 3 001 3 . 0 010 2 . 9 011 2 . 6 100 2 . 5 101 2 . 2 110 2 . 1 111 1 . 8 Power-Up/Down Sequencing During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE) together during power up or power down meets these requirements Pre-Bias Start-up The EP5357xUI does not support startup into a pre-biased condition. Be sure the output capacitors are not charged or the output of the EP5357xUI is not pre-biased when the EP5357xUI is first enabled. Input Filter Capacitor For ILOAD ≤ 500mA, CIN = 2.2uF For ILOAD > 500mA CIN = 4.7uF. 0402 capacitor case size is acceptable. The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with fre quency, bias, and with

©Enpirion 2012 all rights reserved, E&OE 15 www.enpirion.com temperature, and are not suitable for switch- mode DC-DC converter input filter applications. Output Filter Capacitor For VIN ≤ 4.3V, COUT_MIN = 10uF 0603 MLCC. For VIN > 4.3V, COUT_MIN = 10uF 0805 MLCC. Ripple performance can be improved by using 2x10µF 0603 MLCC c apacitors (for any allowed VIN). The maximum output filter capacitance next to the output pins of the device is 60µF low ESR MLCC capacitance. V OUT has to be sensed at the last output filter capacitor next to the EP5357xUI. Additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient separation between the V OUT Sense point and the bulk capacitance. Excess total capacitance on the output (Output Filter + Bulk) can cause an over-current condition at startup. Refer to the section on Soft-Start for the maximum total capacitance on the output. The output capacitor mu st use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch- mode DC-DC converter output filter applications. Recommended PCB Footprint Figure 12: EP5357 Package PCB Footprint

53 Frontage Road Suite 210

Hampton, NJ 08827 Phone: +1 908-894-6000 Fax: +1 908-894-6090 Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion.

Product Information

EP5357HUI specifications and overview.

Summary

600mA Synchronous Buck Regulator with Integrated Inductor

Description

600mA Synchronous Buck Regulator with Integrated Inductor

Source title EP5357HUI Datasheet(PDF) - Enpirion, Inc.

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