EEP24AA025

24AA024_V01 MICROCHIP | Alldatasheet

Document overview

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• PDF pages: 41

Technical content

Features

• Single Supply with Operation from 1.7V to 5.5V for 24AA024/24AA025 Devices and 2.5V to 5.5V for 24LC024/24LC025 Devices
• Low-Power CMOS Technology: - Read current: 1 mA, maximum - Standby current: 1 µA, maximum (I-temp.)
• Organized as a Single Block of 256 Bytes (256 x 8)
• Two-Wire Serial Interface, I2C Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time: 5 ms Maximum
• Self-timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect on 24XX024 Devices
• High Reliability: - More than one million erase/write cycles - Data retention: >200 years - ESD protection: >4000V
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges: - Industrial (I): -40°C to +85°C - Extended (E): -40°C to +125°C Packages
• 8-Lead DFN, 8-Lead TDFN, 8-Lead MSOP, 8- Lead PDIP, 8-Lead SOIC, 8-Lead TSSOP and 6- Lead SOT-23 (24XX025 only)

Description

The Microchip Technology Inc. 24AA024/24LC024/ 24AA025/24LC025 is a 2-Kbit Serial Electrically Erasable PROM (EEPROM). The device is organized as one block of 256 x 8-bit memory with a two-wire serial interface. Its low-voltage design permits operation down to 1.7V, with standby and active currents of only 1 µA and 1 mA, respectively. The device has a page write capability for up to 16 bytes of data. Functional address lines allow the connection of up to eight 24AA024/ 24LC024/24AA025/24LC025 devices on the same bus for up to 16 Kbits of contiguous EEPROM memory. Package Types Part Number V CC Range Max. Clock Temp. Range Write Protect Available Packages 24AA024 1.7V-5.5V 400 kHz (1) I Yes MC, MNY, MS, P, SN, ST 24AA025 1.7V-5.5V 400 kHz (1) I No MC, MNY, MS, OT, P, SN, ST 24LC024 2.5V-5.5V 400 kHz I, E Yes MC, MNY, MS, P, SN, ST 24LC025 2.5V-5.5V 400 kHz I, E No MC, MNY, MS, OT, P , SN, ST Note 1: 100 kHz for VCC <2 . 5 V Note 1: WP pin is not internally connected on the 24XX025. VSS VCC SCL SDA PDIP/SOIC/TSSOP/MSOP VSS WP SCL SDA VCC8 SOT-23 VCCSCL SDA VSS A0 DFN/TDFN 3 4 WP (1) (1) 2-Kbit I2C Serial EEPROM

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 2  2007-2022 Microchip Technology Inc. and its subsidiaries Block Diagram I/O Control Logic Memory Control Logic XDEC HV Generator EEPROM Array Write-Protect Circuitry YDEC VCC VSS Sense Amp. R/W Control SDA SCL A0 A1 A2 WP Note 1: WP pin is not internally connected on the 24XX025. (1)

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 3 24AA024/24LC024/24AA025/24LC025

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†) TABLE 1-1: DC CHARACTERISTICS † NOTICE: Stresses above those listed under “Absolute Maxi mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of th is specification is not im plied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Industrial (I): T A = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): T A = -40°C to +125°C, VCC = +2.5V to +5.5V Param. No. Symbol Characteristic Min. Max. Units Conditions D1 V IH High-level Input Voltage 0.7V CC —V D2 V IL Low-level Input Voltage — 0.3V CC V0 . 2 V CC for VCC <2 . 5 V D3 V HYS Hysteresis of Schmitt Trigger Inputs 0.05VCC —V ( Note) D4 V OL Low-level Output Voltage — 0.40 V I OL = 3.0 mA, VCC =2 . 5 V D5 I LI Input Leakage Current — ±1 µA V IN =V SS or VCC D6 I LO Output Leakage Current — ±1 µA V OUT =V SS or VCC D7 CIN, COUT Pin Capacitance (all inputs/outputs) —1 0 p F V CC =5 . 5 V (Note) TA = 25°C, FCLK =1M H z D8 I CCWRITE Operating Current —3 m A V CC = 5.5V, SCL = 400 kHz D9 I CCREAD —1 m A D10 I CCS Standby Current —1 µ A SDA = SCL = VCC A0, A1, A2, WP = VSS, I-Temp —5 µ A SDA = SCL = VCC A0, A1, A2, WP = VSS, E-Temp Note: This parameter is periodically sampled and not 100% tested.

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 4  2007-2022 Microchip Technology Inc. and its subsidiaries TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): T A = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): T A = -40°C to +125°C, VCC = +2.5V to +5.5V Param. No. Symbol Characteristic Min. Max. Units Conditions 1F CLK Clock Frequency — 100 kHz 1.7V ≤ VCC <1 . 8 V — 400 kHz 1.8V ≤ VCC ≤ 5.5V 2T HIGH Clock High Time 4000 — ns 1.7V ≤ VCC <1 . 8 V 600 — ns 1.8V ≤ VCC ≤ 5.5V 3T LOW Clock Low Time 4700 — ns 1.7V ≤ VCC < 1.8V 1300 — ns 1.8V ≤ VCC ≤ 5.5V 4T R SDA and SCL Rise Time — 1000 ns 1.7V ≤ VCC < 1.8V (Note 1) — 300 ns 1.8V ≤ VCC ≤ 5.5V (Note 1) 5T F SDA and SCL Fall Time — 1000 ns 1.7V ≤ VCC < 1.8V (Note 1) — 300 ns 1.8V ≤ VCC ≤ 5.5V (Note 1) 6T HD:STA Start Condition Hold Time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 7T SU:STA Start Condition Setup Time 4700 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 8T HD:DAT Data Input Hold Time 0 — ns ( Note 2) 9T SU:DAT Data Input Setup Time 250 — ns 1.7V ≤ VCC < 1.8V 100 — ns 1.8V ≤ VCC ≤ 5.5V 10 T SU:STO Stop Condition Setup Time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 11 T SU:WP WP Setup Time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 12 T HD:WP WP Hold Time 4700 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 13 T AA Output Valid from Clock — 3500 ns 1.7V ≤ VCC < 1.8V (Note 2) — 900 ns 1.8V ≤ VCC ≤ 5.5V (Note 2)

14 T BUF

Bus Free Time: Bus time must be free before a new transmission can start 4700 — ns 1.7V ≤ VCC < 1.8V 1300 — ns 1.8V ≤ VCC ≤ 5.5V

15 T SP Input Filter Spike Suppression

(SDA and SCL pins) —5 0 n s ( Note 1 and Note 3)

16 T WC Write Cycle Time (byte or

page) —5 m s 17 — Endurance 1,000,000 — cycles 25°C, VCC = 5.5V, Page mode (Note 4) Note 1: Not 100% tested. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization.

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 5 24AA024/24LC024/24AA025/24LC025 FIGURE 1-1: BUS TIMING DATA (unprotected) (protected) SCL SDA In SDA Out WP D3 4 11 12

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 6  2007-2022 Microchip Technology Inc. and its subsidiaries

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE

2.1 Chip Address Inputs (A0, A1, A2)

The A0, A1 and A2 inputs are used by the 24AA024/ 24LC024/24AA025/24LC025 for multiple device operation. The levels on these inputs are compared with the corresponding bits in the client address. The chip is selected if the comparison is true. Up to eight devices (four for SOT-23 package) may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either V CC or V SS. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘ 1’ before normal device operation can proceed.

2.2 Serial Address/Data Input/Output

(SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal; therefore, the SDA bus requires a pull-up resistor to V CC (typical 10 k for 100 kHz and 2 k for 400 kHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.

2.3 Serial Clock (SCL)

The SCL input is used to synchronize the data transfer from and to the device.

2.4 Write-Protect (WP) (24XX024 Only)

WP is the hardware write-protect pin. It must be tied to VCC or VSS. If tied to Vcc, hardware write protection is enabled. If WP is tied to Vss, the hardware write protection is disabled. Note that the WP pin is available only on the 24XX024. This pin is not internally connected on the 24XX025.

2.5 Noise Protection

The 24AA024/24LC024/24AA025/24LC025 employs a VCC threshold detector circuit which disables the internal erase/write logic if the V CC is below 1.5V at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. Name PDIP SOIC TSSOP DFN/TDFN (1) MSOP SOT-23 Description A0 1 1 1 1 1 5 Address Pin AO A1 2 2 2 2 2 4 Address Pin A1 A2 3 3 3 3 3 — Address Pin A2 V SS 4 4 4 4 4 2 Ground SDA 5 5 5 5 5 3 Serial Address/Data I/O SCL 6 6 6 6 6 1 Serial Clock WP 7 7 7 7 7 — Write-Protect Input VCC 8 8 8 8 8 6 Power Supply Note 1: Exposed pad on DFN/TDFN can be connected to VSS or left floating.

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3.0 FUNCTIONAL DESCRIPTION

The 24AA024/24LC024/24AA025/24LC025 supports a bidirectional, two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as receiver. The bus has to be controlled by a host device that gener ates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24AA024/ 24LC024/24AA025/24LC025 works as client. Both host and client can operate as transmitter or receiver, but the host device determines which mode is activated.

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 8  2007-2022 Microchip Technology Inc. and its subsidiaries

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when, after a Start condition, th e data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop conditi on. The number of the data bytes transferred between the Start and Stop conditions is determined by the host device and is, the- oretically, unlimited (though only the last 16 bytes will be stored when performing a write operation). When an overwrite does occur, it will replace data in a First-In- First-Out (FIFO) principle.

4.5 Acknowledge

Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The host device must generate an extra clock pulse, which is associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the acknowledge-related clock pulse. Moreover, setup and hold times must be taken into account. A host must signal an end of data to the client by not generating an Acknowledge bit on the last byte that has been clocked out of the client. In this case, the client must leave the data line high to enable the host to generate the Stop condition (Figure 4-2). FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS FIGURE 4-2: ACKNOWLEDGE TIMING Note: The 24AA024/24LC024/24AA025/24LC025 does not generate any Acknowledge bits if an internal programming cycle is in progress. (A) (B) (C) (D) (A) (C)SCL SDA Start Condition Address or Acknowledge Valid Data Allowed to Change Stop Condition SCL 9876543211 2 3 Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. Receiver must release the SDA line at this point so the Transmitter can continue sending data. SDA Acknowledge Bit Data from transmitterData from transmitter

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5.0 DEVICE ADDRESSING

A control byte is the first byte received following the Start condition from the host device. The control byte consists of a 4-bit cont rol code. For the 24AA024/ 24LC024/24AA025/24LC025, this is set as ‘ 1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24AA024/24LC024/24AA025/24LC025 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits (MSb) of the word address. The combination of the 4-bit control code and the next three bits are called the client address. For the SOT-23 package, the A2 address pin is not available. During device addressing, the A2 Chip Select bit should be set to ‘0’. The last bit of the control byte is the Read/Write (R/W) bit and it defines the operation to be performed. When set to a one, a read operation is selected. When set to a zero, a write operation is selected. The next byte received defines the address of the first data byte (Figure 5-2). Following the Start condition, the 24AA024/24LC024/24AA025/24LC025 monitors the SDA bus checking the control byte being transmitted. Upon receiving a valid client address and the R/W bit, the client device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA024/24LC024/24AA025/24LC025 will select a read or write operation. FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Addressing Across

The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to

16 Kbits by adding up to eight 24AA024/24LC024/

24AA025/24LC025 devices on the same bus. In this case, software can use A0 of the control byte as address bit A8; A1 as address bit A9; and A2 as address bit A10. It is not possible to sequentially read across device boundaries. For the SOT-23 package, up to four 24AA025/24LC025 devices can be added for up to 8 Kbits of address space. In this case, software can use A0 of the control byte as address bit A8, and A1 as address bit A9. It is not possible to sequentially read across device boundaries. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

1010 A2 A1 A0SA C K R/W

1 •010 R/W A Control Byte Word Address Byte Control Code Chip Select bits A A A A 0 7

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 10  2007-2022 Microchip Technology Inc. and its subsidiaries

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the Start signal from the host, the device code(four bits), the Chip Select bits (three bits) and the R/W bit (which is a logic low) are placed onto the bus by the host transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the host is the word address and will be written into the Address Pointer of the 24AA024/24LC024/24AA025/24LC025. After receiving another Acknowledge signal from the 24AA024/24LC024/24AA025/24LC025, the host device will transmit the data word to be written into the addressed memory location. The 24AA024/24LC024/ 24AA025/24LC025 acknowledges again and the host generates a Stop condition. This initiates the internal write cycle and, during this time, the 24AA024/ 24LC024/24AA025/24LC025 will not generate Acknowledge signals ( Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection (24XX024 only) has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if write protection is enabled.

6.2 Page Write

The write control byte, word address and the first data byte are transmitted to the 24AA024/24LC024/ 24AA025/24LC025 in the same way as in a byte write. However, instead of generat ing a Stop condition, the host transmits up to 15 additional data bytes to the 24AA024/24LC024/24AA025/24LC025, which are temporarily stored in the on-chip page buffer and will be written into the memory once the host has transmitted a Stop condition. Upon receipt of each word, the four lower-order Address Pointer bits, which form the byte counter, are internally incremented by one. The higher-order four bits of the word address remain constant. If the host should transmit more than 16 bytes prior to generating the Stop condition, the Address Pointer will roll over and the previously received data will be overwritten. As wit h the byte-write operation, once the Stop condition is received, an internal write cycle will begin ( Figure 6-2). If an attempt is made to write to the protected porti on of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if write protection is enabled.

6.3 Write Protection

The WP pin (available on 24XX024 only) must be tied to VCC or V SS. If tied to V CC, the entire array will be write-protected. If the WP pin is tied to V SS, write operations to all address locations are allowed. The WP pin is not available on the SOT-23 package. FIGURE 6-1: BYTE WRITE Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. S P Bus Activity Host SDA Line Bus Activity S T A R T S T O P Control Byte Word Address Data A C K A C K A C K

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 11 24AA024/24LC024/24AA025/24LC025 FIGURE 6-2: PAGE WRITE S P Bus Activity Host SDA Line Bus Activity S T A R T Control Byte Word Address (n) Data (n) Data (n + 15) S T O P A C K A C K A C K A C K A C K Data (n +1)

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 12  2007-2022 Microchip Technology Inc. and its subsidiaries

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the host, the device initiates the internally timed write cycle, with ACK polling being initiated immediately. This involves the host sending a Start condition, followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is comp lete, the device will return the ACK and the host can then proceed with the next read or write operation. See Figure 7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Next Operation No Yes

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8.0 READ OPERATIONS

Read operations are initiated in the same way as write operations, with the exce ption that the R/W bit of the client address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read.

8.1 Current Address Read

The 24AA024/24LC024/24AA025/24LC025 contains an Address Pointer that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address ‘n’, the next current address read operation would access data from address n + 1. Upon receipt of the client address with the R/W bit set to ‘1’, the 24AA024/ 24LC024/24AA025/24LC025 issues an acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but generate a Stop condition, which causes the 24AA024/24LC024/ 24AA025/24LC025 to discontinue transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24AA024/24LC024/24 AA025/24LC025 as part of a write operation. Once the word address is sent, the host generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The host then issues the control byte again, but with the R/W bit set to a ‘1’. The 24AA024/24LC024/24AA025/24LC025 will then issue an acknowledge and transmit the 8-bit data word. The host will not acknowledge the transfer, though it does generate a Stop condition, which causes the 24AA024/24LC024/24AA025/24LC025 to discontinue transmission ( Figure 8-2). After this command, the internal Address Pointer will point to the address location following the one that was just read.

8.3 Sequential Read

Sequential reads are initiated in the same way as a random read except that after the 24AA024/24LC024/ 24AA025/24LC025 transmits the first data byte, the host issues an acknowledge (as opposed to a Stop condition in a random read). This directs the 24AA024/ 24LC024/24AA025/24LC025 to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential r eads, the 24AA024/24LC024/ 24AA025/24LC025 contains an internal Address Pointer that is incremented by one upon completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 0FFh to address 000h. FIGURE 8-1: CURRENT ADDRESS READ SP Bus Activity Host SDA Line Bus Activity S T O P Control Byte Data (n) A C K N o A C K S T A R T Block Select Bits

1010 A0 A1 A2 1

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9.0 PACKAGING INFORMATION

9.1 Package Marking Information*

8-Lead PDIP (300 mil) Example: 8-Lead SOIC (3.90 mm) Example: 8-Lead TSSOP Example: 24LC024 I/P 13F 2224 24LC024I SN 2224 13F 8-Lead MSOP Example: XXXX TYWW NNN XXXXT YWWNNN 4L24 I224 13F 4L24I 22413F XXXXXXXT XXXXYYWW NNN 8-Lead 2x3 DFN Example: XXX YWW NN 2P4 224 8-Lead 2x3 TDFN Example: XXX YWW NN AP4 224

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 16  2007-2022 Microchip Technology Inc. and its subsidiaries Part Number 1st Line Marking Codes TSSOP MSOP DFN TDFN SOT-23 I-TEMP E-TEMP I-TEMP E-TEMP I-TEMP E-TEMP 24AA024 4A24 4A24T 2P1 — AP1 — — — 24LC024 4L24 4L24T 2P4 AP5 AP4 2P5 — — 24AA025 4A25 4A25T 2R1 — AR1 — HQNN HRNN 24LC025 4L25 4L25T 2R4 AR5 AR4 2R5 HMNN HPNN 6-Lead SOT-23 XXNN HQEF Example: Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) RoHS compliant JEDEC ® designator for Matte Tin (Sn) Note: Standard OTP marking consists of Mi crochip part number, year code, week code, and traceability code. Note: For very small packages with no room for the JEDEC ® designator , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part num ber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 17 24AA024/24LC024/24AA025/24LC025 B A For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing No. C04-018-P Rev F Sheet 1 of 2 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] eB E A L 8X b 8X b1 c C PLANE .010 C N D NOTE 1 TOP VIEW END VIEWSIDE VIEW e

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 18  2007-2022 Microchip Technology Inc. and its subsidiaries Microchip Technology Drawing No. C04-018-P Rev F Sheet 2 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing eB - - .430 BSC: Basic Dimension. Theoretically exact value shown without tolerances. protrusions shall not exceed .010" per side. Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or Pin 1 visual index feature may vary, but must be located within the hatched area. § Significant Characteristic Dimensioning and tolerancing per ASME Y14.5M e DATUM A DATUM A e b e b e ALTERNATE LEAD DESIGN (NOTE 5) 5. Lead design above seating plane may vary, based on assembly vendor.

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 19 24AA024/24LC024/24AA025/24LC025

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-SN Rev J Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

H ș c 4X ș1 4X ș1 (L1) L R VIEW C SEE VIEW C NOTE 1 D

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 20  2007-2022 Microchip Technology Inc. and its subsidiaries Microchip Technology Drawing No. C04-057-SN Rev J Sheet 2 of 2 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: 5. Datums A & B to be determined at Datum H. Foot Angle 0° – 8° 8°–0°Lead Angle 0.51–0.31bLead Width 0.25–0.17cLead Thickness 1.27–0.40LFoot Length 0.50–0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25–0.10A1Standoff -–1.25A2Molded Package Thickness 1.75––AOverall Height

1.27 BSCePitch

Footprint L1 1.04 REF Mold Draft Angle 5° – 15° ș ––0.07R1Lead Bend Radius ––0.07RLead Bend Radius

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 21 24AA024/24LC024/24AA025/24LC025 RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-SN Rev J BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

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 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 25 24AA024/24LC024/24AA025/24LC025 TOP VIEW VIEW A–A SIDE VIEW Note: http://www.microchip.com/packaging For the most current package drawings, please see the Microchip Packaging Specification located at 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Microchip Technology Drawing C04-111-MS Rev D A B 0.25 C 2X 4 TIPS

0.25 C A-B D

A A 0.20 H 0.20 H N SEE DETAIL B NOTE 1 C 0.10 C H 8X b e D D E E A A2 SEATING PLANE Sheet 1 of 2 D

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 26  2007-2022 Microchip Technology Inc. and its subsidiaries For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2 C SEATING PLANE H Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Molded Package Width Molded Package Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.65 BSC

0.85 0.40 0.22 0.00 0.60 MILLIMETERS MIN NOM 0.80 0.40 1.10 0.15 MAX L1 0.95 REFFootprint Overall Length D 3.00 BSC Terminal Thickness c 0 . 0 8–0 . 2 3 R ș –0.07 –Lead Bend Radius –0.07 –Lead Bend Radius –0° 8°Foot Angle –5° 15°Mold Draft Angle 0.75 0.95

4.90 BSC

3.00 BSC

ș c 4X ș1 4X ș1 L (L1) R Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Microchip Technology Drawing C04-111-MS Rev D

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 27 24AA024/24LC024/24AA025/24LC025 RECOMMENDED LAND PATTERN Dimension Limits Units Contact Pitch MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) Y X 1.45 0.45 NOM CContact Pad Spacing 4.40 Contact Pad to Contact Pad (X4) G1 2.95 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: E C Contact Pad to Contact Pad (X6) GX 0.20 X Y GX SILK SCREEN 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Microchip Technology Drawing C04-2111-MS Rev D

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 28  2007-2022 Microchip Technology Inc. and its subsidiaries /g37/g36 /g19/g17/g20/g24/g38 /g19/g17/g20/g24/g38 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g19/g24/g38 /g11/g39/g36/g55/g56/g48/g3/g37/g12 /g11/g39/g36/g55/g56/g48/g3/g36/g12 /g38 /g54/g40/g36/g55/g44/g49/g42 /g51/g47/g36/g49/g40 /g49/g50/g55/g40/g3/g20 /g49 /g21/g59 /g55/g50/g51/g3/g57/g44/g40/g58 /g54/g44/g39/g40/g3/g57/g44/g40/g58 /g37/g50/g55/g55/g50/g48/g3/g57/g44/g40/g58 /g49/g50/g55/g40/g3/g20 /g20/g21 /g49 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g20/g19/g38 /g19/g17/g19/g27/g38 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g3/g38/g19/g23/g16/g20/g21/g22/g3/g53/g72/g89/g3/g40/g3/g54/g75/g72/g72/g87/g3/g20/g3/g82/g73/g3/g21 /g39 /g40 /g36 /g11/g36/g22/g12 /g27/g59/g3/g69 /g72 /g21/g59 /g39/g21 /g40/g21 /g46 /g47 /g27/g59 /g36/g20 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g27/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g39/g88/g68/g79/g3/g41/g79/g68/g87/g15/g3/g49/g82/g3/g47/g72/g68/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g48/g38/g12/g3/g16/g3/g21/g91/g22/g91/g20/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g39/g41/g49/g64 /g20/g21

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 29 24AA024/24LC024/24AA025/24LC025 /g49/g50/g55/g40/g3/g21 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g3/g38/g19/g23/g16/g20/g21/g22/g3/g53/g72/g89/g3/g40/g3/g54/g75/g72/g72/g87/g3/g21/g3/g82/g73/g3/g21 /g49/g88/g80/g69/g72/g85/g3/g82/g73/g3/g55/g72/g85/g80/g76/g81/g68/g79/g86 /g50/g89/g72/g85/g68/g79/g79/g3/g43/g72/g76/g74/g75/g87 /g55/g72/g85/g80/g76/g81/g68/g79/g3/g58/g76/g71/g87/g75 /g50/g89/g72/g85/g68/g79/g79/g3/g58/g76/g71/g87/g75 /g55/g72/g85/g80/g76/g81/g68/g79/g3/g47/g72/g81/g74/g87/g75 /g40/g91/g83/g82/g86/g72/g71/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75 /g55/g72/g85/g80/g76/g81/g68/g79/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g51/g76/g87/g70/g75 /g54/g87/g68/g81/g71/g82/g73/g73 /g56/g81/g76/g87/g86 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g36/g20 /g36 /g69 /g40/g21 /g36/g22 /g72 /g47 /g40 /g49 /g19/g17/g24/g19/g3/g37/g54/g38 /g19/g17/g21/g19/g3/g53/g40/g41 /g20/g17/g24/g19 /g19/g17/g22/g19 /g19/g17/g21/g19 /g19/g17/g27/g19 /g19/g17/g19/g19 /g19/g17/g21/g24 /g19/g17/g23/g19 /g16 /g19/g17/g28/g19 /g19/g17/g19/g21 /g22/g17/g19/g19/g3/g37/g54/g38 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g48/g44/g49/g49/g50/g48 /g27 /g20/g17/g26/g24 /g19/g17/g24/g19 /g19/g17/g22/g19 /g20/g17/g19/g19 /g19/g17/g19/g24 /g48/g36/g59 /g46/g16/g19/g17/g21/g19 /g16 /g53/g40/g41/g29/g3/g53/g72/g73/g72/g85/g72/g81/g70/g72/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g15/g3/g88/g86/g88/g68/g79/g79/g92/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g15/g3/g73/g82/g85/g3/g76/g81/g73/g82/g85/g80/g68/g87/g76/g82/g81/g3/g83/g88/g85/g83/g82/g86/g72/g86/g3/g82/g81/g79/g92/g17 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g20/g17 /g22/g17 /g23/g17 /g49/g82/g87/g72/g86/g29 /g51/g76/g81/g3/g20/g3/g89/g76/g86/g88/g68/g79/g3/g76/g81/g71/g72/g91/g3/g73/g72/g68/g87/g88/g85/g72/g3/g80/g68/g92/g3/g89/g68/g85/g92/g15/g3/g69/g88/g87/g3/g80/g88/g86/g87/g3/g69/g72/g3/g79/g82/g70/g68/g87/g72/g71/g3/g90/g76/g87/g75/g76/g81/g3/g87/g75/g72/g3/g75/g68/g87/g70/g75/g72/g71/g3/g68/g85/g72/g68/g17 /g51/g68/g70/g78/g68/g74/g72/g3/g76/g86/g3/g86/g68/g90/g3/g86/g76/g81/g74/g88/g79/g68/g87/g72/g71 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48 /g55/g72/g85/g80/g76/g81/g68/g79/g16/g87/g82/g16/g40/g91/g83/g82/g86/g72/g71/g16/g51/g68/g71 /g27/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g39/g88/g68/g79/g3/g41/g79/g68/g87/g15/g3/g49/g82/g3/g47/g72/g68/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g48/g38/g12/g3/g16/g3/g21/g91/g22/g91/g20/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g39/g41/g49/g64 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g50/g89/g72/g85/g68/g79/g79/g3/g47/g72/g81/g74/g87/g75 /g40/g91/g83/g82/g86/g72/g71/g3/g51/g68/g71/g3/g47/g72/g81/g74/g87/g75 /g39 /g39/g21 /g20/g17/g22/g19 /g21/g17/g19/g19/g3/g37/g54/g38 /g16/g20 /g17 /g24 /g24 /g21/g17 /g51/g68/g70/g78/g68/g74/g72/g3/g80/g68/g92/g3/g75/g68/g89/g72/g3/g82/g81/g72/g3/g82/g85/g3/g80/g82/g85/g72/g3/g72/g91/g83/g82/g86/g72/g71/g3/g87/g76/g72/g3/g69/g68/g85/g86/g3/g68/g87/g3/g72/g81/g71/g86/g17

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 30  2007-2022 Microchip Technology Inc. and its subsidiaries /g53/g40/g38/g50/g48/g48/g40/g49/g39/g40/g39/g3/g47/g36/g49/g39/g3/g51/g36/g55/g55/g40/g53/g49 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g56/g81/g76/g87/g86 /g50/g83/g87/g76/g82/g81/g68/g79/g3/g38/g72/g81/g87/g72/g85/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75 /g50/g83/g87/g76/g82/g81/g68/g79/g3/g38/g72/g81/g87/g72/g85/g3/g51/g68/g71/g3/g47/g72/g81/g74/g87/g75 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g76/g87/g70/g75 /g60/g21 /g59/g21 /g20/g17/g26/g24 /g20/g17/g24/g24 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g19/g17/g24/g19/g3/g37/g54/g38 /g48/g44/g49 /g40 /g48/g36/g59 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g47/g72/g81/g74/g87/g75/g3/g11/g59/g27/g12 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75/g3/g11/g59/g27/g12 /g60/g20 /g59/g20 /g19/g17/g27/g24 /g19/g17/g22/g19 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g38/g19/g23/g16/g21/g20/g21/g22/g3/g53/g72/g89/g3/g40 /g49/g50/g48 /g27/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g39/g88/g68/g79/g3/g41/g79/g68/g87/g15/g3/g49/g82/g3/g47/g72/g68/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g48/g38/g12/g3/g16/g3/g21/g91/g22/g91/g20/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g39/g41/g49/g64 /g54/g44/g47/g46/g3/g54/g38/g53/g40/g40/g49 /g20/g21 /g27 /g38 /g40 /g59/g20 /g60/g20 /g42/g20 /g60/g21 /g59/g21 /g38/g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g54/g83/g68/g70/g76/g81/g74 /g22/g17/g19/g19 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g87/g82/g3/g38/g72/g81/g87/g72/g85/g3/g51/g68/g71/g3/g11/g59/g27/g12 /g42/g20 /g19/g17/g21/g19 /g55/g75/g72/g85/g80/g68/g79/g3/g57/g76/g68/g3/g39/g76/g68/g80/g72/g87/g72/g85 /g57 /g55/g75/g72/g85/g80/g68/g79/g3/g57/g76/g68/g3/g51/g76/g87/g70/g75 /g40/g57 /g19/g17/g22/g19 /g20/g17/g19/g19 /g145/g57 /g40/g57 /g40/g57 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g49/g82/g87/g72/g86/g29 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48 /g41/g82/g85/g3/g69/g72/g86/g87/g3/g86/g82/g79/g71/g72/g85/g76/g81/g74/g3/g85/g72/g86/g88/g79/g87/g86/g15/g3/g87/g75/g72/g85/g80/g68/g79/g3/g89/g76/g68/g86/g15/g3/g76/g73/g3/g88/g86/g72/g71/g15/g3/g86/g75/g82/g88/g79/g71/g3/g69/g72/g3/g73/g76/g79/g79/g72/g71/g3/g82/g85/g3/g87/g72/g81/g87/g72/g71/g3/g87/g82/g3/g68/g89/g82/g76/g71/g3/g86/g82/g79/g71/g72/g85/g3/g79/g82/g86/g86/g3/g71/g88/g85/g76/g81/g74 /g85/g72/g73/g79/g82/g90/g3/g83/g85/g82/g70/g72/g86/g86 /g20/g17 /g21/g17 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 31 24AA024/24LC024/24AA025/24LC025 BA 0.15 C 0.15 C

0.10 C A B

0.05 C (DATUM B) (DATUM A) C SEATING PLANE NOTE 1 N TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] D E A (A3) e 8X b L K With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 32  2007-2022 Microchip Technology Inc. and its subsidiaries Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: NOM MILLIMETERS

0.50 BSC

2.00 BSC

0.20 REF

1. Pin 1 visual index feature may vary, but must be located within the hatched area. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Contact-to-Exposed Pad Contact Thickness Exposed Pad Width Exposed Pad Length 4. Dimensioning and tolerancing per ASME Y14.5M 3. Package is saw singulated 2. Package may have one or more exposed tie bars at ends. Notes: Contact Width Overall Width Overall Length Contact Length Standoff Number of Pins Overall Height Pitch K 0.20 Units N e A Dimension Limits D b E L 0.20 1.35 1.25 0.25 0.00 0.70 MIN 0.25 0.30 1.30 1.40 1.35 0.30 0.45 1.45 0.75 0.02 0.05 0.80 MAX With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 33 24AA024/24LC024/24AA025/24LC025 RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Optional Center Pad Length Contact Pitch 1.50 1.60 MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) 0.85 0.25 Microchip Technology Drawing No. C04-129-MN Rev. B NOM 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] CContact Pad Spacing 2.90 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: C E EV EV ØV SILK SCREEN With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 34  2007-2022 Microchip Technology Inc. and its subsidiaries /g37 /g36 /g19/g17/g20/g24/g38/g36/g16/g37 /g19/g17/g20/g24/g38/g39 /g19/g17/g21/g19/g38/g36/g16/g37/g39 /g21/g59 /g55/g50/g51/g3/g57/g44/g40/g58 /g54/g44/g39/g40/g3/g57/g44/g40/g58 /g40/g49/g39/g3/g57/g44/g40/g58 /g19/g17/g20/g19/g38 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g3/g38/g19/g23/g16/g19/g21/g27/g39/g3/g11/g50/g55/g12/g3/g54/g75/g72/g72/g87/g3/g20/g3/g82/g73/g3/g21 /g21/g59 /g25/g59 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g25/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g54/g80/g68/g79/g79/g3/g50/g88/g87/g79/g76/g81/g72/g3/g55/g85/g68/g81/g86/g76/g86/g87/g82/g85/g3/g11/g50/g55/g15/g3/g50/g55/g60/g12/g3/g3/g62/g54/g50/g55/g16/g21/g22/g64 /g39 /g40/g40/g20 /g72 /g72/g20 /g40 /g21 /g40/g20 /g21 /g25/g59/g3/g69 /g39 /g36 /g36/g21 /g36/g20 /g300/g47 /g11/g47/g20/g12 /g53 /g53/g20 /g70 /g19/g17/g21/g19/g38/g36/g16/g37 /g21/g59 /g38 /g54/g40/g36/g55/g44/g49/g42/g3/g51/g47/g36/g49/g40

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 35 24AA024/24LC024/24AA025/24LC025 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g3/g38/g19/g23/g16/g19/g21/g27/g39/g3/g11/g50/g55/g12/g3/g54/g75/g72/g72/g87/g3/g21/g3/g82/g73/g3/g21 /g25/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g54/g80/g68/g79/g79/g3/g50/g88/g87/g79/g76/g81/g72/g3/g55/g85/g68/g81/g86/g76/g86/g87/g82/g85/g3/g11/g50/g55/g15/g3/g50/g55/g60/g12/g3/g3/g62/g54/g50/g55/g16/g21/g22/g64 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g83/g85/g82/g87/g85/g88/g86/g76/g82/g81/g86/g3/g86/g75/g68/g79/g79/g3/g81/g82/g87/g3/g72/g91/g70/g72/g72/g71/g3/g19/g17/g21/g24/g80/g80/g3/g83/g72/g85/g3/g86/g76/g71/g72/g17 /g20/g17 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g21/g17 /g49/g82/g87/g72/g86/g29 /g53/g40/g41/g29/g3/g3/g53/g72/g73/g72/g85/g72/g81/g70/g72/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g15/g3/g88/g86/g88/g68/g79/g79/g92/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g15/g3/g73/g82/g85/g3/g76/g81/g73/g82/g85/g80/g68/g87/g76/g82/g81/g3/g83/g88/g85/g83/g82/g86/g72/g86/g3/g82/g81/g79/g92/g17 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g86/g3/g39/g3/g68/g81/g71/g3/g40/g20/g3/g71/g82/g3/g81/g82/g87/g3/g76/g81/g70/g79/g88/g71/g72/g3/g80/g82/g79/g71/g3/g73/g79/g68/g86/g75/g3/g82/g85/g3/g83/g85/g82/g87/g85/g88/g86/g76/g82/g81/g86/g17/g3/g48/g82/g79/g71/g3/g73/g79/g68/g86/g75/g3/g82/g85 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48 /g41/g82/g82/g87/g3/g36/g81/g74/g79/g72 /g49/g88/g80/g69/g72/g85/g3/g82/g73/g3/g47/g72/g68/g71/g86 /g51/g76/g87/g70/g75 /g50/g88/g87/g86/g76/g71/g72/g3/g79/g72/g68/g71/g3/g83/g76/g87/g70/g75 /g50/g89/g72/g85/g68/g79/g79/g3/g43/g72/g76/g74/g75/g87 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g54/g87/g68/g81/g71/g82/g73/g73 /g50/g89/g72/g85/g68/g79/g79/g3/g58/g76/g71/g87/g75 /g48/g82/g79/g71/g72/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g58/g76/g71/g87/g75 /g50/g89/g72/g85/g68/g79/g79/g3/g47/g72/g81/g74/g87/g75 /g41/g82/g82/g87/g3/g47/g72/g81/g74/g87/g75 /g41/g82/g82/g87/g83/g85/g76/g81/g87 /g47/g72/g68/g71/g3/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g47/g72/g68/g71/g3/g58/g76/g71/g87/g75 /g47/g20 /g73 /g69 /g70 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g40 /g40/g20 /g39 /g47 /g72/g20 /g36 /g36/g21 /g36/g20 /g56/g81/g76/g87/g86 /g49 /g72 /g19/g131 /g19/g17/g19/g27 /g19/g17/g21/g19 /g16 /g16 /g16 /g20/g19/g131 /g19/g17/g21/g25 /g19/g17/g24/g20 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g19/g17/g28/g24/g3/g37/g54/g38 /g20/g17/g28/g19/g3/g37/g54/g38 /g19/g17/g22/g19 /g19/g17/g28/g19 /g19/g17/g27/g28 /g19/g17/g19/g19 /g19/g17/g25/g19/g3/g53/g40/g41 /g21/g17/g28/g19/g3/g37/g54/g38 /g19/g17/g23/g24 /g21/g17/g27/g19/g3/g37/g54/g38 /g20/g17/g25/g19/g3/g37/g54/g38 /g20/g17/g20/g24 /g16 /g16 /g48/g44/g49 /g25 /g49/g50/g48 /g20/g17/g23/g24 /g20/g17/g22/g19 /g19/g17/g20/g24 /g19/g17/g25/g19 /g48/g36/g59

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 36  2007-2022 Microchip Technology Inc. and its subsidiaries /g53/g40/g38/g50/g48/g48/g40/g49/g39/g40/g39/g3/g47/g36/g49/g39/g3/g51/g36/g55/g55/g40/g53/g49 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g49/g82/g17/g3/g38/g19/g23/g16/g21/g19/g21/g27/g39/g3/g11/g50/g55/g12 /g25/g16/g47/g72/g68/g71/g3/g51/g79/g68/g86/g87/g76/g70/g3/g54/g80/g68/g79/g79/g3/g50/g88/g87/g79/g76/g81/g72/g3/g55/g85/g68/g81/g86/g76/g86/g87/g82/g85/g3/g11/g50/g55/g15/g3/g50/g55/g60/g12/g3/g3/g62/g54/g50/g55/g16/g21/g22/g64 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g37/g54/g38/g29/g3/g37/g68/g86/g76/g70/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g17/g3/g55/g75/g72/g82/g85/g72/g87/g76/g70/g68/g79/g79/g92/g3/g72/g91/g68/g70/g87/g3/g89/g68/g79/g88/g72/g3/g86/g75/g82/g90/g81/g3/g90/g76/g87/g75/g82/g88/g87/g3/g87/g82/g79/g72/g85/g68/g81/g70/g72/g86/g17 /g49/g82/g87/g72/g86/g29 /g20/g17/g3/g39/g76/g80/g72/g81/g86/g76/g82/g81/g76/g81/g74/g3/g68/g81/g71/g3/g87/g82/g79/g72/g85/g68/g81/g70/g76/g81/g74/g3/g83/g72/g85/g3/g36/g54/g48/g40/g3/g60/g20/g23/g17/g24/g48 /g39/g76/g80/g72/g81/g86/g76/g82/g81/g3/g47/g76/g80/g76/g87/g86 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g47/g72/g81/g74/g87/g75/g3/g11/g59/g22/g12 /g50/g89/g72/g85/g68/g79/g79/g3/g58/g76/g71/g87/g75 /g39/g76/g86/g87/g68/g81/g70/g72/g3/g37/g72/g87/g90/g72/g72/g81/g3/g51/g68/g71/g86 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g58/g76/g71/g87/g75/g3/g11/g59/g22/g12 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g76/g87/g70/g75 /g38/g82/g81/g87/g68/g70/g87/g3/g51/g68/g71/g3/g54/g83/g68/g70/g76/g81/g74 /g22/g17/g28/g19 /g20/g17/g20/g19 /g42 /g61 /g60 /g20/g17/g26/g19 /g19/g17/g25/g19 /g48/g36/g59/g48/g44/g49 /g38 /g59 /g40 /g56/g81/g76/g87/g86 /g49/g50/g48 /g19/g17/g28/g24/g3/g37/g54/g38 /g21/g17/g27/g19 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g39/g76/g86/g87/g68/g81/g70/g72/g3/g37/g72/g87/g90/g72/g72/g81/g3/g51/g68/g71/g86 /g42/g59 /g19/g17/g22/g24 /g40 /g59 /g42/g59 /g60 /g42/g38/g61 /g54/g44/g47/g46/g3/g54/g38/g53/g40/g40/g49 /g42

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 37 24AA024/24LC024/24AA025/24LC025 APPENDIX A: REVISION HISTORY Revision Q (08/2022) Updated formatting to current template; Replaced ter- minology “Master” and “Slave” with “Host” and “Client” respectively. Updated Package Drawings. Revision P (04/2015) Corrected T BUF values; Corrected numbering of AC parameters; Updated Product Identification System. Revision N (10/2009) Added 6-lead SOT-23 Package; Revised Sections 5.0, 5.1 and 6.3. Revision M (10/2009) Added E-temp; Revised Section 1.0; Table 1-2; Figure 1-1; 1st Line Marking Codes table in Section 9.1; Product ID section. Revision L (04/2008) Replaced Package Drawings; Added TDFN package; Revised Product ID section. Revision K (03/2007) Replaced Package Drawings (Rev. AM). Revision J (02/2007) Revised Features section; Revised Pin Function Table; Changed 1.8V to 1.7V, Table 1-1 and Table 1-2; Replaced Package Drawings; Replaced On-line Support page; Revised Product ID section. Revision H Added DFN package. Revision G Added part number 24AA025 to document; Correction to Section 1.0, Ambient Temperature. Revision F Corrections to Section 1.0, Electrical Characteristics.

24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 38  2007-2022 Microchip Technology Inc. and its subsidiaries THE MICROCHIP WEBSITE Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com . Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sa les offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support

 2007-2022 Microchip Technology Inc. and its subsidiaries DS20001210Q-page 39 24AA024/24LC024/24AA025/24LC025 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: 24AA024 = 1.7V, 2-Kbit Addressable Serial EEPROM with WP pin. 24LC024 = 2.5V, 2-Kbit Addressable Serial EEPROM with WP pin. 24AA025 = 1.7V, 2-Kbit Addressable Serial EEPROM with no WP pin. 24LC025 = 2.5V, 2-Kbit Addressable Serial EEPROM with no WP pin. Tape and Reel Option: Blank = Standard packaging (tube or tray) T = Tape and Reel (1) Temperature Range: I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package: OT = Plastic Small Outline Transistor, 5-Lead (SOT-23) (Tape and Reel only) (24XX025 only) P = Plastic Dual In-Line – 300 mil Body, 8-Lead (PDIP) SN = Plastic Small Outline - Narrow, 3.90 mm Body, 8-Lead (SOIC) ST = Plastic Thin Shrink Small Outline – 4.4 mm, 8-Lead (TSSOP) MS = Plastic Micro Small Outline Package, 8-Lead (MSOP) MC = Plastic Dual Flat, No Lead Package – 2x3x1.0 mm Body, 8-Lead (DFN) MNY(2) = Plastic Dual Flat, No Lead Package – 2x3x0.75mm Body, 8-Lead (TDFN) (Tape and Reel only) Examples: a) 24AA024-I/P: Industrial Temperature, 1.7V, PDIP package. b) 24AA024-I/SN: Industrial Temperature, 1.7V, SOIC package. c) 24AA025T-I/ST: Tape and Reel, Industrial Temperature, 1.7V, TSSOP package. d) 24LC024-I/P: Industrial Temperature, 2.5V, PDIP package. e) 24LC024-E/MS: Extended Temperature, 2.5V, MSOP package. f) 24LC025T-I/OT: Tape and Reel, Industrial Temperature, 2.5V, SOT-23 package. PART NO. X /XX PackageTemperature Range Device [X] Tape and Reel Option Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Mi crochip Sales Office for package availability with the Tape and Reel option. 2: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish. (1)

DS20001210Q-page 40  2007-2022 Microchip Technology Inc. and its subsidiaries This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this informa- tion in any other manner violates these terms. Information regarding device applications is provided only for your conve- nience and may be superseded by updates. It is your responsi- bility to ensure t hat your applicatio n meets with your specifications. Contact your lo cal Microchip sales office for additional support or, obtai n additional support at https:// www.microchip.com/en-us/support/design-help/client-support- services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE , INCIDENTAL, OR CONSE- QUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applica- tions is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses ar e conveyed, implicitly or otherwise, under any Microchip intellectual pr operty rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In- Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2007-2022, Microchip Technology Incorporated and its subsidiar- ies. All Rights Reserved. ISBN: 978-1-6683-0935-3 Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure w hen used in the intended manner, within operating specifications, and under normal conditions.
• Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
• Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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