IR3876MPBF IRF | Alldatasheet
Document overview
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Technical content
Features
Input Voltage Range: 3V to 21V Output Voltage Range: 0.5V to 12V Continuous 12A Load Capability Constant On-Time control Excellent Efficiency at very low output current levels Compensation Loop not Required Programmable switching frequency, soft start, and over current protection Power Good Output Precision Voltage Reference (0.5V, +/-1%) Pre-bias Start Up Under/Over Voltage Fault Protection Ultra small, low profile 5mm x 6mm QFN Package
Applications
Notebook and desktop computers Game consoles Consumer electronics – STB, LCD, TV, printers General purpose POL DC-DC converters
Description
The IR3876 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC voltage regulator. The onboard constant on time hysteretic controller and MOSFETs make IR3876 a space-efficient solution that delivers up to 12A of precisely controlled output voltage in 60oC ambient temperature applications without airflow. Programmable switching frequency, soft start, and over current protection allows for a very flexible solution suitable for many different applications and an ideal choice for battery powered applications. Additional features include pre-bias startup, very precise 0.5V reference, over/under voltage shut down, power good output, and enable input with voltage monitoring capability. 12A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR SupIRBuck TM IR3876 BOOT PHASE VCC FF SS EN GND ISET PGND VIN RFF CBOOT CSS (4.5V-7.5V) VIN 3VCBP PGOOD FB RISET VOUT (3V-21V) (0.5V-12V)L CLDO PD-97763
(Voltages referenced to GND unless otherwise specified) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. W/C2θ W/C35θ o PCBJ o JA
PACKAGE INFORMATION
ORDERING INFORMATION
x0.8 Zcross VCC FF x1.2 UV# SSDelay Run Run 3VCBP VCC VCC SETSS FB PGOOD VCC BOOT PHASE PGND FF VIN ISET GND EN GND PWM COMP VBG LDO GND VCC 3VCBP 3VCBP OVER CURRENT DCM OC#
ISET 2 Connecting resistor to PHASE pin sets over current trip point PGOOD 3 5V Power good – pull up to 3.3V GND 4,17 Reference Bias return and signal reference FB 5 3.3V Inverting input to PWM comparator, OVP / PGood sense SS 6 3.3V Set soft start slew-rate with a capacitor to GND NC 7 ----- No connection 3VCBP 8 3.3V LDO output. A minimum of 1.0 µF ceramic capacitor is required NC 9 ----- No connection VCC 10 5V Gate drive supply PGND 11 Reference Power return PHASE 12 VIN Phase node (or switching node) of MOSFET half bridge VIN 13 VIN Input voltage for the system. BOOT 14 VIN +VCC Bootstrapped gate drive supply – connect a capacitor to PHASE FF 15 VIN Input voltage feed forward – sets on-time with a resistor to VIN EN 16 5V Enable
Recommended Operating Conditions Electrical Specifications Unless otherwise specified, these specification apply over VIN = 12V, VCC = 5V, 0oC ≤ TJ ≤ 125oC. * Note: PHASE pin must not exceed 25V. Symbol Definition Min Max Unit VIN Input Voltage 3 21* V VCC Supply Voltage 4.5 7.5 VOUT Output Voltage 0.5 12 IOUT Output Current 0 12 A Fs Switching Frequency N/A 1000 kHz TJ Junction Temperature 0 125 oC PARAMETER NOTE TEST CONDITION MIN TYP MAX UNIT BIAS SUPPLIES VCC Turn-on Threshold 3.9 4.2 4.5 V VCC Turn-off Threshold 3.6 3.9 4.2 V VCC Threshold Hysteresis 150 mV VCC Operating Current RFF = 200K, EN = HIGH, Fs = 300kHz 9.2 mA VCC Shutdown Current EN = LOW 35 50 µA FF Shutdown Current EN = LOW 2 µA VIN Shutdown Current EN = LOW 1 µA INTERNAL LDO OUTPUT LDO Output Voltage Range CLDO = 1µF 3.1 3.3 3.5 V Output Current 8 mA CONTROL LOOP Reference Accuracy, VREF VREF 0.495 0.5 0.505 V On-Time Accuracy RFF = 180K, TJ = 65oC 280 300 320 ns Min Off Time 1 400 ns Soft-Start Current EN = HIGH 8 10 12 µA Zero Current Threshold 1 Measure at VPHASE -5 -2.4 0 mV FAULT PROTECTION ISET Pin Output Current 18 20 22 µA Under Voltage Threshold Falling VFB & Monitor PGOOD 0.37 0.4 0.43 V Under Voltage Hysteresis 1 Rising VFB 10 mV Over Voltage Threshold Rising VFB & Monitor PGOOD 0.58 0.62 0.66 V Over Voltage Hysteresis 1 Falling VFB 10 mV PGOOD Delay Threshold (VSS) 1 V
Electrical Specifications (continued) Unless otherwise specified, these specification apply over VIN = 12V, VCC = 5V, 0oC ≤ TJ ≤ 125oC. Note 1: Guaranteed by design, not tested in production Note 2: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3 for Consumer Market. PARAMETER NOTE TEST CONDITION MIN TYP MAX UNIT GATE DRIVE Dead Time 1 Monitor body diode conduction on PHASE pin 5 30 ns BOOTSTRAP PFET Forward Voltage I(BOOT) = 10mA 100 200 300 mV UPPER MOSFET Static Drain-to-Source On- Resistance VCC = 5V, ID = 12A, TJ = 25oC 7 12 16 mΩ LOWER MOSFET Static Drain-to-Source On- Resistance VCC = 5V, ID = 12A, TJ = 25oC 4 5.3 7 mΩ LOGIC INPUT AND OUTPUT EN High Logic Level 2 - - V EN Low Logic Level - - 0.6 V EN Input Current EN = 3.3V 11 µA PGOOD Pull Down Resistance 25 50 Ω
Figure 7. Typical Application Circuit for VOUT = 1.05V, Fs = 300kHz
1 C2 22uF CAP,22uF,25V,CERAMIC,X5R,1210 Panasonic ECJ-4YB1E226M
1 C3 68uF CAP,68uF,25V,ELECT,FK,SMD Panasonic EEV-FK1E680P
1 R9 0 RES,0Ω,1/10W,1%,0603,SMD Vishay/Dale CRCW06030000Z0EAHP
1 R3 200K RES,200kΩ,1/10W,1%,0603,SMD Vishay/Dale CRCW0603200KFKEA
1 SW1 SPST SWITCH, DIP, SPST, SMT C&K Components SD02H0SK
1 U1 IR3876 5mm x 6mm QFN IR IR3876MPBF
reference (Vref) or the soft start (SS) voltage. RUN signal when all conditions are met. either pin drops below the falling thresholds. Electrical Specification), SS_DELAY goes HIGH. startup sequence is shown in Figure 17. Figure 17. Normal Startup disturbances of the output voltage. pulling the EN pin below its lower threshold. pulling the soft start pin below 0.3V.
Constant-on-time control is a fast , ripple based control scheme. Unstable operation can occur if certain conditions are not met. The system instability is usually caused by:
- Switching noise coupled to FB input. This causes the PWM comparator to trigger prematurely after the 400ns minimum Q2 on- time. It will result in double or multiple pulses every switching cycle instead of the expected single pulse. Double pulsing can causes higher output voltage ripple, but in most application it will not affect operation. This can usually be prevented by careful layout of the ground plane and the FB sensing trace.
- Steady state ripple on FB pin being too small. The PWM comparator in IR3876 requires minimum 7mVp-p ripple voltage to operate stably. Not enough ripple will result in similar double pulsing issue described above. Solving this may require using output capacitors with higher ESR.
- ESR loop instability. The stability criteria of constant on-time is: ESR*Cout>Ton/2. If ESR is too small that this criteria is violated then sub-harmonic oscillation will occur. This is similar to the instability problem of peak- current-mode control with D>0.5. Increasing ESR is the most effective way to stabilize the system, but the price paid is the larger output voltage ripple.
- For applications with all ceramic output capacitors, the ESR is usually too small to meet the stability criteria. In these applications, external slope compensation is necessary to make the loop stable. The ramp injection circuit, composed of R6, C13, and C14, shown in Figure 7 is required. The inductor current ripple sensed by R6 and C13 is AC coupled to the FB pin through C14. C14 is usually chosen between 1 to 10nF, and C13 between 10 to 100nF. R6 should then be chosen such that L/DCR = C13*R6. GATE DRIVE LOGIC The gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval. An adaptive dead time prevents the simultaneous conduction of the upper and lower MOSFETs. The lower gate voltage (LGATE) must be below approximately 1V after PWM goes HIGH before the upper MOSFET can be gated on. Also, the upper gate voltage (UGATE), the difference voltage between UGATE and PHASE, must be below approximately 1V after PWM goes LOW before the lower MOSFET can be gated on. The control MOSFET is gated on after the adaptive delay for PWM = HIGH and the synchronous MOSFET is gated on after the adaptive delay for PWM = LOW. The lower MOSFET is driven ‘off’ when the signal ZCROSS indicates that the inductor current has reversed as detected by the PHASE voltage crossing the zero current threshold. The synchronous MOSFET stays ‘off’ until the next PWM falling edge. When the lower peak of inductor current is above zero, a forced continuous current condition is selected. The control MOSFET is gated on after the adaptive delay for PWM = HIGH, and the synchronous MOSFET is gated on after the adaptive delay for PWM = LOW. The synchronous MOSFET gate is driven on for a minimum duration. This minimum duration allows time to recharge the bootstrap capacitor and allows the current monitor to sample the PHASE voltage.
Figure 20. Typical Input Current Waveform. guide one through the process. node. The typical percentage is 25%. inductance. ΔI is defined as shown in Figure 20.
Design Criteria: Input Voltage, VIN, = 7V to 16V Output Voltage, VOUT = 1.05V Switching Frequency, Fs = 300KHz Inductor Ripple Current, 2ΔI = 3A Maximum Output Current, IOUT = 12A Over Current Trip, IOC = 18A Overshoot Allowance, VOS = VOUT + 50mV Undershoot Allowance, VDROP = 50mV Choose an input capacitor: Find RFF : Choose an inductor with the lowest DCR and AC power loss as possible to increase the overall system efficiency. For instance, choose MPL1055-1R21R manufactured by Delta. The inductance of this part is 1.2µH and has 2.9mΩ DCR. Ripple current needs to be recalculated using the chosen inductor. A A A V VA 3.1 36.1 1116 1.0521I IN_RMS A Panasonic 10µF (ECJ3YB1E106M) accommodates 6 Arms of ripple current at 300KHz. Due to the chemistry of multilayer ceramic capacitors, the capacitance varies over temperature and operating voltage, both AC and DC. One 10µF capacitor is recommended. In a practical solution, one 1µF capacitor is required along with the 10µF. The purpose of the 1µF capacitor is to suppress the switching noise and deliver high frequency current. Choose an output capacitor: To meet the undershoot specification, select a set of output capacitors which has an equivalent ESR of 10mΩ (50mV/5A). To meet the overshoot specification, equation 7 will be used to calculate the minimum output capacitance. As a result, 300µF will be needed for 5A load removal. Combine those two requirements, one can choose a set of output capacitors from manufactures such as Sanyo or Rubycon. A 330µF (2SWZ330M R05) from Rubycon is recommended. This capacitor has 4.5mΩ ESR which leaves margin for the voltage drop of the ESL during load step up. k 175 300k201 V Pick a standard value 178 kΩ, 1% resistor. Find RSET : k 6.55 20 18 m2.51.4R SET A A H HzAV VVV 1.1 300k361 1.05-611.05 FΔI2V VVVL sIN OUTINOUT AHzHV VVV 1.36 300k2.1612 1.05-611.05ΔI The RDSON of the lower MOSFET could be expected to increase by a factor of 1.4 over temperature. Therefore, pick a 6.65kΩ, 1% standard resistor. Find a resistive voltage divider for VOUT = 1.05V: Choose the soft start capacitor: Once the soft start time has chosen, such as 1000us to reach to the reference voltage, a 22nF for CSS is used to meet 1000µs. Choose an inductor to meet the design specification: V0.5 V RR RV OUT FB R2 = 2.55kΩ, R1 = 2.80kΩ, both 1% standard resistors.
PCB Metal and Components Placement Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large toe fillet that can be easily inspected. Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment. Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste.
MIN MAX MIN MAX MIN MAX MIN MAX c P 3.242 3.342 0.1276 0.1316 D Q 1.265 1.365 0.0498 0.05374 E R 2.644 2.744 0.1042 0.1081 e S 1.5 1.6 0.0591 0.063 e1 t1, t2, t3 e2 t4 DIM MILIMITERS INCHES DIM MILIMITERS INCHES 0.203 REF. 0.008 REF. 5.000 BASIC 1.970 BASIC 6.000 BASIC 2.364 BASIC 1.033 BASIC 0.0407 BASIC 0.650 BASIC 0.0256 BASIC 0.852 BASIC 0.0259 BASIC 1.153 BASIC 0.045 BASIC 0.727 BASIC 0.0286 BASIC 0.401 BASIC 0.016 BACIS IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial Market (Note 2) Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 5/2012