EEC1005

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 2020 Microchip Technology Inc. DS00003392B-page 1

• Complete Universal Storage Backplane Manage- ment Processor - SFF-TA-1005 Universal Backplane Manage- ment (UBM) over I2C - Provides SFF-8654 compliant Host Facing Connector (HFC) communication support over I2C - HFC connection responds to all standard UBM commands from the host - Integrates the UBM FRU non-volatile mem- ory on the UBM FRU I2C Address - Provides SFF-8639 compliant U.2 Drive Fac- ing Connector (DFC) Support - Provides SFF-TA-1001 compliant U.3 Drive Facing Connector (DFC) Support - Support for SES over UBM
• Supports I2C communication to Baseboard Man- agement Controller
• Up to 8 I2C ports for UBM and BMC host inter- faces
• SFF-8485 Support - Implements up to 4 Hardware Accelerated SGPIO Legacy Interfaces for SAS/SATA backplane implementations
• Secure Boot - EEC1005 code is authenticated by a secure boot loader prior to loading from internal flash - Hardware accelerated crypto blocks provide fast secure boot - Secure Firmware update - Key revocation
• Supports Storage LED Management as per SFF-

8489 IBPI specifications by default

• Custom LED patterns can be configured
• Scalable Solution for up to 16 Hard Drives on a Single Device - SGPIO Host Interfaces support up to 16 drives (SAS/SATA drive types) - UBM Host Interfaces support up to 12 drives (NVMe drive types) - Up to 6 HFCs
• Supports multiple backplanes on a single chassis
• Support for NVME Hot plug and Power Disable for drives
• Integrated NV Memory for: - UBM FRU (Field Replaceable Unit) for every HFC - General Purpose FRU - NV Configuration Memory
• Configurable Interfaces using a single analog configuration pin - Host interface (SGPIO vs UBM) - Number of HFCs and Drive Facing Connec- tors (DFCs) - Other supported features
• Monitors system PERST - One pin per DFC for PERST support
• Monitors for drive insertion from IFDET and PRSNT signals - IFDET2 support (for SFF-TA-1001)
• Package Options - 144 pin WFBGA RoHS Compliant package - 84 pin WFBGA RoHS Compliant package EEC1005 Enterprise Storage Backplane Management Processor

DS00003392B-page 2  2020 Microchip Technology Inc. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the be st documentation possible to ensur e successful use of your Micr o- chip products. To this end, we will continue to improve our pub lications to better suit your needs. Our publications will be r efined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. As device/documentat ion issues become known to us , we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

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 2020 Microchip Technology Inc. DS00003392B-page 3 EEC1005 Table of Contents

DS00003392B-page 4  2020 Microchip Technology Inc.

1.0 GENERAL DESCRIPTION

EEC1005 is a generic, easily configurable, True Universal Backplane Management (UBM) device that can be used on hard drive backplanes to provide complete storage enclosure man agement and reporting to computing host systems using industry standard communication protocols. EEC1005 supports a variety of host interfaces to accommodate SA S/SATS/NVMe backplane. The SFF-8654 slimline connector (Host facing Connector) can be used to route SAS sign als in which case the HBA will manage SAS/SATA drives, the same connector protocol (physically a different connector) can be used to route PCIe signals in which case the HBA will manage NVME drives. In both cases UBM will be used as management protocol with support of SGPIO as well on SAS Slimline (Configuration dependent).The device su pports using U.2 and U.3 Drive facing Connectors. EEC1005 also supports Multiple Backplanes on a single chassis. EEC1005 supports 2 or 3 LED IBPI blinking patterns for up to 16 drives. Customized LED blink pattern can also be pro- grammed through the FRU. The EEC1005 has a secure boot loader that authenticates and decrypts the Flash boot image (UBM application) using the AES-256, ECDSA P-256, SHA-256 cryptographic hardware accelerators. EEC1005 hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and EC_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Additionally, the device offers lockable OTP storage for private keys and IDs. EEC1005 is available in 84 pin and 144 pin WFBGA packages.

1.1 References

1. SFF-TA-1005 Universal Backplane Management Specification 2. SFF-8485 Serial General-Purpose Input/output (SGPIO) Specification 3. SFF-8448 SAS Sideband Signal Assignment 4. SFF-8489 Serial GPIO (Internatio nal Blinking Pattern Interpretation) 5. Enterprise SSD Form Factor Version 1.0a 6. SFF-TA-1001 (U.3 Drive Connector) Specification 7. SFF-8639 (U.2 Drive Connector) Specification 8. SFF-9639 (U.2 Connector Pinout) Specification 9. SFF-8654 Slimline Connector Specification 10. SFF-9402 Multi-Protocol Internal Cables for SAS and/or PCIe (Slimline Connector Pinout) Specification 11. SCSI Enclosure Services -4 Specification

 2020 Microchip Technology Inc. DS00003392B-page 5 EEC1005

2.0 UBM BACKPLA NE ARCHITECTURE

EEC1005 on the back plane communicates to the Host through SGPIO or I2C interface over the Host facing Connector (Host attach configuration) or dedicated cable (Direct attach c onfiguration). It detects hard drive being installed in the backplane and notifies the host of the insertion/removal/failure of the drive. It also blinks Leds for each hard drive’s sta- tus as explained in Section 8.0, "LED Specifications". There are different types of Backplanes based on: 1. Number of drives the back plane supports 2. Type of host communication (For eg. I2C or SGPIO) 3. Type of Drive slots (For eg. U.2 or U.3) The different configurations of the backplane that EEC1005 supports is covered in Section 3.0, "Configurations".

2.1 Direct Attach UBM Backplane

A direct attach configuration is enabled when user connects the backplane directly to mother board and the drives are not managed by an HBA. In this case the drives are managed either by BMC or PCIe Switch/Expander for switch-based configurations.EEC1005 can be used in Direct attach configurations using UBM as the management protocol from BMC (BMC Emulation) or Switch/Expander. EEC1005 based backplane architectures are capable of supporting Y-cable configurations where the PCIe lanes from a single Host HFC will be split into 2x backplane HFC’s, this allows splitting on PCIe clocks using clock buffers as shown in the following diagram.

DS00003392B-page 6  2020 Microchip Technology Inc.

2.2 Host Attach UBM Backplane

A Host attach configuration is enabled when user connects the backplane directly to SMARTROC/HBA and the drives are managed by an HBA. EEC1005 can be used in Host attach configuration as in FIGURE 2-2: “Host Attach Configu- ration”. Each HFC is connected to a Host through a cable to communicate with EEC1005. EEC1005 based backplane architecture supports NVME PERST functionality by allowing the Host to directly control the PERST signal. This allows the Host to directly control the reset behavior of NVME drive without adding any latency. The PERST signal will be driven from HFC and then split into 2 signals to control 2 drives from a single signal. FIGURE 2-1: DIRECT ATTACH CONFIGURATION Note: The hardware bifurcation of the PCIe lanes is application dependent. Usually each HFC bifurcates x8 lanes into two x4 connections. CPU ChipSet BMC BMC EEC1005 IFDET,PRSNT,PERST X4 High Speed transmit & Receive PCIe lanes PCIe Clock PCIe PCIe UBM I2C BMC I2C HFC(SFF‐8654) SFF‐8639/9639 U.2 SFF‐8639/9639 U.2 IFDET,PRSNT,PERST X4 High Speed transmit & Receive PCIe lanes X4 High Speed transmit & Receive PCIe lanes X4 High Speed transmit & Receive PCIe lanes PCIe PCIe Clock PCIe Clock SideBand Signals UBM I2C BMC I2C Clock Buffer

 2020 Microchip Technology Inc. DS00003392B-page 7 EEC1005 FIGURE 2-2: HOST ATTACH CONFIGURATION NVMe/SAS/ SATA Drive 1 Drive 8 High Speed Serial High Speed Serial HFC DFC DFC UBM1 I2C UBM4 I2C HFC HFC 1 HFC 4 UBM4 Change Detect UBM1 Sideband UBM4 Sideband Drive 1 IFDET# Drive 1 PERST0# Drive 1 PRSNT# Drive 1 IFDET2# (Optional) Drive 8 IFDET# Drive 8 PERST0# Drive 8 PRSNT# Drive 8 IFDET2# (Optional) LED Online/Green Fault/Amber Drive 1 Online LED Drive 1 Fault LED LED Online/Green Fault/Amber Drive 8 Online LED Drive 8 Fault LED UBM 4 Controller FRU UBM 1 Controller FRU BMC I2C+ Backplane FRU BMC I2C Drive 1 Drive 8 EEC1005 Host System OS & Driver BMC 3x SGPIO Host 3x SGPIO Device ROC/HBA NVMe/SAS/ SATA ROC/HBA UBM1 Change Detect DFC 8 LED DFC 1 LED High Speed Serial

DS00003392B-page 8  2020 Microchip Technology Inc.

3.0 CONFIGURATIONS

Multiple Backplane architectures are supported using EEC1005 th at are configured by firmware based on an analog value sampled at one of EEC1005 i nput ADC pin (Config Pin) at s tartup. Table 3-1, “EEC1005 Configuration Select” provides the complete list of Configurations selectable based on the analog value on CONFIG_PIN. The analog value can be set by a resistor divider network as in Figure 3-1, the values of the resistors are user defined.The configuration is fixed for a Backplane and is not runtime modified. The recom mendations on the resistor values are provided in Table 3-2, “Recommended Resistor Values,” on page 9. TABLE 3-1: EEC1005 CONFIGURATION SELECT EEC1005 Configa a. Configurations not mentioned in the above table are not supported by EEC1005. Pin Count ID Config (V) Pinout HFC Totalb b. HFC Total is the number of host facing connectors required for a particular configuration. HFC - SAS HFC - PCIe DFC Total DFC SAS/ SATA DFC PCIe 4 Drive SGPIO 84 01 0.1 Table 10-3, “SGPIO Con- troller - 84 Pin Package” 110 44 0 8 Drive SGPIO 84 02 0.2 Table 10-3, “SGPIO Con- troller - 84 Pin Package” 110 88 0 12 Drive SPGIO 144 03 0.3 Table 10-1, “SGPIO Con- troller - 144 Pin Package” 2 2 0 12 12 0 16 Drive SPGIO 144 04 0.4 Table 10-1, “SGPIO Con- troller - 144 Pin Package” 2 2 0 16 16 0

4 Drive UBM

U.2 84 05 0.5 Table 10-4, “UBM Con- troller - 84 Pin Package” 312 44 4

8 Drive UBM

U.2 84 06 0.6 Table 10-4, “UBM Con- troller - 84 Pin Package” 514 88 8 U.2 (Full Fea- ture) 144 07 0.7 Table 10-2, “UBM Con- troller - 144 Pin Package” 514 88 8 U.3 (Minimum Feature) 84 08 0.8 Table 10-4, “UBM Con- troller - 84 Pin Package” 444 88 8 U.3 (Full Fea- ture) 144 09 0.9 Table 10-2, “UBM Con- troller - 144 Pin Package” 444 88 8

12 Drive UBM

U.2 PCIe Only (Full Featured) 144 0A 1.0 Table 10-2, “UBM Con- troller - 144 Pin Package” 606 1 2 0 1 2 U.3 PCIe Only (Full Featured) 144 0B 1.1 Table 10-2, “UBM Con- troller - 144 Pin Package” 606 1 2 0 1 2

8 Drive

U.2 144 0D 1.3 Table 10-5, “UBM_SGPIO Controller - 144 Pin Package” 514 88 8

 2020 Microchip Technology Inc. DS00003392B-page 9 EEC1005 FIGURE 3-1: VOLTAGE DIVIDER AT ADC INPUT TABLE 3-2: RECOMMENDED RESISTOR VALUES EEC1005 Config Config (V) Pino ut R2 (in Ohms) R3(in Ohms) 4 Drive SGPIO 0.1 Table 10-3, “SGPIO Controller - 84 Pin Package” 301 11.5 8 Drive SGPIO 0.2 Table 10-3, “SGPIO Controller - 84 Pin Package” 634 11 12 Drive SPGIO 0.3 Table 10-1, “SGPIO Controller - 144 Pin Package” 1000 0 16 Drive SPGIO 0.4 Table 10-1, “SGPIO Controller - 144 Pin Package” 1370 9.31 4 Drive UBM U.2 0.5 Table 10-4, “UBM Controller - 84 Pin Package” 1780 5.76 8 Drive UBM U.2 0.6 Table 10-4, “UBM Controller - 84 Pin Package” 2210 12.1 8 Drive UBM U.2 (Full Feature)

0.7 Table 10-2, “UBM

Package” 2670 40.2 R1 = 10K VCC = 3.3V C = 0.1uf To ADC input (CFG Pin)

DS00003392B-page 10  2020 Microchip Technology Inc. 8 Drive UBM U.3 (Minimum Feature)

0.8 Table 10-4, “UBM

Package” 3160 40.2 8 Drive UBM U.3 (Full Feature)

0.9 Table 10-2, “UBM

Package” 3740 10 12 Drive UBM U.2 PCIe Only (Full Fea- tured)

1.0 Table 10-2, “UBM

Package” 4320 28 12 Drive UBM U.3 PCIe Only (Full Fea- tured)

1.1 Table 10-2, “UBM

Package” 4990 10

8 Drive UBM+SGPIO

U.2

1.3 Table 10-5,

“UBM_SGPIO Con- troller - 144 Pin Pack- age” 5490 1000 Note 1: The resistor values suggested are based on the standard value resistors available @1% tolerance. 2: It is highly recommended to use 1% tolerant resistors at ADC input. 3: The ADC input capacitor should be 0.1uF. 4: The resistor R1 should be fixed at 10K. 5: The Config values not mentioned in the above table is not supported by EEC1005. TABLE 3-2: RECOMMENDED RESISTOR VALUES (CONTINUED) EEC1005 Config Config (V) Pino ut R2 (in Ohms) R3(in Ohms)

 2020 Microchip Technology Inc. DS00003392B-page 11 EEC1005

4.0 CONFIGURATION FRU

EEC1005 supports a 256-byte FRU (Field Replaceable Unit) that i s used to initialize/input the parameters which are client specific. These parameters are read on power up as well as run time to initialize the firmware accordingly. This 256-byte FRU is accessible over BMC I2C segment, if used in an architecture where BMC exists. TABLE 4-1: CONFIGURATION FRU TABLE Address Group Field Name Pattern LED Name Parameters 0x00 Global ACTIVITY/2WIRE_RESET OPTION 0x01 Global IBPI PATTERN 2/3 LED 0x02 Global Backplane HFC Count 0x03 Global Backplane DFC Count 0x04 Global Backplane Physical Location 0x05 Global RSVD 0x06 Global RSVD 0x07 Global RSVD 0x08 Global RSVD 0x09 Global RSVD 0x0A Global RSVD 0x0B Global RSVD 0x0C Global RSVD 0x0D Global RSVD 0x0E Global RSVD 0x0F Global RSVD 0x10 Global RSVD 0x11 Global RSVD 0x12 Global RSVD 0x13 Global RSVD 0x14 Global CHECKSUM 0x15 HFC0 UBM CONTROLL ER DEVICE CODE MSB 0x16 HFC0 UBM CONTRO LLER DEVICE CODE 0x17 HFC0 UBM CONTRO LLER DEVICE CODE 0x18 HFC0 UBM CONTROLLER DEVICE CODE LSB 0x19 HFC0 SILICON VENDOR ID VENDOR SPECIFIC 0x1A HFC0 SILICON VENDOR ID VENDOR SPECIFIC 0x1B HFC0 HFC IDENTITY 0x1C HFC0 CPRSNT# or CHANGE_DETECT# 0x1D HFC0 RSVD 0x1E HFC0 RSVD 0x1F HFC0 RSVD 0x20 HFC0 RSVD 0x21 HFC0 RSVD 0x22 HFC0 RSVD 0x23 HFC0 RSVD 0x24 HFC0 RSVD 0x25 HFC0 RSVD

DS00003392B-page 12  2020 Microchip Technology Inc. 0x26 HFC0 RSVD 0x27 HFC0 RSVD 0x28 HFC0 RSVD 0x29 HFC0 RSVD 0x2A HFC0 RSVD 0x2B HFC0 RSVD 0x2C HFC0 CHECKSUM 0x2D HFC1 UBM CONTROLL ER DEVICE CODE MSB 0x2E HFC1 UBM CONTRO LLER DEVICE CODE 0x2F HFC1 UBM CONTRO LLER DEVICE CODE 0x30 HFC1 UBM CONTROLLER DEVICE CODE LSB 0x31 HFC1 SILICON VENDOR ID VENDOR SPECIFIC 0x32 HFC1 SILICON VENDOR ID VENDOR SPECIFIC 0x33 HFC1 HFC IDENTITY 0x34 HFC1 CPRSNT# or CHANGE_DETECT# 0x35 HFC1 RSVD 0x36 HFC1 RSVD 0x37 HFC1 RSVD 0x38 HFC1 RSVD 0x39 HFC1 RSVD 0x3A HFC1 RSVD 0x3B HFC1 RSVD 0x3C HFC1 RSVD 0x3D HFC1 RSVD 0x3E HFC1 RSVD 0x3F HFC1 RSVD 0x40 HFC1 RSVD 0x41 HFC1 RSVD 0x42 HFC1 RSVD 0x43 HFC1 RSVD 0x44 HFC1 CHECKSUM 0x45 HFC2 UBM CONTROLL ER DEVICE CODE MSB 0x46 HFC2 UBM CONTRO LLER DEVICE CODE 0x47 HFC2 UBM CONTRO LLER DEVICE CODE 0x48 HFC2 UBM CONTROLLER DEVICE CODE LSB 0x49 HFC2 SILICON VENDOR ID VENDOR SPECIFIC 0x4A HFC2 SILICON VENDOR ID VENDOR SPECIFIC 0x4B HFC2 HFC IDENTITY 0x4C HFC2 CPRSNT# or CHANGE_DETECT# 0x4D HFC2 RSVD 0x4E HFC2 RSVD TABLE 4-1: CONFIGURATION FRU TABLE (CONTINUED) Address Group Field Name Pattern LED Name Parameters

 2020 Microchip Technology Inc. DS00003392B-page 13 EEC1005 0x4F HFC2 RSVD 0x50 HFC2 RSVD 0x51 HFC2 RSVD 0x52 HFC2 RSVD 0x53 HFC2 RSVD 0x54 HFC2 RSVD 0x55 HFC2 RSVD 0x56 HFC2 RSVD 0x57 HFC2 RSVD 0x58 HFC2 RSVD 0x59 HFC2 RSVD 0x5A HFC2 RSVD 0x5B HFC2 RSVD 0x5C HFC2 CHECKSUM 0x5D HFC3 UBM CONTROLL ER DEVICE CODE MSB 0x5E HFC3 UBM CONTRO LLER DEVICE CODE 0x5F HFC3 UBM CONTRO LLER DEVICE CODE 0x60 HFC3 UBM CONTROLLER DEVICE CODE LSB 0x61 HFC3 SILICON VENDOR ID VENDOR SPECIFIC 0x62 HFC3 SILICON VENDOR ID VENDOR SPECIFIC 0x63 HFC3 HFC IDENTITY 0x64 HFC3 CPRSNT# or CHANGE_DETECT# 0x65 HFC3 RSVD 0x66 HFC3 RSVD 0x67 HFC3 RSVD 0x68 HFC3 RSVD 0x69 HFC3 RSVD 0x6A HFC3 RSVD 0x6B HFC3 RSVD 0x6C HFC3 RSVD 0x6D HFC3 RSVD 0x6E HFC3 RSVD 0x6F HFC3 RSVD 0x70 HFC3 RSVD 0x71 HFC3 RSVD 0x72 HFC3 RSVD 0x73 HFC3 RSVD 0x74 HFC3 CHECKSUM 0x75 HFC4 UBM CONTROLL ER DEVICE CODE MSB 0x76 HFC4 UBM CONTRO LLER DEVICE CODE 0x77 HFC4 UBM CONTRO LLER DEVICE CODE 0x78 HFC4 UBM CONTROLLER DEVICE CODE LSB TABLE 4-1: CONFIGURATION FRU TABLE (CONTINUED) Address Group Field Name Pattern LED Name Parameters

DS00003392B-page 14  2020 Microchip Technology Inc. 0x79 HFC4 SILICON VENDOR ID VENDOR SPECIFIC 0x7A HFC4 SILICON VENDOR ID VENDOR SPECIFIC 0x7B HFC4 HFC IDENTITY 0x7C HFC4 CPRSNT# or CHANGE_DETECT# 0x7D HFC4 RSVD 0x7E HFC4 RSVD 0x7F HFC4 RSVD 0x80 HFC4 RSVD 0x81 HFC4 RSVD 0x82 HFC4 RSVD 0x83 HFC4 RSVD 0x84 HFC4 RSVD 0x85 HFC4 RSVD 0x86 HFC4 RSVD 0x87 HFC4 RSVD 0x88 HFC4 RSVD 0x89 HFC4 RSVD 0x8A HFC4 RSVD 0x8B HFC4 RSVD 0x8C HFC4 CHECKSUM 0x8D HFC5 UBM CONTROLL ER DEVICE CODE MSB 0x8E HFC5 UBM CONTRO LLER DEVICE CODE 0x8F HFC5 UBM CONTRO LLER DEVICE CODE 0x90 HFC5 UBM CONTROLLER DEVICE CODE LSB 0x91 HFC5 SILICON VENDOR ID VENDOR SPECIFIC 0x92 HFC5 SILICON VENDOR ID VENDOR SPECIFIC 0x93 HFC5 HFC IDENTITY 0x94 HFC5 CPRSNT# or CHANGE_DETECT# 0x95 HFC5 RSVD 0x96 HFC5 RSVD 0x97 HFC5 RSVD 0x98 HFC5 RSVD 0x99 HFC5 RSVD 0x9A HFC5 RSVD 0x9B HFC5 RSVD 0x9C HFC5 RSVD 0x9D HFC5 RSVD 0x9E HFC5 RSVD 0x9F HFC5 RSVD 0xA0 HFC5 RSVD 0xA1 HFC5 RSVD TABLE 4-1: CONFIGURATION FRU TABLE (CONTINUED) Address Group Field Name Pattern LED Name Parameters

 2020 Microchip Technology Inc. DS00003392B-page 15 EEC1005 0xA2 HFC5 RSVD 0xA3 HFC5 RSVD 0xA4 HFC5 CHECKSUM 0xA5 HFC6 UBM CONTROLLER DEVICE CODE MSB 0xA6 HFC6 UBM CONTRO LLER DEVICE CODE 0xA7 HFC6 UBM CONTRO LLER DEVICE CODE 0xA8 HFC6 UBM CONTROLLER DEVICE CODE LSB 0xA9 HFC6 SILICON VENDOR ID VENDOR SPECIFIC 0xAA HFC6 SILICON VENDOR ID VENDOR SPECIFIC 0xAB HFC6 HFC IDENTITY 0xAC HFC6 CPRSNT# or CHANGE_DETECT# 0xAD HFC6 RSVD 0xAE HFC6 RSVD 0xAF HFC6 RSVD 0xB0 HFC6 RSVD 0xB1 HFC6 RSVD 0xB2 HFC6 RSVD 0xB3 HFC6 RSVD 0xB4 HFC6 RSVD 0xB5 HFC6 RSVD 0xB6 HFC6 RSVD 0xB7 HFC6 RSVD 0xB8 HFC6 RSVD 0xB9 HFC6 RSVD 0xBA HFC6 RSVD 0xBB HFC6 RSVD 0xBC HFC6 CHECKSUM 0xBD LED PAT- TERN NOT_PRES_LED_ACT_BLINKP_REP NOT_PRES LED_ACT BLINK- P_REP 0xBE LED PAT- TERN NOT_PRES_LED_ACT_PAT_PERIOD NOT_PRES LED_ACT PAT_PE- RIOD 0xBF LED PAT- TERN NOT_PRES_LED_STAorLOC_BLINK- P_REP NOT_PRES LED_STAor- LOC BLINK- P_REP 0xC0 LED PAT- TERN NOT_PRES_LED_STAorLOC_PAT_PE- RIOD NOT_PRES LED_STAor- LOC PAT_PE- RIOD 0xC1 LED PAT- TERN NOT_PRES_LED_FAIL_BLINKP_REP NOT_PRES LED_FAIL BLINK- P_REP 0xC2 LED PAT- TERN NOT_PRES_LED_FAIL_PAT_PERIOD NOT_PRES LED_FAIL PAT_PE- RIOD 0xC3 LED PAT- TERN PRES_NO_ACT_LED_ACT_BLINKP_REP PRES_NO_AC T LED_ACT BLINK- P_REP 0xC4 LED PAT- TERN PRES_NO_ACT_LED_ACT_PAT_PERIOD PRES_NO_AC T LED_ACT PAT_PE- RIOD 0xC5 LED PAT- TERN PRES_NO_ACT_LED_STAorLOC_BLINK- P_REP PRES_NO_AC T LED_STAor- LOC BLINK- P_REP TABLE 4-1: CONFIGURATION FRU TABLE (CONTINUED) Address Group Field Name Pattern LED Name Parameters

DS00003392B-page 16  2020 Microchip Technology Inc. 0xC6 LED PAT- TERN PRES_NO_ACT_LED_STAor- LOC_PAT_PERIOD PRES_NO_AC T LED_STAor- LOC PAT_PE- RIOD 0xC7 LED PAT- TERN PRES_NO_ACT_LED_FAIL_BLINKP_REP PRES_NO_AC T LED_FAIL BLINK- P_REP 0xC8 LED PAT- TERN RIOD PRES_NO_AC T LED_FAIL PAT_PE- RIOD 0xC9 LED PAT- TERN PRES_ACT_LED_ACT_BLINKP_REP PRES_ACT LED_ACT BLINK- P_REP 0xCA LED PAT- TERN PRES_ACT_LED_ACT_PAT_PERIOD PRES_ACT LED_ACT PAT_PE- RIOD 0xCB LED PAT- TERN PRES_ACT_LED_STAorLOC_BLINK- P_REP PRES_ACT LED_STAor- LOC BLINK- P_REP 0xCC LED PAT- TERN PRES_ACT_LED_STAorLOC_PAT_PE- RIOD PRES_ACT LED_STAor- LOC PAT_PE- RIOD 0xCD LED PAT- TERN PRES_ACT_LED_FAIL_BLINKP_REP PRES_ACT LED_FAIL BLINK- P_REP 0xCE LED PAT- TERN PRES_ACT_LED_FAIL_PAT_PERIOD PRES_ACT LED_FAIL PAT_PE- RIOD 0xCF LED PAT- TERN LOCATE_LED_ACT_BLINKP_REP LOCATE LED_ACT BLINK- P_REP 0xD0 LED PAT- TERN LOCATE_LED_ACT_PAT_PERIOD LOCATE LED_ACT PAT_PE- RIOD 0xD1 LED PAT- TERN LOCATE_LED_STAorLOC_BLINKP_REP LOCATE LED_STAor- LOC BLINK- P_REP 0xD2 LED PAT- TERN LOCATE_LED_STAorLOC_PAT_PERIOD LOCATE LED_STAor- LOC PAT_PE- RIOD 0xD3 LED PAT- TERN LOCATE_LED_FAIL_BLINKP_REP LOCATE LED_FAIL BLINK- P_REP 0xD4 LED PAT- TERN LOCATE_LED_FAIL_PAT_PERIOD LOCATE LED_FAIL PAT_PE- RIOD 0xD5 LED PAT- TERN FAIL_LED_ACT_BLINKP_REP FAIL LED_ACT BLINK- P_REP 0xD6 LED PAT- TERN FAIL_LED_ACT_PAT_PERIOD FAIL LED_ACT PAT_PE- RIOD 0xD7 LED PAT- TERN FAIL_LED_STAorLOC_BLINKP_REP FAIL LED_STAor- LOC BLINK- P_REP 0xD8 LED PAT- TERN FAIL_LED_STAorLOC_PAT_PERIOD FAIL LED_STAor- LOC PAT_PE- RIOD 0xD9 LED PAT- TERN FAIL_LED_FAIL_BLINKP_REP FAIL LED_FAIL BLINK- P_REP 0xDA LED PAT- TERN FAIL_LED_FAIL_PAT_PERIOD FAIL LED_FAIL PAT_PE- RIOD 0xDB LED PAT- TERN REBUILD_LED_ACT_BLINKP_REP REBUILD LED_ACT BLINK- P_REP 0xDC LED PAT- TERN REBUILD_LED_ACT_PAT_PERIOD REBUILD LED_ACT PAT_PE- RIOD 0xDD LED PAT- TERN REBUILD_LED_STAorLOC_BLINKP_REP REBUILD LED_STAor- LOC BLINK- P_REP 0xDE LED PAT- TERN REBUILD_LED_STAorLOC_PAT_PERIOD REBUILD LED_STAor- LOC PAT_PE- RIOD TABLE 4-1: CONFIGURATION FRU TABLE (CONTINUED) Address Group Field Name Pattern LED Name Parameters

 2020 Microchip Technology Inc. DS00003392B-page 17 EEC1005 0xDF LED PAT- TERN REBUILD_LED_FAIL_BLINKP_REP REBUILD LED_FAIL BLINK- P_REP 0xE0 LED PAT- TERN REBUILD_LED_FAIL_PAT_PERIOD REBUILD LED_FAIL PAT_PE- RIOD 0xE1 LED PAT- TERN PFA_LED_ACT_BLINKP_REP PFA LED_ACT BLINK- P_REP 0xE2 LED PAT- TERN PFA_LED_ACT_PAT_PERIOD PFA LED_ACT PAT_PE- RIOD 0xE3 LED PAT- TERN PFA_LED_STAorLOC_BLINKP_REP PFA LED_STAor- LOC BLINK- P_REP 0xE4 LED PAT- TERN PFA_LED_STAorLOC_PAT_PERIOD PFA LED_STAor- LOC PAT_PE- RIOD 0xE5 LED PAT- TERN PFA_LED_FAIL_BLINKP_REP PFA LED_FAIL BLINK- P_REP 0xE6 LED PAT- TERN PFA_LED_FAIL_PAT_PERIOD PFA LED_FAIL PAT_PE- RIOD 0xE7 LED PAT- TERN RSVD 0xE8 LED PAT- TERN RSVD 0xE9 LED PAT- TERN RSVD 0xEA LED PAT- TERN RSVD 0xEB LED PAT- TERN RSVD 0xEC LED PAT- TERN RSVD 0xED LED PAT- TERN RSVD 0xEE LED PAT- TERN RSVD 0xEF LED PAT- TERN RSVD 0xF0 LED PAT- TERN RSVD 0xF1 LED PAT- TERN RSVD 0xF2 LED PAT- TERN RSVD 0xF3 LED PAT- TERN RSVD 0xF4 LED PAT- TERN RSVD 0xF5 LED PAT- TERN RSVD 0xF6 LED PAT- TERN RSVD 0xF7 LED PAT- TERN RSVD TABLE 4-1: CONFIGURATION FRU TABLE (CONTINUED) Address Group Field Name Pattern LED Name Parameters

DS00003392B-page 18  2020 Microchip Technology Inc. 0xF8 LED PAT- TERN RSVD 0xF9 LED PAT- TERN RSVD 0xFA LED PAT- TERN RSVD 0xFB LED PAT- TERN RSVD 0xFC LED PAT- TERN RSVD 0xFD LED PAT- TERN RSVD 0xFE LED PAT- TERN RSVD 0xFF LED PAT- TERN CHECKSUM TABLE 4-1: CONFIGURATION FRU TABLE (CONTINUED) Address Group Field Name Pattern LED Name Parameters

 2020 Microchip Technology Inc. DS00003392B-page 19 EEC1005

5.0 GENERIC FRU

EEC1005 has a Generic FRU space which customer can use as non v olatile storage. 256 bytes are allocated for this Customer defined Generic FRU. This memory emulates AT24C02 256 byte I2C EEPROM.Read and write of data to this FRU space can be done by host over the same physical I2C interf ace connected to BMC/Host at I2C slave address 0x54 (7-bit address).

DS00003392B-page 20  2020 Microchip Technology Inc.

6.0 UBM FRU

The SFF-TA-1005 (UBM) Specification calls out for an external Field Replaceable Unit (FRU) per every UBM Controller. EEC1005 incorporates a UBM FRU for every UBM Controller as per the spec requirement within EEC1005 Memory space. This saves board space and cost. The UBM FRU on backplane is a 256 byte read-only NVRAM with IPM I FRU formatted content and is responsible for reporting static backplane information. FIGURE 6-1: UBM FRU FORMAT

 2020 Microchip Technology Inc. DS00003392B-page 21 EEC1005 The UBM FRU is addressed as specified by SFF-TA-1005, over Slave Address (0xAE). FIGURE 6-2: UBM FRU HFC 0 HFC 1 EEC1005 Drive0 Drive4 UBM CONTROLLER 1 UBM CONTROLLER 2 UBM FRU UBM FRUUBM I2C UBM I2C

DS00003392B-page 22  2020 Microchip Technology Inc.

7.0 UBM CONTROLLER COMMANDS

The UBM Controller manages the Host facing Connector sideband I/O signaling, the Drive facing connector I/O signal- ing and the LED states for the DFC. It provides backplane imple mentation features and options for the initialization of the devices. These features are selected for the device through the CONFIG_PIN (Section 10.2, "Pin List") as explained in Section 3.0, "Configurations". The below are the supported UBM controller command set for EEC1005. There are variables in UBM that are client specific for example “Vendor Specific” bytes of Silicon Identity and Revision Command. EEC 1005 allows clients to initialize those variables from FRU, the UBM registers are initialized to these values on power up.

7.1 Silicon Identity and Revision (0x02)

7.2 Programming Update Mode Capabilities (0x03)

Update Mode: The update mode will be set to 0x01 to indicate that update is supported while the device remains online. In order to support the non-destructive status of NVME drives while the update is being performed the GPIOs status will remain consistent across a firmware reset.

7.3 Host Facing Connector Info (0x30)

Host Facing Connector ID will start from 0 and will report SAS HFC first followed by NVME HFC PORT TYPE: HFCs that are SAS/SATA shall report Port Type = 0. HFCs that are PCIe shall report Port Type = 1. Byte/Bit 7 6 5 4 3 2 1 0

0 UBM Spec Major Version = 1 UBM Spec Minor Version = 3

1 PCIE Vendor ID (LSB) = 0x54

2 PCIE Vendor ID (MSB) = 0x00

RESERVED = 0x00

4 UMB Controller Device Code (LSB) = Configuration FRU

5 UBM Controller Device Code = Configuration FRU

7 UBM Controller Device Code (MSB) = Configuration FRU

RESERVED = 0x00009

10 UBM Controller Image Version Minor = Backplane FW Minor Versi on

11 UBM Controller Image Version Ma jor = Backplane FW Major Version

12 Vendor Specific = Configuration FRU

0 RSVD Update Mode = 0x01

0 Port Type

= 1 (PCIe) = 0 (SAS) RSVD = 0x0 Host Facing Connector Identity = Configuration FRU

 2020 Microchip Technology Inc. DS00003392B-page 23 EEC1005

7.4 Backplane Info (0x31)

The Backplane Type will represent the Configuration selected from Config Pin.The Backplane Number will be read from Configuration FRU or configured based on input voltage on CONFIG_BPNUM_PIN.

7.5 Starting Slot (0x32)

Starting Slot is fixed to 0x0.

7.6 Capabilities (0x33)

CLOCK ROUTING: Set to 0 for SAS HFCS. Set to 1 for PCIe HFCs. SLOT POWER CONTROL: Set to 0. DFCs with SAS drives will support Slot Power Control if a backplane configuration supports Power Disable Pin PCIE RESET CONTROL: Set to 0. DUAL PORT: Set to 0. Single ported only. 2WIRE RESET: Set to 0. 2-wire reset is not supported. CHANGE DETECT: Set to 1. One Change Detect interrupt supported per backplane HFC. DFC CHANGE COUNT : Set to 1. Indicates if a change count is maintained per an individual DFC Status and Control Command Descriptor. PRSNT: Set to 1. Indicates that the DFCs connected to this HFC support the PRSNT signal. IFDET1: Set to 1. Indicates that the DFCs connected to this HFC support the IFDET1 signal. *IFDET2: This bit will be set to 1 if it is a U.3 backplane and to 0 if it is a U.2 backplane DFC PERST# MANAGEMENT OVERRIDE : Set to 1, Override supported

7.7 Features (0x34)

READ CHECKSUM: Set to 1. Byte/Bit 7 6 5 4 3 2 1 0

0 Backplane Type RSVD = 0 Backplane Number = Configuration FRU

0 Starting Slot = 0x00

Count = 1 Change Detect Int = 1 2-Wire Reset = 02h Dual Port = 0b PCIe Reset Control Slot Power Control = 1 Clock Rout- ing = Configu- ration FRU

1 RSVD = 00h DFC

PERST# Manage- ment Override support =1 IFDET2 = 0 or 1* IFDET1 = 1 PRSNT = 1 P10 Byte/Bit 7 6 5 4 3 2 1 0

0 DFC PERST# Man-

State Mask = Drive Type Change Mask = PCIE Reset Change Mask = CPRSTN = Configura- tion FRU Write Check- sum = 1b Read Check- sum = 1b

1 RSVD = 0x00

DS00003392B-page 24  2020 Microchip Technology Inc. WRITE CHECKSUM CHECKING: Set to 1. CPRSNT LEGACY MODE: Set to 0. PCIE RESET CHANGE MASK: Set to 1. DRIVE TYPE INSTALLED CHANGE COUNT MASK: Set to 1 OPERATIONAL STATE CHANGE COUNT MASK: Set to 1. DFC PERST# MANAGEMENT OVERRIDE : Indicates the DFC_PERST# behaviour when a drive has been installed 0 = No override 1 = DFC PERST# Managed upon install 2 = DFC PERST# Automatically released upon install 3 = Reserved

 2020 Microchip Technology Inc. DS00003392B-page 25 EEC1005

8.0 LED SPECIFICATIONS

EEC1005 supports three LED’s per every DFC ( Activity, Fail, Locate ).The Drive Activity LED can be controlled directly from Host or from EEC1005 which is selected using Configuration FRU (Configuration address 0x01), the Fail (Amber) and Locate (Green) are supported as a bi color LED on backplane and controlled by EEC1005. In order to prevent any current leakage, the LED pins will remain tri-stated till the backplane is initialized and the default state for all the LED’s will be off on power up after initialization is complete. The table below summarizes the LED patterns as per International Blinking Pattern Interpretation defined in SFF-8489. If a Host sets multiple drive states at the same time, then bac kplane controller will follow a priority as defined in the below. Configurable LED blink frequency/duty cycle are also supported via FRU in order to support blink patterns that are not IBPI complaint. TABLE 8-1: IBPI LED BLINK PATTERN Drive State Locate/Identify L ED (Green) Fail LED (Amber) Drive Not Present OFF OFF Drive Present, No Activity ON OFF Drive Present, Activity ON OFF Locate (Identify) 4Hz OFF Fail OFF ON Rebuild OFF 1Hz Rebuild Abort OFF 1Hz Predicted Failure (PFA) OFF 2 Blinks at 4Hz & Pause for 0.5sec Hot spare Not Supported Not Supported In A Critical Array Not Supported Not Supported In a Failed Array Not Supported Not Supported TABLE 8-2: LED PRIORITY Drive State Priority Locate (Identify) 1 Fault 2 Predicted Failure 3 Rebuild Abort 4 Drive Present, Activity 5 Drive Present, No Activity 6

DS00003392B-page 26  2020 Microchip Technology Inc.

9.0 MULTIPLE CHASSIS CONFIGURATION

When multiple Backplanes are used in a single system, the Backplane Number in the Backplane Info (0x31) UBM reg- ister is used by host to determine the physical backplane location of a given backplane. The Backplane Number is populates with the values of Table 9-1, “ Backplane number vs Resistor select” as a function of the voltage on pin CONFIG_BPNUM_PIN. This voltage can be provided by a fixed voltage divider on the backplane or by mating with the backplane power cable. Alternatively, the Configuration FRU can be used to overwrite the Back- plane Number value. This is done by writing a value different than 0xFF to offset 0x04 of the Configuration FRU, Back- plane Physical Location. FIGURE 9-1: MULTIPLE CHASSIS CONFIGURATION CPU HBA2 Front x8 Backplane 1 Rear x4 Backplane 1 Direct I2C/Chipset UBM I2C UBM I2C BMC I2C BMC I2C PCIe PCIe HBA1 BMC

 2020 Microchip Technology Inc. DS00003392B-page 27 EEC1005 FIGURE 9-2: BACKPLANE NUMBER SELECT ADC INPUT TABLE 9-1: BACKPLANE NUMBER VS RESISTOR SELECT Backplane Number Pull Down Resistor (R2) in Ohms Voltage at the Config_BPNUM_Pin 000 . 0 0 0 1 470 0.148 2 820 0.250 3 1200 0.354 4 1800 0.503 5 2700 0.702 6 3600 0.874 7 4700 1.055 8 5600 1.185 9 6800 1.336 10 8200 1.487 11 10000 1.650 12 12000 1.800 13 15000 1.980 14 18000 2.121 15 22000 2.269 Note 1: The resistor values suggested are based on the standard value resistors available @1% tolerance 2: It is highly recommended to use 1% tolerant resistors at ADC input 3: The ADC input capacitor should be 0.1uF 4: The resistor R1 should be fixed at 10K 5: The Backplane Number values not mentioned in the above table is not supported by EEC1005 R1 = 10K VCC = 3.3V C = 0.1ufR2 To ADC input (Config_BPNUM_Pin)

DS00003392B-page 28  2020 Microchip Technology Inc.

10.0 PIN CONFIGURATION

10.1 Description

Section 10.0 “Pin Configuration” consists of the Pin Lists and Package Drawings.

10.2 Pin List

TABLE 10-1: SGPIO CONTR OLLER - 144 PIN PACKAGE Ball Number Function A1 DFC_00_PWR_DISABLE A2 BMC_I2C_SDA A3 BMC_I2C_SCL A4 DFC_14_IFDET_N A5 DFC_13_IFDET_N A6 RSVD A7 NC A8 SGPIO_03_DATAOUT A9 DFC_07_IFDET_N A10 DFC_13_ACTIVITY_N A11 DFC_08_PWR_DISABLE A12 DFC_02_LED_STA_N B1 DFC_06_ACTIVITY_N B2 SGPIO_00_CLOCK B3 DFC_05_LED_STA_N B4 DFC_01_IFDET_N B5 DFC_12_IFDET_N B6 NC B7 DFC_09_PRSNT_N B8 DFC_03_PWR_DISABLE B9 DFC_05_PWR_DISABLE B10 DFC_04_PWR_DISABLE B11 DFC_14_ACTIVITY_N B12 SGPIO_03_CTRL_TYPE C1 DFC_01_PWR_DISABLE C2 SGPIO_03_CLOCK C3 SGPIO_01_CLOCK C4 SGPIO_02_CLOCK C5 DFC_13_PRSNT_N C6 RSVD C7 DFC_10_PRSNT_N C8 DFC_07_LED_STA_N C9 DFC_02_ACTIVITY_N C10 DFC_10_ACTIVITY_N C11 DFC_07_PWR_DISABLE C12 DFC_03_ACTIVITY_N D1 VCC

 2020 Microchip Technology Inc. DS00003392B-page 29 EEC1005 D2 DFC_07_ACTIVITY_N D3 DFC_02_IFDET_N D4 nRESET_IN D5 SGPIO_02_LOAD D6 DFC_12_PWR_DISABLE D7 NC D8 DFC_11_PWR_DISABLE D9 DFC_08_IFDET_N D10 DFC_11_ACTIVITY_N D11 DFC_14_PWR_DISABLE D12 DFC_13_PWR_DISABLE E1 BMC_2WIRE_RESET E2 DFC_15_ACTIVITY_N E3 DFC_02_PWR_DISABLE E4 SGPIO_00_DATAOUT E5 VCC E6 VSS E7 VCC E8 VSS E9 SGPIO_01_DATAOUT E10 DFC_09_ACTIVITY_N E11 DFC_00_LED_ACT_N E12 SGPIO_02_CTRL_TYPE F1 VR_CAP F2 DFC_06_PWR_DISABLE F3 SGPIO_03_DATAIN F4 SGPIO_01_LOAD F5 VCC F6 DFC_06_IFDET_N F7 DFC_04_LED_STA_N F8 VSS F9 DFC_07_PRSNT_N F10 nSTRAP_IN F11 DFC_08_ACTIVITY_N F12 DFC_06_LED_STA_N G1 DFC_15_PWR_DISABLE G2 VREF_ADC G3 SGPIO_03_LOAD G4 DFC_12_ACTIVITY_N G5 VSS G6 VSS G7 DFC_04_ACTIVITY_N G8 VCC TABLE 10-1: SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED) Ball Number Function

DS00003392B-page 30  2020 Microchip Technology Inc. G9 HEARTBEAT_PIN G10 DFC_08_LED_STA_N G11 DFC_03_LED_STA_N G12 DFC_05_ACTIVITY_N H1 CONFIG_PIN H2 DFC_05_IFDET_N H3 DFC_09_PWR_DISABLE H4 DFC_01_LED_ACT_N H5 DFC_10_PWR_DISABLE H6 VCC H7 VCC H8 DFC_00_ACTIVITY_N H9 DFC_09_LED_STA_N H10 DFC_10_LED_STA_N H11 DFC_11_LED_STA_N H12 DFC_11_LED_ACT_N J1 DFC_04_IFDET_N J2 DFC_00_IFDET_N J3 DFC_03_IFDET_N J4 DFC_10_IFDET_N J5 DFC_03_LED_ACT_N J6 DFC_15_LED_ACT_N J7 DFC_12_LED_ACT_N J8 SGPIO_02_DATAIN J9 NC J10 DFC_12_PRSNT_N J11 DFC_11_PRSNT_N J12 SGPIO_00_CTRL_TYPE K1 CONFIG_BPNUM_PIN K2 DFC_00_PRSNT_N K3 DFC_15_PRSNT_N K4 DFC_02_LED_ACT_N K5 DFC_13_LED_ACT_N K6 DFC_12_LED_STA_N K7 DFC_06_LED_ACT_N K8 DFC_07_LED_ACT_N K9 DFC_09_LED_ACT_N K10 DFC_08_LED_ACT_N K11 SGPIO_00_DATAIN K12 DFC_15_IFDET_N L1 DFC_01_PRSNT_N L2 SGPIO_00_LOAD L3 DFC_14_PRSNT_N TABLE 10-1: SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED) Ball Number Function

 2020 Microchip Technology Inc. DS00003392B-page 31 EEC1005 L4 SGPIO_01_DATAIN L5 DFC_14_LED_ACT_N L6 DFC_14_LED_STA_N L7 DFC_05_LED_ACT_N L8 DFC_04_PRSNT_N L9 DFC_01_LED_STA_N L10 SGPIO_01_CTRL_TYPE L11 DFC_05_PRSNT_N L12 DFC_10_LED_ACT_N M1 DFC_09_IFDET_N M2 DFC_02_PRSNT_N M3 DFC_11_IFDET_N M4 DFC_03_PRSNT_N M5 DFC_08_PRSNT_N M6 DFC_04_LED_ACT_N M7 DFC_13_LED_STA_N M8 DFC_00_LED_STA_N M9 DFC_15_LED_STA_N M10 DFC_01_ACTIVITY_N M11 SGPIO_02_DATAOUT M12 DFC_06_PRSNT_N TABLE 10-2: UBM CONTROLLER - 144 PIN PACKAGE Ball Number Function A1 DFC_02_IFDET2_N A2 BMC_I2C_SDA A3 BMC_I2C_SCL A4 HFC_04_SCL A5 HFC_04_SDA A6 RSVD A7 HFC_01_SDA A8 DFC_06_ACTIVITY_N A9 DFC_07_IFDET_N A10 DFC_10_IFDET2_N A11 DFC_09_IFDET2_N A12 DFC_02_LED_STA_N B1 DFC_01_IFDET2_N B2 HFC_00_SCL B3 DFC_05_LED_STA_N B4 DFC_01_IFDET_N B5 HFC_02_SCL B6 HFC_02_SDA TABLE 10-1: SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED) Ball Number Function

DS00003392B-page 32  2020 Microchip Technology Inc. B7 DFC_09_PRSNT_N B8 DFC_04_PERST_N B9 DFC_06_IFDET2_N B10 DFC_05_IFDET2_N B11 DFC_11_IFDET2_N B12 DFC_11_PWR_DISABLE C1 DFC_03_IFDET2_N C2 DFC_09_PERST_N C3 DFC_05_PERST_N C4 DFC_08_PERST_N C5 DFC_10_PERST_N C6 RSVD C7 DFC_10_PRSNT_N C8 DFC_07_LED_STA_N C9 DFC_02_ACTIVITY_N C10 DFC_10_ACTIVITY_N C11 DFC_08_IFDET2_N C12 DFC_08_PWR_DISABLE D1 VCC D2 DFC_00_PERST_N D3 DFC_02_IFDET_N D4 nRESET_IN D5 DFC_00_IFDET2_N D6 HFC_03_CHNG_DET_N D7 HFC_01_SCL D8 HFC_01_CHNG_DET_N D9 DFC_08_IFDET_N D10 DFC_11_ACTIVITY_N D11 HFC_05_2WIRE_RESET D12 HFC_04_2WIRE_RESET E1 BMC_2WIRE_RESET E2 DFC_11_PERST_N E3 DFC_04_IFDET2_N E4 DFC_03_ACTIVITY_N E5 VCC E6 VSS E7 VCC E8 VSS E9 DFC_02_PERST_N E10 DFC_09_ACTIVITY_N E11 DFC_00_LED_ACT_N E12 DFC_10_PWR_DISABLE F1 VR_CAP TABLE 10-2: UBM CONTROLLER - 144 PIN PACKAGE (CONTINUED) Ball Number Function

 2020 Microchip Technology Inc. DS00003392B-page 33 EEC1005 F2 DFC_07_IFDET2_N F3 DFC_07_ACTIVITY_N F4 DFC_03_PERST_N F5 VCC F6 DFC_06_IFDET_N F7 DFC_04_LED_STA_N F8 VSS F9 DFC_07_PRSNT_N F10 nSTRAP_IN F11 DFC_01_PERST_N F12 DFC_06_LED_STA_N G1 HFC_05_CHNG_DET_N G2 VREF_ADC G3 DFC_08_ACTIVITY_N G4 DFC_09_PWR_DISABLE G5 VSS G6 VSS G7 DFC_04_ACTIVITY_N G8 VCC G9 HEARTBEAT_PIN G10 DFC_08_LED_STA_N G11 DFC_03_LED_STA_N G12 DFC_05_ACTIVITY_N H1 CONFIG_PIN H2 DFC_05_IFDET_N H3 HFC_00_2WIRE_RESET H4 DFC_01_LED_ACT_N H5 HFC_01_2WIRE_RESET H6 VCC H7 VCC H8 DFC_00_ACTIVITY_N H9 DFC_09_LED_STA_N H10 DFC_10_LED_STA_N H11 DFC_11_LED_STA_N H12 DFC_11_LED_ACT_N J1 DFC_04_IFDET_N J2 DFC_00_IFDET_N J3 DFC_03_IFDET_N J4 DFC_10_IFDET_N J5 DFC_03_LED_ACT_N J6 DFC_01_PWR_DISABLE J7 HFC_02_2WIRE_RESET J8 DFC_06_PWR_DISABLE TABLE 10-2: UBM CONTROLLER - 144 PIN PACKAGE (CONTINUED) Ball Number Function

DS00003392B-page 34  2020 Microchip Technology Inc. J9 HFC_03_SCL J10 HFC_05_SCL J11 DFC_11_PRSNT_N J12 HFC_03_SDA K1 CONFIG_BPNUM_PIN K2 DFC_00_PRSNT_N K3 DFC_07_PERST_N K4 DFC_02_LED_ACT_N K5 HFC_03_2WIRE_RESET K6 DFC_02_PWR_DISABLE K7 DFC_06_LED_ACT_N K8 DFC_07_LED_ACT_N K9 DFC_09_LED_ACT_N K10 DFC_08_LED_ACT_N K11 HFC_00_CHNG_DET_N K12 HFC_05_SDA L1 DFC_01_PRSNT_N L2 HFC_00_SDA L3 DFC_06_PERST_N L4 HFC_04_CHNG_DET_N L5 DFC_00_PWR_DISABLE L6 DFC_04_PWR_DISABLE L7 DFC_05_LED_ACT_N L8 DFC_04_PRSNT_N L9 DFC_01_LED_STA_N L10 HFC_02_CHNG_DET_N L11 DFC_05_PRSNT_N L12 DFC_10_LED_ACT_N M1 DFC_09_IFDET_N M2 DFC_02_PRSNT_N M3 DFC_11_IFDET_N M4 DFC_03_PRSNT_N M5 DFC_08_PRSNT_N M6 DFC_04_LED_ACT_N M7 DFC_03_PWR_DISABLE M8 DFC_00_LED_STA_N M9 DFC_07_PWR_DISABLE M10 DFC_01_ACTIVITY_N M11 DFC_05_PWR_DISABLE M12 DFC_06_PRSNT_N TABLE 10-2: UBM CONTROLLER - 144 PIN PACKAGE (CONTINUED) Ball Number Function

 2020 Microchip Technology Inc. DS00003392B-page 35 EEC1005 TABLE 10-3: SGPIO CONTROLLER - 84 PIN PACKAGE Ball Number Function A1 DFC_07_ACTIVITY_N A2 DFC_00_IFDET_N A3 DFC_05_LED_STA_N A4 BMC_I2C_SDA A5 BMC_I2C_SCL A6 DFC_03_ACTIVITY_N A7 DFC_00_PRSNT_N A8 RSVD A9 DFC_06_PWR_DISABLE A10 DFC_05_PWR_DISABLE B1 VCC B2 nRESET_IN B3 SGPIO_01_CLOCK B4 SGPIO_00_CLOCK B5 DFC_01_IFDET_N B6 DFC_02_ACTIVITY_N B7 NC B8 DFC_07_LED_STA_N B9 DFC_03_PWR_DISABLE B10 DFC_07_IFDET_N C1 SGPIO_00_LOAD C2 SGPIO_00_DATAOUT C5 DFC_02_PWR_DISABLE C6 RSVD C9 DFC_01_PWR_DISABLE C10 DFC_02_IFDET_N D1 VR_CAP D2 SGPIO_01_LOAD D4 VCC D5 VCC D6 VSS D7 VSS D9 DFC_06_LED_STA_N D10 DFC_02_LED_STA_N E1 CONFIG_PIN E2 DFC_04_PWR_DISABLE E3 BMC_2WIRE_RESET E4 VCC E7 VSS E8 SGPIO_01_DATAOUT E9 DFC_00_LED_ACT_N E10 nSTRAP_IN F1 VREF_ADC

DS00003392B-page 36  2020 Microchip Technology Inc. F2 DFC_01_LED_ACT_N F3 DFC_06_IFDET_N F4 VSS F7 VSS F8 DFC_07_PRSNT_N F9 DFC_00_PWR_DISABLE F10 DFC_04_ACTIVITY_N G1 DFC_04_IFDET_N G2 DFC_05_ACTIVITY_N G4 RSVD G5 VCC G6 VCC G7 VCC G9 DFC_04_LED_STA_N G10 DFC_03_LED_STA_N H1 DFC_05_IFDET_N H2 SPARE H5 DFC_03_LED_ACT_N H6 DFC_01_ACTIVITY_N H9 DFC_00_ACTIVITY_N H10 DFC_07_PWR_DISABLE J1 DFC_03_IFDET_N J2 CONFIG_BPNUM_PIN J3 SGPIO_01_DATAIN J4 DFC_02_PRSNT_N J5 DFC_04_LED_ACT_N J6 DFC_04_PRSNT_N J7 DFC_00_LED_STA_N J8 DFC_06_PRSNT_N J9 SGPIO_00_DATAIN J10 SGPIO_00_CTRL_TYPE K1 DFC_06_ACTIVITY_N K2 DFC_01_PRSNT_N K3 DFC_02_LED_ACT_N K4 DFC_03_PRSNT_N K5 DFC_06_LED_ACT_N K6 DFC_07_LED_ACT_N K7 DFC_05_LED_ACT_N K8 DFC_01_LED_STA_N K9 SGPIO_01_CTRL_TYPE K10 DFC_05_PRSNT_N TABLE 10-3: SGPIO CONTROLLER - 84 PIN PACKAGE (CONTINUED) Ball Number Function

 2020 Microchip Technology Inc. DS00003392B-page 37 EEC1005 TABLE 10-4: UBM CONTROLLER - 84 PIN PACKAGE Ball Number Function A1 DFC_00_PERST_N A2 DFC_02_IFDET_N A3 DFC_05_LED_STA_N A4 BMC_I2C_SDA A5 BMC_I2C_SCL A6 HFC_04_SCL A7 HFC_02_SCL A8 DFC_05_ACTIVITY_N A9 HFC_01_SDA A10 HFC_01_SCL B1 VCC B2 nRESET_IN B3 DFC_05_PERST_N B4 HFC_00_SCL B5 DFC_01_IFDET_N B6 HFC_04_SDA B7 HFC_02_SDA B8 DFC_07_LED_STA_N B9 DFC_04_PERST_N B10 DFC_07_IFDET_N C1 HFC_00_SDA C2 DFC_03_ACTIVITY_ N/HFC_03_2WIRE_RESET C5 HFC_03_CHNG_DET_N C6 DFC_06_ACTIVITY_N C9 HFC_01_CHNG_DET_N C10 DFC_02_ACTIVITY_ N/HFC_02_2WIRE_RESET D1 VR_CAP D2 DFC_03_PERST_N D4 VCC D5 VCC D6 VSS D7 VSS D9 DFC_06_LED_STA_N D10 DFC_02_LED_STA_N E1 CONFIG_PIN E2 DFC_07_ACTIVITY_N E3 BMC_2WIRE_RESET E4 VCC E7 VSS E8 DFC_02_PERST_N E9 DFC_00_LED_ACT_N E10 nSTRAP_IN F1 VREF_ADC

DS00003392B-page 38  2020 Microchip Technology Inc. F2 DFC_01_LED_ACT_N F3 DFC_06_IFDET_N F4 VSS F7 VSS F8 DFC_07_PRSNT_N F9 DFC_01_PERST_N F10 DFC_04_ACTIVITY_N/HFC_04_2WIRE_RESET G1 DFC_04_IFDET_N G2 DFC_07_PERST_N G4 DFC_07_PRSNT_N G5 VCC G6 VCC G7 VCC G9 DFC_04_LED_STA_N G10 DFC_03_LED_STA_N H1 DFC_05_IFDET_N H2 DFC_00_IFDET_N H5 DFC_03_LED_ACT_N H6 DFC_01_ACTIVITY_ N/HFC_01_2WIRE_RESET H9 DFC_00_ACTIVITY_ N/HFC_00_2WIRE_RESET H10 HFC_03_SCL J1 DFC_03_IFDET_N J2 CONFIG_BPNUM_PIN J3 HFC_04_CHNG_DET_N J4 DFC_02_PRSNT_N J5 DFC_04_LED_ACT_N J6 DFC_04_PRSNT_N J7 DFC_00_LED_STA_N J8 DFC_06_PRSNT_N J9 HFC_00_CHNG_DET_N J10 HFC_03_SDA K1 DFC_06_PERST_N K2 DFC_01_PRSNT_N K3 DFC_02_LED_ACT_N K4 DFC_03_PRSNT_N K5 DFC_06_LED_ACT_N K6 DFC_07_LED_ACT_N K7 DFC_05_LED_ACT_N K8 DFC_01_LED_STA_N K9 HFC_02_CHNG_DET_N K10 DFC_05_PRSNT_N TABLE 10-4: UBM CONTROLLER - 84 PIN PACKAGE (CONTINUED) Ball Number Function

 2020 Microchip Technology Inc. DS00003392B-page 39 EEC1005 TABLE 10-5: UBM_SGPIO CON TROLLER - 144 PIN PACKAGE Ball Number Function A1 DFC_02_IFDET2_N A2 BMC_I2C_SDA A3 BMC_I2C_SCL A4 NC A5 NC A6 RSVD A7 HFC_02_SDA A8 DFC_06_ACTIVITY_N A9 DFC_07_IFDET_N A10 NC A11 DFC_05_PERST_N A12 DFC_02_LED_STA_N B1 DFC_01_IFDET2_N B2 SGPIO_00_CLOCK/HFC_00_SCL B3 DFC_05_LED_STA_N B4 DFC_01_IFDET_N B5 HFC_03_SCL B6 HFC_03_SDA B7 DFC_03_PERST_N B8 DFC_04_PERST_N B9 DFC_06_IFDET2_N B10 DFC_05_IFDET2_N B11 HFC_04_SDA B12 HFC_00_CHNG_DET_N C1 DFC_03_IFDET2_N C2 NC C3 SGPIO_01_CLOCK C4 NC C5 NC C6 RSVD C7 NC C8 DFC_07_LED_STA_N C9 DFC_02_ACTIVITY_N C10 HFC_01_SCL C11 DFC_03_ACTIVITY_N C12 HFC_01_CHNG_DET_N D1 VCC D2 DFC_00_PERST_N D3 DFC_02_IFDET_N D4 nRESET_IN D5 DFC_00_IFDET2_N D6 HFC_04_CHNG_DET_N D7 HFC_02_SCL

DS00003392B-page 40  2020 Microchip Technology Inc. D8 HFC_02_CHNG_DET_N D9 HFC_04_SCL D10 HFC_01_SDA D11 NC D12 HFC_00_2WIRE_RESET E1 BMC_2WIRE_RESET E2 NC E3 DFC_04_IFDET2_N E4 SGPIO_00_DATAOUT E5 VCC E6 VSS E7 VCC E8 VSS E9 SGPIO_01_DATAOUT E10 HFC_03_CHNG_DET_N E11 DFC_00_LED_ACT_N E12 NC F1 VR_CAP F2 DFC_07_IFDET2_N F3 DFC_07_ACTIVITY_N F4 SGPIO_01_LOAD F5 VCC F6 DFC_06_IFDET_N F7 DFC_04_LED_STA_N F8 VSS F9 DFC_07_PRSNT_N F10 nSTRAP_IN F11 DFC_01_PERST_N F12 DFC_06_LED_STA_N G1 NC G2 VREF_ADC G3 NC G4 NC G5 VSS G6 VSS G7 DFC_04_ACTIVITY_N G8 VCC G9 HEARTBEAT_PIN G10 NC G11 DFC_03_LED_STA_N G12 DFC_05_ACTIVITY_N H1 CONFIG_PIN H2 DFC_05_IFDET_N TABLE 10-5: UBM_SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED) Ball Number Function

 2020 Microchip Technology Inc. DS00003392B-page 41 EEC1005 H3 HFC_01_2WIRE_RESET H4 DFC_01_LED_ACT_N H5 HFC_02_2WIRE_RESET H6 VCC H7 VCC H8 DFC_00_ACTIVITY_N H9 NC H10 NC H11 NC H12 NC J1 DFC_04_IFDET_N J2 DFC_00_IFDET_N J3 DFC_03_IFDET_N J4 NC J5 DFC_03_LED_ACT_N J6 DFC_01_PWR_DISABLE J7 HFC_03_2WIRE_RESET J8 DFC_06_PWR_DISABLE J9 NC J10 NC J11 NC J12 SGPIO_00_CTRL_TYPE K1 CONFIG_BPNUM_PIN K2 DFC_00_PRSNT_N K3 DFC_07_PERST_N K4 DFC_02_LED_ACT_N K5 HFC_04_2WIRE_RESET K6 DFC_02_PWR_DISABLE K7 DFC_06_LED_ACT_N K8 DFC_07_LED_ACT_N K9 NC K10 NC K11 SGPIO_00_DATAIN K12 NC L1 DFC_01_PRSNT_N L2 SGPIO_00_LOAD/HFC_00_SDA L3 DFC_06_PERST_N L4 SGPIO_01_DATAIN L5 DFC_00_PWR_DISABLE L6 DFC_04_PWR_DISABLE L7 DFC_05_LED_ACT_N L8 DFC_04_PRSNT_N L9 DFC_01_LED_STA_N TABLE 10-5: UBM_SGPIO CONTROLLE R - 144 PIN PACKAGE (CONTINUED) Ball Number Function

DS00003392B-page 42  2020 Microchip Technology Inc. L10 SGPIO_01_CTRL_TYPE L11 DFC_05_PRSNT_N L12 NC M1 DFC_02_PERST_N M2 DFC_02_PRSNT_N M3 NC M4 DFC_03_PRSNT_N M5 NC M6 DFC_04_LED_ACT_N M7 DFC_03_PWR_DISABLE M8 DFC_00_LED_STA_N M9 DFC_07_PWR_DISABLE M10 DFC_01_ACTIVITY_N M11 DFC_05_PWR_DISABLE M12 DFC_06_PRSNT_N TABLE 10-5: UBM_SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED) Ball Number Function

 2020 Microchip Technology Inc. DOS-00000 DS00003392B-page 43 EEC1005

11.0 ELECTRICAL SPECIFICATIONS

11.1 Maximum Ratings*

*Stresses exceeding those listed could cause permanent damage t o the device. This is a stress rating only and func- tional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied.

11.1.1 ABSOLUTE MAXIMUM THERMAL RATINGS

11.1.2 ABSOLUTE MAXIMUM SU PPLY VOLTAGE RATINGS

11.1.3 ABSOLUTE MAXIMUM I/O VOLTAGE RATINGS

11.2 Operational Specifications

11.2.1 POWER SUPPLY OPERATIONAL CHARACTERISTICS

11.2.2 CAPACITIVE LOADING SPECIFICATIONS

The following table defines the maximum capacitive load validated for the buffer characteristics listed in Table 11-4, "DC Electrical Characteristics". CAPACITANCE TA = 25°C; fc = 1MHz; Vcc = 3.3 VDC Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Max- imum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. Parameter Maximum Limits Operating Temperature Range -40 oC to +85oC Industrial Storage Temperature Range -55 o to +150oC Lead Temperature Range Refer to JEDEC Spec J-STD-020B Symbol Parameter Maximum Limits VCC 3.3V Power Supply with res pect to ground -0.3V to +3.63V Parameter Maximum Limits Voltage on any Digital Pin with respect to ground Determined by Power Supply of I/O Buffer and Pad Type TABLE 11-1: POWER SUPPLY OPERATING CONDITIONS Symbol Parameter MIN TYP MAX Units VCC 3.3V Power Supply 3.135 3.3 3.465 V Note: All output pins, except pin under test, tied to AC ground.

DS00003392B-page 44 DOS-00000  2020 Microchip Technology Inc.

11.2.3 DC ELECTRICAL CHARACTERISTICS FOR I/O BUFFERS

TABLE 11-2: MAXIMUM CAPACITIVE LOADING Parameter Symbol Limits Unit Notes MIN TYP MAX Input Capacitance C IN 10 pF Note 1 Output Capacitance C OUT 20 pF Note 2 Note 1: All input buffers can be characterized by this capacitance unless otherwise specified. 2: All output buffers can be characterized by this capacitance unless otherwise specified. TABLE 11-3: BUFFER TYPE Signal Name Buffer Type DFC_xx_ACTIVITY_N I DFC_xx_IFDET_N I DFC_xx_IFDET2_N I DFC_xx_PRSNT_N I HFC_xx_2WIRE_RESET I DFC_xx_LED_ACT_N OD-2mA DFC_xx_LED_STA_N OD-2mA DFC_xx_PERST_N OD-2mA DFC_xx_CHNG_DET_N OD-2mA DFC_xx_PWR_DISABLE_N PIO CONFIG_PIN I_AN CONFIG_BPNUM_PIN I_AN Note: xx is the instance/port number

 2020 Microchip Technology Inc. DOS-00000 DS00003392B-page 45 EEC1005 TABLE 11-4: DC ELECTRICAL CHARACTERISTICS Parameter Symbol MIN TYP MAX Units Comments PIO Type Buffer All PIO Buffers Pull-up Resistor @3.3V R PU 34 52 95 K Ω Internal PU selected via the GPIO Pin Control Register. All PIO Buffers Pull-down Resistor @3.3V R PD 38 63 127 K Ω Internal PD selected via the GPIO Pin Control Register. PIO V OL VOH VCC- 0.4 0.4 V V IOL = 4 mA (min) IOH = -4 mA (min) OD-2mA Low Output Level V OL 0.4 V I OL = 2mA (min) I Type Input Buffer TTL Compatible Schmitt Trigger Input Low Input Level V ILI 0.3x VCC V High Input Level V IHI 0.7x VCC V Schmitt Trigger Hysteresis V HYS 400 mV I_AN Type Buffer I_AN Type Buffer (Analog Input Buffer) I_AN Voltage range on pins: -0.3V to +3.63V These buffers are not 5V tolerant buffers and they are not back- drive protected ADC Reference Pins VREF_ADC Voltage (Option A) V VCC V Connect to same power supply as VCC Voltage (Option B) V 2.97 3.0 3.03 V Input Impedance R REF 75 K Ω Input Low Current ILEAK -0.05 +0.05 µA This buffer is not 5V tolerant This buffer is not backdrive pro- tected.

DS00003392B-page 46 DOS-00000  2020 Microchip Technology Inc.

11.2.3.1 Pin Leakage

Leakage characteristics for all digital I/O pins is shown in th e following Pin Leakage table, unless otherwise specified. Two exceptions are pins with Over-voltage protection and Backdrive protection (10.2 “Pin List”). Leakage character- istics for Over-Voltage protected pins and Backdrive protected pins are shown in the two sub-sections following the Pin Leakage table.

11.2.4 ADC ELECTRICAL CHARACTERISTICS

11.2.5 THERMAL CHARACTERISTICS

TABLE 11-5: PIN LEAKAGE (VCC=3.3V + 5%; VCC = 1.8V +5%) (TA = -40oC to +85oC) Leakage Current I IL +/-2 µA VIN=0V to VCC TABLE 11-6: ADC CHARACTERISTICS Symbol Parameter MIN TYP MAX Units Comments VCC Analog Supply Voltage 3.135 3.3 3.465 V VRNG Input Voltage Range 0 VREF _ADC V Range of VREF_ADC input to ADC ground RES Resolution – – 10/12 Bits Guaranteed Monotonic DNL Differential Non Linearity, DNL -1 – +1 LSB Guaranteed Monotonic INL Integral Non Linearity, INL -3.0 – +3 LSB Guaranteed Monotonic EGAIN Gain Error, EGAIN -2 – 2 LSB EOFFSET Offset Error, EOFFSET -2 – 2 LSB CONV Conversion Time 1.125 S/channel II Input Impedance 4 4.5 5.3 M  TABLE 11-7: THERMAL OPERATING CONDITIONS Rating Symbol MIN TYP MAX Unit Consumer Temperature Devices Operating Junction Temperature Range T J 0— 1 2 5 ° C Operating Ambient Temperature Range - Industrial T A -40 — +85 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – S IOH) PD 69.3 (PINT + PI/O) mW I/O Pin Power Dissipation: I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation P DMAX (TJa– TA)/JA a.Tj Max value is at ambient of 70oC W

 2020 Microchip Technology Inc. DOS-00000 DS00003392B-page 47 EEC1005

11.3 Power Consumption

TABLE 11-9: VCC SUPPLY CURRENT, I_VCC 48 MHz Clock Typical (3.3V, 25C) Max (3.45V, 70C) Max (3.45V, 85C) Unit Comments 48MHz 9.41 13.79 15.8 mA Full On

DS00003392B-page 48  2020 Microchip Technology Inc.

12.0 PACKAGE INFORMATION

12.1 144 Pin WFBGA/WC Package Note: For the most current package dra wings, see the Microchip Packag ing Specification at http://www.micro- chip.com/packaging. B A 0.15 C 0.15 C

0.15 C A B

0.08 C (DATUM B) (DATUM A) C SEATING PLANE TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 0.08 C Microchip Technology Drawing C04-416A Sheet 1 of 2 D E A 144X Øbe e 144X(A1) For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 144-Ball Very, Very Thin Fine Pitch Ball Grid Array (WCX) - 10x10 mm Body[WFBGA] e 0.10 C A B C D E F G H J K L M A B C D E F G H J K L M 1 23456789 1 0 1 1 1 2 123456789 1 0 1 1 1 2

 2020 Microchip Technology Inc. DS00003392B-page 49 EEC1005 0LFURFKLS7HFKQRORJ\\'UDZLQJ&$6KHHWRI 1XPEHURI7HUPLQDOV 2YHUDOO+HLJKW 7HUPLQDO'LDPHWHU 2YHUDOO:LGWK ([SRVHG3DG:LGWK 0ROG3DFNDJH7KLFNQHVV 3LWFK 6WDQGRII 8QLWV 'LPHQVLRQ/LPLWV E H %6& 5() 0,//,0(7(56 0,1 120 0$; 5() 5HIHUHQFH'LPHQVLRQXVXDOO\\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\\ %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV Notes: 3LQYLVXDOLQGH[IHDWXUHPD\\YDU\\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %DOO9HU\\9HU\\7KLQ)LQH3LWFK%DOO*ULG$UUD\\ :&; [PP%RG\\>:)%*$@ )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWS ZZZPLFURFKLSFRPSDFNDJLQJ 1RWH 2YHUDOO/HQJWK ([SRVHG3DG/HQJWK %6& %6& %6& %6&

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 2020 Microchip Technology Inc. DS00003392B-page 51 EEC1005 12.2 84 Pin WFBGA/SX1 Package Note: For the most current package dra wings, see the Microchip Packag ing Specification at http://www.micro- chip.com/packaging.

DS00003392B-page 52  2020 Microchip Technology Inc. APPENDIX A: DATA SHEET REVISION HISTORY TABLE A-1: REVISION HISTORY Revision Section/Figure/Entry Correction DS00003392B (05-06-20) Section 7.6, "Capabilities (0x33)" Register bits "2-Wire Reset” updated to 02h. Section 11.0, "Electrical Spec- ifications" Chapter added DS00003392A (02-26-20) Initial document

 2020 Microchip Technology Inc. DS00003392B-page 53 EEC1005 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con- tains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi- nars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi- cation” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu- ment. Technical support is available through the web site at: http://www.microchip.com/support

DS00003392B-page 54  2020 Microchip Technology Inc. PRODUCT IDENTIFICATION SYSTEM Not all of the possible combinations of Device, Temperature Range and Package may be offered for sale. To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.(1) Device Device: EEC1005 (1) UBM Controller Total SRAM: H 256KB Version/ Revision: B# B = Version, # = Version Revision Number Temperature Range: I/ = -40 oC to +85oC (Industrial) Package: WC 144 pin WFBGA 10x10mm body, 0.80mm pitch SX1 84 pin WFBGA 7x7mm body, 0.65mm pitch Tape and Reel Option: Blank = Tray packaging TR = Tape and Reel (3) Example: a) EEC1005-I/WC = EEC1005 with 12-drive UBM solution provided with FW Temp Range/ Package Note 1: These products meet the halogen maximum concentration values per IEC61249-2-21. 2: All package options are RoHS compliant. For RoHS compliance and environmental information, please visit http://www.micro- chip.com/pagehandler/en- us/aboutus/ehs.html 3: Tape and Reel identifier only appears in the catalog part number description. This identi- fier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option - X - X Tape and Reel Option Total SRAM XX - - X/XXX(2) Version/ Revision

 2020 Microchip Technology Inc. <Redtext> DS00003392B-page 55 EEC1005 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro- chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRa te, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chip KIT logo, CryptoMemory, CryptoRF, dsPIC, F lashFlex, flexPWR, HELDO, IGLOO , JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouc h, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, M PLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 log o, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC , SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherS ynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMO S, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProAS IC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, a nd ZL are registered trademarks of Microchip Technology Incorpo rated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutom otive, CryptoCompanion, Crypto Controller, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, D AM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet log o, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ri pple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperS witcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technolo gy, and Symmcom are registered trademarks of Microchip Technolo gy Inc. in other countries. GestIC is a registered trademark of Microchip Technology German y II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020, Microchip Technology Incorporated, All Rights Reserved. ISBN: 9781522458968 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the spec ification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the m ost secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breac h the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerne d about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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