ECLTSSOP20EVB ONSEMI | Alldatasheet
Document overview
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Technical content
1 Publication Order Number:
device under test (see Table 1. Configuration List).
- Information on 20-lead TSSOP Evaluation Board
- Assembly Instructions
- Appropriate Lab Setup
- Bill of Materials This manual should be used in conjunction with the device data sheet, which contains full technical details on the device specifications and operation. Board Lay-Up The 20-lead TSSOP evaluation board is implemented in four layers with split (dual) power supplies (see Figure 3. Evaluation Board Lay-Up). For standard ECL lab setup and test, a split (dual) power supply is essential to enable the 50 internal impedance in the oscilloscope as a termination for ECL devices. The first layer or primary trace layer is 0.008″ thick Rogers RO4003 material, which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz copper ground. The FR4 dielectric material is placed between second and third layer and between third and fourth layer. The third layer is the power plane (V CC & VEE ) and a portion of this layer is a ground plane. The fourth layer is the secondary trace layer.
Figure 1. Top View of the 20-lead TSSOP Evaluation Board
Figure 2. Bottom View of the 20-lead TSSOP Evaluation Board Figure 3. Evaluation Board Lay-up
4 LAYER
versatile and accommodate several different configurations. F and C1, C2, and C3 are 0.1F); (See Figure 5).
Figure 4. Evaluation Board Layout
Figure 5. Enlarged Bottom View of the Evaluation Board Table 1. Configuration List
1 See Figure 6 EP14, LVEP14
2 See Figure 7 EP17, LVEP17
3 See Figure 8 EP29
4 See Figure 9 EP40
5 See Figure 10 EP56, LVEP56
6 See Figure 11 EP57
7 See Figure 12 EP139
Materials for this evaluation board. device to the evaluation board. –1.3 V; see Table 2, Power Supply Levels). Table 2. Power Supply Levels C5 to reduce the unwanted noise from the power supplies. vertical (side) position, instead of its original or flat position. imperfect alignment and soldering of the SMA connector.
Figure 6. Configuration 1
0603 CHIP
0805 CHIP
0402 CHIP
Table 3. Configuration 1 (Device EP14 and LVEP14)
Figure 7. Configuration 2 Table 4. Configuration 2 (Device EP17 and LVEP17)
Figure 8. Configuration 3 Table 5. Configuration 3 (Device EP29)
Figure 9. Configuration 4 Table 6. Configuration 4 (Device EP40) (Options 1 & 2)
Figure 10. Configuration 5 Table 7. Configuration 5 (Device EP56 and LVEP56)
Figure 11. Configuration 6 Table 8. Configuration 6 (Device EP57)
Figure 12. Configuration 7 Table 9. Configuration 7 (Device EP139)
Figure 13. Example of Standard Lab Setup (Configuration 1)
- Connect appropriate power supplies to VCC , VEE ,
- Connect a signal generator to the input SMA
- Connect a test measurement device on the device
Table 10. Power Supply Levels
Table 11. Bill of Materials
Figure 14. Gerber Files
Figure 15. Gerber Files
http://onsemi.com Notes
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