ECLSOIC8EVB ONSEMI | Alldatasheet
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device under test (See Table 1. Configuration List).
- Information on 8−lead SOIC Evaluation Board
- Assembly Instructions
- Appropriate Lab Setup
- Bill of Materials This manual should be used in conjunction with the device data sheet, which contains full technical details on the device specifications and operation. Board Lay−Up The 8−lead SOIC evaluation board is implemented in four layers with split (dual) power supplies (Figure 2. Evaluation Board Lay−up). For standard ECL lab setup and test, a split (dual) power supply is essential to enable the 50 internal impedance in the oscilloscope as a termination for ECL devices. The first layer or primary trace layer is 0.008″ thick Rogers RO4003 material, which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz copper ground plane and a portion of the plane is the V EE power plane. The FR4 dielectric material is placed between second and third layer and between third and fourth layer. The third layer is also 1.0 oz copper ground plane and a portion of this layer is V CC power plane. The fourth layer is the secondary trace layer.
Figure 1. Top and Bottom View of the 8−lead SOIC Evaluation Board
Figure 2. Evaluation Board Lay−up
4 LAYER
versatile and accommodate several different configurations. figures. (C1 and C2 are 0.01 F and C3 and C4 are 0.1 F). Figure 3. Evaluation Board Layout
Table 1. Configuration List
contains the Bill of Materials for this evaluation board. –1.3 V; see Table 2: Power Supply Levels). Table 2. Power Supply Levels Table 3. Power Supply Levels for Translators device. The VEE clip connects directly to pin 5 of the device. C2 to reduce the unwanted noise from the power supplies. R2, R3, R4, R6, and R7, depending on the specific device. soldering of the SMA connector.
Figure 4. Configuration 1 Schematic Table 4. Configuration 1
Figure 5. Configuration 2 Schematic Table 5. Configuration 2
Figure 6. Configuration 3 Schematic Table 6. Configuration 3
Figure 7. Configuration 4 Schematic Table 7. Configuration 4
Figure 8. Configuration 5 Schematic Table 8. Configuration 5
Figure 9. Configuration 6 − Translator Schematic Table 9. Configuration 6
Figure 10. Configuration 7 − Translator Schematic Table 10. Configuration 7 *See Appendix for loaded testing condition.
Figure 11. Configuration 8 − Translator Schematic Table 11. Configuration 8
Figure 12. Configuration 9 − Translator Schematic Table 12. Configuration 9 *See Appendix for loaded testing condition.
Figure 13. Configuration 10 − Translator Schematic Table 13. Configuration 10 *See Appendix for loaded testing condition.
Figure 14. Configuration 11 − Translator Schematic Table 14. Configuration 11
Figure 15. Example of Standard Lab Setup (Configuration 1)
- Connect appropriate power supplies to VCC , VEE ,
Table 15. Power Supply Levels slight modification as indicated in Table 16. Table 16. Power Supply Levels for Translators
- Connect a signal generator to the input SMA
- Connect a test measurement device on the device
Table 17. Bill of Materials
http://onsemi.com Appendix A (Modified Configurations) MC10EL16D/MC100EL16D MC100LVEL16D MC10EP16D/MC100EP16D MC10EP16DF/MC100EP16DF MC100EP16VAD MC100LVEP16D The devices listed above have the option of being driven single−endedly by using the provided VBB pin of the device. In order to drive it single−endedly, Configuration 2 needs to be modified. 1. Remove the 50 chip resistor from R3. 2. Short pin 3 and pin 4 together. Option A) Short R3 and R4 trace pads. Or Option B) Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors. MC10EP16D/MC100EP16DT This device has an option of being 50 terminated internally. To evaluate the internal 50 resistor of the device, Configuration 2 needs to be modified. 1. Remove the 50 chip resistors from R2 and R3. 2. Short R1 and R4 to VTT (GND). Option A) Short R1 and R4 to VTT (GND). Or Option B) Place SMA connectors on J1 and J4. Place shorting barrels on J1 and J4 SMA connector. MC100EP16VBD This device has an option of single−ended feedback output and being driven single−endedly using the VBB . To utilize the feedback option and drive it single−endedly, Configuration 2 needs to be modified. Feedback option 1. Connect a SMA connector on J1 Drive single−endedly 2. Remove the 50 chip resistor from R3. 3. Short pin 3 and pin 4 together. Option A) Short R3 and R4. Or Option B) Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors. MC100EP16VCD This device has an option of single−ended feedback output with an enable pin. To utilize the feedback option and enable option, Configuration 5 needs to be modified. 1. Connect a SMA connector on J1. 2. Remove the 50 chip resistor from R3. MC100EP16VSD This device has an option of varying the output swing amplitude and being driven single−endedly. In order to utilize these options, Configuration 2 needs to be modified. Output Swing Control 1. Connect a SMA connector on J1 2. Add a decoupling capacitor between J1 and V CC (0.01 F) Drive Single−Endedly 1. Remove the 50 chip resistor from R3. 2. Short pin 3 and pin 4 together. Option A) Short R3 and R4. Or Option B) Place a SMA connector on J4 and use a cable with SMA connectors to short J3 and J4 connectors. MC100EP16VTD This device has an option of varying the output swing amplitude and internal termination. In order to utilize these options, Configuration 2 needs to be modified. Output Swing Control 1. Connect a SMA connector on J1 2. Add a decoupling capacitor between J1 and V CC (0.0 1 F) Internal Termination 1. Remove the 50 chip resistors from R2 and R3. 2. Short R1 and R4 to VTT (GND) Option A) Short R1 and R4 to VTT (GND). Or Option B) Place SMA connectors on J1 and J4. Place shorting barrels on J1 and J4 SMA connector. MC10ELT21D/MC100EL21D MC100EL23D MC10ELT26D/MC100ELT26D MC100EPT21D MC100EPT23D MC100EPT26D MC100LVELT23 The TTL output data presented in the data sheet are obtained under 500 load resistor in parallel with 20 pF fixture capacitance. In order to obtain comparable data as in the data sheet, the evaluation board needs to be modified. 1. Cut the output trace so that the 0402* size chip resistor can be placed over the cut out trace. 2. Solder a 450 chip resistor across the cut out trace. *Any size chip resistor can be used. The recommended size of the chip resistor is 0402, to reduce the effect of parasitic with a 17 mil trace width. 450 in series with 50 instrument resistance add up to 500 loaded condition.
Figure 16. Gerber Files
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