ECLLQFP32EVB ONSEMI | Alldatasheet
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Technical content
1 Publication Order Number:
device under test (see Table 1. Configuration List).
- Information on 32-lead LQFP Evaluation Board
- Assembly Instructions
- Appropriate Lab Setup
- Bill of Materials This manual should be used in conjunction with the device data sheet, which contains full technical details on the device specifications and operation. Board Lay-Up The 32-lead LQFP evaluation board is implemented in four layers with split (dual) power supplies (see Figure 3. Evaluation Board Lay-Up). For standard ECL lab setup and test, a split (dual) power supply is essential to enable the 50 internal impedance in the oscilloscope as a termination for ECL devices. The first layer or primary trace layer is 0.008″ thick Rogers RO4003 material, which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz copper ground. The FR4 dielectric material is placed between second and third layer and between third and fourth layer. The third layer is the power plane (V CC & VEE ) and a portion of this layer is a ground plane. The fourth layer is the secondary trace layer.
Figure 1. Top View of the 32-lead LQFP Evaluation Board
Figure 2. Bottom View of the 32-lead LQFP Evaluation Board Figure 3. Evaluation Board Lay-up
4 LAYER
versatile and accommodate several different configurations. F and C1, C2, and C3 are 0.1F); (See Figure 5).
Figure 4. Evaluation Board Layout
Figure 5. Enlarged Bottom View of the Evaluation Board Table 1. Configuration List
1 See Figure 6 LVE164
2 See Figure 7 EP016 / EP016A
3 See Figure 8 EP101 / EP105
4 See Figure 9 EP116
5 See Figure 10 EP131
6 See Figure 11 EP142
7 See Figure 12 EP195 / EP196
8 See Figure 13 EP445
9 See Figure 14 EP446
10 See Figure 15 EP451
11 See Figure 16 EP809
12 See Figure 17 LVEP111 / LVEP210
13 See Figure 18 LVEP210S
Materials for this evaluation board. device to the evaluation board. –1.3 V; see Table 2, Power Supply Levels). Table 2. Power Supply Levels C5 to reduce the unwanted noise from the power supplies. vertical (side) position, instead of its original or flat position. imperfect alignment and soldering of the SMA connector.
Figure 6. Configuration 1
0402 CHIP
0805 CHIP
0603 CHIP
Table 3. Configuration 1 (Device LVE164)
Figure 7. Configuration 2 Table 4. Configuration 2 (Device EP016 and EP016A)
Figure 8. Configuration 3 Table 5. Configuration 3 (Device EP101 and EP105)
Figure 9. Configuration 4 Table 6. Configuration 4 (Device EP116)
Figure 10. Configuration 5 Table 7. Configuration 5 (Device EP131)
Figure 11. Configuration 6 Table 8. Configuration 6 (Device EP142)
Figure 12. Configuration 7 Table 9. Configuration 7 (Device EP195 and EP196)
Figure 13. Configuration 8 Table 10. Configuration 8 (Device EP445)
Figure 14. Configuration 9 Table 11. Configuration 9 (Device EP446)
Figure 15. Configuration 10 Table 12. Configuration 10 (Device EP451)
Figure 16. Configuration 11 Table 13. Configuration 11 (Device EP809)
Figure 17. Configuration 12 Table 14. Configuration 12 (Device LVEP111 and LVEP210)
Figure 18. Configuration 13 Table 15. Configuration 13 (Device LVEP210S)
Figure 19. Example of Standard Lab Setup (Configuration 12)
- Connect appropriate power supplies to VCC , VEE ,
- Connect a signal generator to the input SMA
- Connect a test measurement device on the device
Table 16. Power Supply Levels Table 17. Bill of Materials
Figure 20. Gerber Files
Figure 21. Gerber Files
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