ECJ2FB0J226M

TPS51463 TI1 | Alldatasheet

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+5V PGOOD TPS51463 www.ti.com SLUSAX2 –FEBRUARY 2012 3.3-V/5-VInput,D-CAP+™ ModeSynchronousStep-DownIntegratedFETsConverter With2-BitVID Check forSamples: TPS51463 1FEATURES DESCRIPTION The TPS51463 isa fullyintegratedsynchronousbuck 23• IntegratedFETs Converterw/TIProprietary regulatoremployingD-CAP+ ™ .Itisused forup to5-D-CAP+ ™ Mode Architecture V step-down where system sizeis at itspremium,• Minimum ExternalPartsCount performanceand optimizedBOM aremust-haves.

• Support allMLCC Output Capacitorand The TPS51463 fullysupportsthe Intel® ChiefRiverSP/POSCAP platform,a ULV/CPU system agent applicationwith
• Auto Skip Mode integrated2-bitVID function.
• Selectable700-kHz and 1-MHz Frequency The TPS51463 alsofeaturestwo switchingfrequency
• Small 4 mm × 4 mm, 24-Pin,QFN Package settings(700 kHz and 1 MHz), skipmode, pre-bias startup,programmable externalcapacitorsoft-start time/voltagetransitiontime,outputdischarge,internalAPPLICATIONS VBST Switch,2-V reference(±1%), power good and• Low-VoltageApplicationsSteppingDown from enable.5-V or 3.3-VRail The TPS51463 isavailableina 4 mm × 4 mm, 24-• Notebook/Desktop Computers pin,QFN package (Green RoHs compliantand Pb• Intel® ChiefRiverPlatformULV CPU System free)and isspecifiedfrom-40°C to85°C. Agent Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2D-CAP+ isa trademarkofTexas Instruments. 3Intelisa registeredtrademarkofIntelCorporation. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLUSAX2 –FEBRUARY 2012 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ORDERING INFORMATION (1) MINIMUMTA PACKAGE (2) ORDERING NUMBER PINS OUTPUT SUPPLY ECO PLANQUANTITY TPS51463RGER 24 Tape and reel 3000 Green (RoHS andPlasticQFN-40°C to85°C no Pb/Br)(RGE) TPS51463RGET 24 Minireel 250 (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orvisittheTI websiteatwww.ti.com. (2) Package drawings,standardpackingquantities,thermaldata,symbolization,and PCB designguidelinesareavailableat www.ti.com/sc/package. THERMAL INFORMATION TPS51463 THERMAL METRIC (1) UNITS RGE (24)PIN θJA Junction-to-ambientthermalresistance 38.3 θJCtop Junction-to-case(top)thermalresistance 44.7 θJB Junction-to-boardthermalresistance 16 °C/W ψJT Junction-to-topcharacterizationparameter 0.8 ψJB Junction-to-boardcharacterizationparameter 16.1 θJCbot Junction-to-case(bottom)thermalresistance 5.4 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT MIN MAX VIN,EN, MODE –0.3 7.0 V5DRV, V5FILT,VBST (withrespecttoSW) –0.3 7.0 Inputvoltagerange VBST –0.3 12.5 V VID0,VID1 –0.3 3.6 VOUT –1.0 3.6 SW –2.0 7.0 SW (transient20 ns and E=5 µJ) –3.5 Outputvoltagerange COMP, SLEW, VREF –0.3 3.6 V PGND –0.3 0.3 PGOOD –0.3 7.0 Human Body Model (HBM) 2000 ElectrostaticDischarge V Charged DeviceModel (CDM) 500 Storagetemperature Tstg –55 150 ˚C Junctiontemperature TJ –40 150 ˚C Lead temperature1,6mm (1/16inch)fromcase for10 seconds 300 ˚C (1) Stressesbeyond thoselistedunder“absolutemaximum ratings”may cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder“recommended operating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.

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www.ti.com SLUSAX2 –FEBRUARY 2012 RECOMMENDED OPERATING CONDITIONS VALUE UNIT MIN TYP MAX VIN,EN, MODE –0.1 6.5 V5DRV, V5FILT,VBST(withrespecttoSW) –0.1 5.5 Inputvoltagerange VBST –0.1 11.75 V VID0,VID1 –0.1 3.5 VOUT –0.8 2.0 SW –0.8 6.5 COMP, SLEW, VREF –0.1 3.5 Outputvoltagerange V PGOOD –0.1 6.5 PGND –0.1 0.1 Ambienttemperaturerange,TA -40 85 °C

ELECTRICAL CHARACTERISTICS

overrecommended free-airtemperaturerange,VVIN = 5.0V,VV5DRV = VV5FILT = 5 V,MODE = OPEN, PGND = GND (unless otherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY: VOLTAGE, CURRENTS AND 5 V UVLO IVINSD Inputvoltageshutdowncurrent EN = 'LO ' 0.02 5 µA V5VIN 5-V supplyvoltage V5DRV and V5FILT voltagerange 4.5 5.0 5.5 V I5VIN 5-V supplycurrent EN =’HI’,V5DRV + V5FILT supplycurrent 1.6 3.0 mA I5VINSD 5-V shutdowncurrent EN = ‘LO ’,V5DRV + V5FILT shutdowncurrent 10 50 µA VV5UVLO V5FILT pinundervoltagelockout Ramp up;EN = 'HI' 4.2 4.3 4.5 V V5FILT undervoltagelockoutVV5UVHYS Fallinghysteresis 440 mVhysteresis VVREFUVLO Referenceundervoltagelockout(1) Risingedge ofVREF, EN = 'HI' 1.8 V VVREFUVHYS Referenceundervoltagehysteresis(1) 100 mV VPOR5VFILT Reset OVP latchisresetby V5FILT fallingbelowtheresetthreshold 1.5 2.3 3.1 V VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER VOUTTOL Outputvoltageaccuracy VVOUT = 0.85V –1.5% 0% 1.5% VVREF Referencevoltage IVREF = 0 µA,TA = 25°C 2 V G M Transconductance 1 mS VDM Differentialmode inputvoltage 0 80 mV ICOMPSRC COMP pinmaximum sourcingcurrent VCOMP = 2 V –80 µA VOFFSET Inputoffsetvoltage TA = 25°C –5 0 5 mV R DSCH Outputvoltagedischargeresistance 42 Ω f–3dbVL –3dB Frequency(1) 6 MHz CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVER CURRENT AND ZERO CROSSING Gain fromthecurrentofthelow-sideFET toPWM comparatorACSINT Internalcurrentsense gain 43 50 59 mV/Awhen PWM = "OFF " IOCL Positiveovercurrentlimit(valley) 4.0 5.5 A IOCL(neg) Negativeovercurrentlimit(valley) –5 A VZXOFF Zerocrossingcomp internaloffset 0 mV DRIVERS: BOOT STRAP SWITCH R DSONBST InternalBST switchon-resistance IVBST = 10 mA, TA = 25°C 5 10 Ω IBSTLK InternalBST switchleakagecurrent VVBST = 14 V,VSW = 7 V,TA = 25°C 1 µA (1) Ensuredby design,notproductiontested. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TPS51463

SLUSAX2 –FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overrecommended free-airtemperaturerange,VVIN = 5.0V,VV5DRV = VV5FILT = 5 V,MODE = OPEN, PGND = GND (unless otherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN PGOOD deasserttolowerVPGDLL Measured attheVOUT pinw/r/tVSLEW 82% 84% 86%(PGOOD → Low) VPGHYSHL PGOOD highhysteresis 8% PGOOD de-asserttohigherVPGDLH Measured attheVOUT pinw/r/tVSLEW 114% 116% 118%(PGOOD → Low) VPGHYSHH PGOOD highhysteresis -8% Minimum inputvoltageforvalid Measured attheVIN pinwitha 2-mA sinkcurrenton PGOODVINMINPG 0.9 1.3 1.5 VPGOOD pin VOVP Overvoltageprotectionthreshold Measured attheVOUT pinw/r/tVSLEW 118% 120% 122% Measured attheVOUT pinw/r/tVSLEW ,devicelatchesOFF,VUVP Undervoltageprotectionthreshold 66% 68% 70%beginssoft-stop TH SD Thermalshutdown(2) Latchoffcontroller,attemptsoft-stop. 125 °C TH SD(hys) Thermalshutdownhysteresis(2) Controllerre-startsaftertemperaturehas dropped 10 °C TIMERS: ON-TIME, MINIMUM OFF TIME, SS, AND I/OTIMINGS VVIN = 5 V,VVOUT = 0.85V,fSW = 667 kHz,fixedVID mode 255 ns tONESHOTC PWM one-shot(2) VVIN = 5 V,VVOUT = 0.85V,fSW = 1 MHz, fixedVID mode 170 ns VVIN = 5 V,VVOUT = 0.85V,fSW = 1 MHz, DRVL on,tMIN(off) Minimum OFF time(2) 357 nsSW = PGND, VVOUT < VSLEW PGOOD startupdelaytime(2)(excl. DelaystartsfromVOUT = VID code 00 and excludesSLEWtPGDDLY 3 msSLEW ramp up time) ramp up time PGOOD highpropagationdelaytPGDPDLYH 50 mV overdrive,risingedge 0.8 1 1.2 mstime(2) tPGDPDLYL PGOOD lowpropagationdelaytime(2) 50 mV overdrive,fallingedge 10 µs tOVPDLY Overvoltageprotectiondelaytime(2) Time fromtheVOUT pinoutof+20% ofVSLEW toOVP fault 0.2 µs Undervoltagefaultenabledelay(excl.Time from(VOUT = VID code 00)goinghightoundervoltagetUVDLYEN 3 msSLEW ramp up time)(2) faultisready tUVPDLY Undervoltageprotectiondelaytime(2) Time fromtheVOUT pinoutof–30% ofVSLEW toUVP fault 8.5 µs ISLEW Soft-startand voltagetransition C SS = 10 nF assumingvoltageslewrateof1 mV/µs 9 10 11 µA LOGIC PINS: I/OVOLTAGE AND CURRENT VPGDPD Power good pulldown voltage PGOOD lowimpedance,ISINK = 4 mA, VVIN = VV5FILT = 4.5V 0.3 V IPGDLKG Power good leakagecurrent PGOOD highimpedance,forcedto5.5V –1 0 1 µA VENH High-levelEN logic EN, VCCP logic 0.8 V VENL Low-levelENlogic EN, VCCP logic 0.3 V IEN EN inputcurrent 1 µA VVIDH High-levelinputVID logic VID0,VID1 0.8 V VVIDL Low-levelinputVID logic VID0,VID1 0.3 V VMODETH MODE thresholdvoltage(3) MODE 7 1.75 1.80 1.85 V IMODE MODE current 15 µA R PD VID pull-downresistance 10 kΩ (2) Ensuredby design,notproductiontested. (3) See Table3 fordescriptionsofMODE parameters.

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www.ti.com SLUSAX2 –FEBRUARY 2012 RGE PACKAGE PIN FUNCTIONS PIN I/O DESCRIPTION NO. NAME 20 PGND I Power ground.Sourceterminaloftherectifyinglow-sidepower FET. 23 VIN I Power supplyinputpin.Drainterminaloftheswitchinghigh-sidepower FET. 1 GND – Signalground. 2 VREF O 2.0-Vreferenceoutput.Connecta 0.22-µF ceramiccapacitortoGND. 3 COMP O ConnectseriesR-C totheVREF pinforloopcompensation. 4 SLEW I/O Program thestartupand voltagetransitiontimeusingan externalcapacitorvia10-µA currentsource. 5 VOUT I Outputvoltagemonitorinputpin. 6 MODE I Allowsselectionofswitchingfrequencies.(See Table3) 9 SW I/O Switchingnode output.Connecttotheexternalinductor. 12 Power supplyforinternalhigh-sidegatedriver.Connecta 0.1-µF bootstrapcapacitorbetween thispinandBST I theSW pin. 13 EN I EnableoftheSMPS.

14 VID0

I 2-bitVID input.

15 VID1

16 PGOOD O Power good output.Connectpull-upresistor. 17 V5FILT I 5-V power supplyforanalogcircuits. 18 V5DRV I 5-V power supplyforthegatedriver. ThermalPad – ConnectdirectlytosystemGND planewithmultiplevias. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TPS51463

12 BST

18 V5DRV

16 PGOOD

VREFIN +20% VOUT VIN tON One- Shot UV OV VREFIN –32% 4SLEW 8 R 3COMP R 1GND 2VREF On-Time and LL Selection 15 /c109A

6 MODE

VREFIN +8/16 % VREFIN –8/16 % Discharge UVP OVP

17 V5FILT

20 PGND

21 PGND

SLUSAX2 –FEBRUARY 2012 www.ti.com BLOCK DIAGRAM Table1.IntelSA VID forIntel® ChiefRiverPlatformULV CPU System Agent VID 0 VID 1 VCCSA (V) 0 0 0.9 0 1 0.85 1 0 0.775 1 1 0.75

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0.1 /c109F DNP L 0.42 /c109H /c109F DNP DNP VCCSA VCCSASNS UDG-12019 0.22 /c109F 10 nF ENABLE VID VID 1+5V /c87 /c109F PGOOD 0.1 /c109F /c109F /c109F VIN /c109F /c109F /c109F 2.2 /c109F 100 k/c87 3.3 nF 1 k /c87 100 /c87 1 k /c87 Thermal Pad 5 k /c87 TPS51463 www.ti.com SLUSAX2 –FEBRUARY 2012 TPS51463 APPLICATION DIAGRAM Figure1. TypicalApplication Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TPS51463

SLUSAX2 –FEBRUARY 2012 www.ti.com ApplicationCircuitListofMaterials Recommended partnumbers forkey externalcomponents forthecircuitinFigure1 arelistedinTable2. Table2.Key ExternalComponent Recommendations (Figure1) FUNCTION MANUFACTURER PART NUMBER OutputInductor Nec-Tokin MPCG0740LR42C Panasonic ECJ2FB0J226M CeramicOutputCapacitors Murata GRM21BR60J226ME39L

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Time (/c109s) Voltage (V) Current Feedback tON t VCS VCOMP UDG-10187 VREF TPS51463 www.ti.com SLUSAX2 –FEBRUARY 2012

APPLICATION INFORMATION

The TPS51463 isa D-CAP+ ™ mode adaptiveon-timeconverter.The outputvoltageissetusinga 2-bitDAC that outputsa referencevoltagein accordance withthe code definedin Table 1. VID-on-the-flytransitionsare supportedwiththeslewratecontrolledby a singlecapacitoron theSLEW pin.The converterautomaticallyruns indiscontinuousconductionmode (DCM) to optimizelight-loadefficiency.Two switchingfrequencyselections are provided,(700 kHz and 1 MHz) toenableoptimizationofthepower chainforthecost,sizeand efficiency requirementsofthedesign. In adaptiveon-timeconverters,the controllervariesthe on-timeas a functionof inputand outputvoltageto maintaina nearlyconstantfrequencyduringsteady-stateconditions.Inconventionalconstanton-timeconverters, each cyclebeginswhen theoutputvoltagecrossestoa fixedreferencelevel.However, intheTPS51463, the cyclebeginswhen thecurrentfeedbackreachesan errorvoltagelevelwhichistheamplifieddifferencebetween thereferencevoltageand thefeedbackvoltage. PWM Operation ReferringtoFigure2,insteadystate,continuousconductionmode, theconverteroperatesinthefollowingway. StartingwiththeconditionthatthetopFET isoffand thebottomFET ison,thecurrentfeedback(VCS )ishigher thantheerroramplifieroutput(VCOMP ).VCS fallsuntilithitsVCOMP ,which containsa component oftheoutput ripplevoltage.VCS isnotdirectlyaccessibleby measuringsignalson pinsofTPS51463. The PWM comparator senseswhere thetwo waveformscrossand triggerstheon-timegenerator. Figure2. D-CAP+ ™ Mode Basic Waveforms The currentfeedbackisan amplifiedand filteredversionofthevoltagebetween PGND and SW duringlow-side FET on-time.The TPS51463 alsoprovidesa single-endeddifferentialvoltage(VOUT ) feedbacktoincreasethe systemaccuracyand reducethedependence ofcircuitperformanceon layout. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TPS51463

/c61 /c180OUT ON IN SW V 1t V f VSLEW RC + PWM Comparator RDS(on) GMV = 1 mS Driver LOUT ESR COUT ROUT UDG-11208 RLOAD 4 k/c87 GMC= 1 mS CC VREF TPS51463 SLUSAX2 –FEBRUARY 2012 www.ti.com PWM Frequency and Adaptiveon Time Control Ingeneral,theon-time(attheSW node)can be estimatedby Equation1. where

• fSW isthefrequencyselectedby theconnectionoftheMODE pin (1) The on-timepulseissentto the top FET. The inductorcurrentand the currentfeedbackrisesto peak value. Each ON pulseislatchedtopreventdoublepulsing.Switchingfrequencysettingsareshown inTable3. Non-Droop Configuration The TPS51463 offersa non-droopsolutiononly.The benefitofa non-droopapproachisthatloadregulationis flat,therefore,ina systemwhere tightDC toleranceisdesired,thenon-droopapproachisrecommended. Forthe Intelsystemagentapplication,non-droopisrecommended as thestandardconfiguration. The non-droopapproachcan be implementedby connectinga resistorand a capacitorbetween theCOMP and theVREF pins.The purposeofthetypeIIcompensationistoobtainhighDC feedbackgainwhileminimizingthe phase delayatunitygaincrossoverfrequencyoftheconverter. The valueoftheresistor(RC )can be calculatedusingthedesiredunitygainbandwidthoftheconverter,and the valueofthecapacitor(CC )can be calculatedby knowingwhere thezerolocationisdesired.An applicationtool thatcalculatesthesevaluesisavailablefromyourlocalTIFieldApplicationEngineer. Figure3 shows thebasicimplementationofthenon-droopmode usingtheTPS51463. Figure3. Non-Droop Mode Basic Implementation

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0.75 0.80 0.85 0.90 0.1 1 10 Output Current (A) Output Voltage (V) Mode 7, VIN = 5 V Mode 8, VIN = 5 V Mode 7, VIN = 3.3 V Mode 8, VIN = 3.3 V TA = 25°C G005 TPS51463 www.ti.com SLUSAX2 –FEBRUARY 2012 Figure4 shows theloadregulationofthesystemagentrailusingnon-droopconfiguration. Figure5 shows thetransientresponseofTPS51463 usingnon-droopconfigurationwhere C OUT = 4 × 22 µF.The appliedsteploadisfrom0 A to2 A. Figure4.0.85-VLoad Regulation Figure5.TransientResponse Table3.Mode Parameter Table SWITCHING VID1 = 1MODE MODE CONNECTION FREQUENCY (fSW ) VID0 = 0 7 100 kΩ 700 kHz 0.85V 8 Open 1 MHz 0.85V Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TPS51463

/c61 SLEW SLEW IC SR /c180/c61 SLEW SS SLEW C 0.9 Vt I TPS51463 SLUSAX2 –FEBRUARY 2012 www.ti.com LightLoad Power Saving Features The TPS51463 has an automaticpulse-skippingmode to provideexcellentefficiencyover a wide loadrange. The convertersenses inductorcurrentand preventsnegativeflowby shuttingoffthelow-sidegatedriver.This saves power by eliminatingre-circulationof the inductorcurrent.Further,when the bottom FET shutsoff,the converterentersdiscontinuousmode, and theswitchingfrequencydecreases,thusreducingswitchinglossesas well. VoltageSlewing The TPS51463 ramps theSLEW voltageup and down toperformtheoutputvoltagetransitioning.The timingis independentofswitchingfrequency,as wellas outputresistiveand capacitiveloading.Itissetby a capacitor fromSLEW pintoGND, calledC SLEW ,togetherwithan internalcurrentsourceof10 µA. The slewrateisused to setthestartupand voltagetransitionrate. (2) where

• ISLEW = 10 µA (nom)
• SR isthetargetoutputvoltageslewrate,perIntelspecificationbetween 0.5mV/µs and 10 mV/µs (3) For thecurrentreferencedesign,an SR of1 mV/µs istargeted.The C SLEW iscalculatedtobe 10 nF.The slower slew rateisdesiredtominimizelargeinductorcurrentperturbationduringstartupand voltagetransitioningthus reducingthepossibilityofacousticnoise. Afterthe power up, when VID1 istransitioningfrom 0 to 1, TPS51463 followsthe SLEW voltageenteringthe forcedPWM mode toactivelydischargetheoutputvoltagefrom0.9V to0.85V. The actualoutputvoltageslew rateisapproximatelythesame as thesetslewratewhilethebandwidthoftheconvertersupportsitand thereis no overcurrenttriggeredby additionalchargingcurrentflowingintotheoutputcapacitors.AfterSLEW transitionis completed,PWM mode ismaintainedfor64 µs (16clockcycleswhen thefrequencyis1 MHz) toensurevoltage regulation. ProtectionFeatures The TPS51463 offersmany featurestoprotecttheconverterpower chainas wellas thesystemelectronics. 5-V UndervoltageProtection(UVLO) The TPS51463 continuouslymonitorsthe voltageon the V5FILT pinto ensure thatthe voltagelevelishigh enough tobiasthedeviceproperlyand toprovidesufficientgatedrivepotentialtomaintainhighefficiency.The converterstartswithapproximately4.3V and has a nominalof440 mV ofhysteresis.Ifthe5-V UVLO limitis reached,theconvertertransitionsthephase node intoa 3-statefunction.And theconverterremainsintheoff stateuntilthedeviceisresetby cycling5 V untilthe5-V POR isreached(2.3-Vnominal).The power inputdoes nothave an UVLO function Power Good Signals The TPS51463 has one open-drainpower good (PGOOD) pin.Duringstartup,thereisa 3 ms power good delay startingfrom the outputvoltagereachingthe regulationpoint(excludingsoft-startramp-up time).And thereis alsoa 1 ms power good highpropagationdelay.The PGOOD pinde-assertsas soon as theEN pinispulledlow oran undervoltageconditionon V5FILT isdetected.The PGOOD signalisblankedduringVID voltagetransitions topreventfalsetriggeringduringvoltageslewing.

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/c40 /c41 /c40 /c41 /c45/c61 /c43 /c180 P POCL dc OCL valley 1I I I 2 TPS51463 www.ti.com SLUSAX2 –FEBRUARY 2012 Output OvervoltageProtection(OVP) Inadditiontothepower good functiondescribedabove,theTPS51463 has additionalOVP and UVP thresholds and protectioncircuits. An OVP conditionis detectedwhen the outputvoltageis approximately120% × VSLEW . In thiscase, the converterde-assertsthe PGOOD signalsand performsthe overvoltageprotectionfunction.The converter remainsinthisstateuntilthe deviceisresetby cycling5 V untilthe 5-V POR threshold(2.3V nominal)is reached. Output UndervoltageProtection(UVP) Output undervoltageprotectionworks in conjunctionwiththe currentprotectiondescribedin the Overcurrent Protectionand OvercurrentLimitsections.Iftheoutputvoltagedropsbelow 70% ofVSLEW ,afteran 8-µs delay, thedevicelatchesOFF. Undervoltageprotectioncan be resetonlyby EN ora 5-V POR. OvercurrentProtection Bothpositiveand negativeovercurrentprotectionareprovidedintheTPS51463:

• OvercurrentLimit(OCL)
• NegativeOCL (levelsame as positiveOCL) OvercurrentLimit Ifthesensed currentvalueisabove theOCL setting,theconverterdelaysthenextON pulseuntilthecurrent drops below the OCL limit.Currentlimitingoccurson a pulse-by-pulsebasis.The TPS51463 uses a valley currentlimitingscheme where theDC OCL trippointistheOCL limitplushalfoftheinductorripplecurrent.The minimum valleyOCL is4 A overprocessand temperature. Duringtheovercurrentprotectionevent,theoutputvoltagelikelydroopsuntiltheUVP limitisreached.Then,the converterde-assertsthePGOOD pin,and thenlatchesOFF afteran 8-µs delay.The converterremainsinthis stateuntilthedeviceisresetby EN ora 5VFILT POR. (4) NegativeOCL The negativeOCL circuitactswhen theconverterissinkingcurrentfrom theoutputcapacitor(s).The converter continuestoactina valleymode, theabsolutevalueofthenegativeOCL setpointistypically-5A. Thermal Protection Thermal Shutdown The TPS51463 has an internaltemperaturesensor.When thetemperaturereachesa nominal125°C, thedevice shutsdown untilthetemperaturecoolsby approximately10°C. Then theconverterrestarts. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TPS51463

0.95 V 1.05-V Rail 260 /c109s EN Internal Enable VID1 (3) VID0 (3) SLEW (1 mV//c109s) VOUT VCCSA_PGOOD UNCORE_PWRGD (1) 900 /c109s 4 ms 2.5 ms Reset Time (2) UDG-10191 TPS51463 SLUSAX2 –FEBRUARY 2012 www.ti.com Startupand VID TransitionTiming Diagrams Figure6. FixedVID/FixedStep Startupand VID Toggle Timing Diagram for2011 IntelPlatform ForFigure6: (1)IncludesVCCA, VCCAXG, and VDDQ power rails. (2)Processorreset:VID transitionmust be completedby thistime. (3)1-kΩ pull-downresistorrequired.

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0.95 V 1.05-V Rail 260 /c109s EN Internal Enable VID1 (3) VID0 (3) SLEW (1 mV//c109s) VOUT VCCSA_PGOOD UNCORE_PWRGD (1) 900 /c109s 4 ms 2.5 ms Reset Time (2) UDG-10192 100/c109s TPS51463 www.ti.com SLUSAX2 –FEBRUARY 2012 Figure7. FixedVID/FixedStep Startupand VID Toggle Timing Diagram for2012 IntelPlatform ForFigure7: (1)IncludesVCCA, VCCAXG, and VDDQ power rails. (2)Processorreset:VID transitionmust be completedby thistime. (3)1-kΩ pull-downresistorrequired. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TPS51463

0.01 0.1 1 10 Output Current (A) Efficiency (%) Mode 7 Mode 8 TA = 25°C VIN = 3.3 V VOUT = 0.85 V G001 0.01 0.1 1 10 Output Current (A) Efficiency (%) Mode 7 Mode 8 TA = 25°C VIN = 5 V VOUT = 0.85 V G002 0.0 0.2 0.4 0.6 0.8 1.0 0.01 0.1 1 10 Output Current (A) Power Loss (W) Mode 7 Mode 8 TA = 25°C VIN = 3.3 V VOUT = 0.85 V G003 0.0 0.2 0.4 0.6 0.8 1.0 0.01 0.1 1 10 Output Current (A) Power Loss (W) Mode 7 Mode 8 TA = 25°C VIN = 5 V VOUT = 0.85 V G004 100 120 140 1 2 3 4 5 Output Current (A) Ambient Temperature (°) Direct Current SOA OTP Boundary G006 110 160 210 260 310 360 -40 -30 -20 -10 -40 -50 Frequency (Hz) Gain Phase 25°C -10°C 85°C 1000 10 k 100 k 1 M 10 M Gain (dB) Phase (°) TPS51463 SLUSAX2 –FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS Figure8.Efficiencyvs.Output Current Figure9.Efficiencyvs.Output Current Figure10.Power Loss vs.Output Current Figure11.Power Loss vs.Output Current Figure12.Bode Plot Figure13.Safe OperatingArea

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www.ti.com SLUSAX2 –FEBRUARY 2012 TYPICAL CHARACTERISTICS (continued) Figure14.Mode=8, IOUT = 0 A, VID Transitioning Figure15.Mode=8, IOUT = 3 A, VID Transitioning Figure16.Mode = 8,OCL Figure17.Mode=7, OCL Figure18.Mode= 8,IOUT = 3 A, Soft-Start Figure19.Mode= 7,IOUT = 3 A, Soft-Start Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):TPS51463

P PI 4 A 0.375 1.5 A/c45 /c61 /c180 /c61 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 IN 10 SW IN P P P P V 0.85V V 5 0.85f V 1 5V dTL 0.47 HI I 1.5 A/c45 /c45 /c230 /c246 /c230 /c246 /c45 /c180 /c45 /c180/c231 /c247 /c231 /c247/c231 /c247 /c231 /c247 /c180 /c180/c180 /c232 /c248 /c232 /c248/c61 /c61 /c61 /c61 /c109 /c109/c61 /c61 /c61 /c109 SLEW SLEW DAC I 10 AC 10 nF 1 mVSR s TPS51463 SLUSAX2 –FEBRUARY 2012 www.ti.com DESIGN PROCEDURE The simplifieddesignprocedurestepsusingtheTPS51463 converterapplicationareoutlinedinthissection. Step One Determinethespecifications. The System AgentRailrequirementsprovidethefollowingkey parameters: 1. V00 = 0.90V 2. V10 = 0.85V 3. ICC(max) = 4 A 4. IDYN(max) = 2 A 5. ICC(tdc)= 3 A Step Two Determinesystemparameters. The inputvoltagerangeand operatingfrequencyareofprimaryinterest.Forexample: 1. VIN = 5 V 2. fSW = 1 MHz Step Three Determineinductorvalueand choose inductor. Smallervaluesofinductorhave bettertransientperformancebuthigherrippleand lowerefficiency.Highervalues have theoppositecharacteristics.Itiscommon practicetolimittheripplecurrentto25% to50% ofthemaximum current.Inthiscase,use 37.5%: (5) AtfSW = 1 MHz, witha 5-V inputand a 0.85-Voutput: (6) For thisapplication,a 0.42-µH, 1.55-mΩ inductorfrom NEC-TOKIN withpartnumber MPCG0740LR42C is chosen. Step Four Settheoutputvoltage. The outputvoltageisdeterminedby theVID settings.The actualvoltagesetpointforeach VID settingislistedin Table1.No externalresistordividersareneeded forthisdesign. Step Five CalculateC SLEW . VID pintransitionand soft-starttimeisdeterminedby C SLEW and 10 µA ofinternalcurrentsource. (7) The slowerslew rateis desiredto minimizelargeinductorcurrentperturbationduringstartupand voltage transition,thusreducingthepossibilityofacousticnoise.

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/c180 /c180/c61 /c61 /c61 /c109 /c109 SLEW SS SLEW C 0.9 V 10 nF 0.9 Vt 900 sI 10 A /c40 /c41 /c40 /c41 P POCL dc OCL valley 1 1I I I 4 A 1.5 A 4.75 A 2 2 /c45/c61 /c43 /c180 /c61 /c43 /c180 /c61 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c230 /c246 /c180/c231 /c247/c180 /c68 /c180 /c43 /c231 /c247 /c232 /c248/c61 /c230 /c246 /c230 /c246 /c45/c231 /c247 /c231 /c247/c180 /c68 /c180 /c180 /c45 /c180 /c231 /c247 /c231 /c247 /c232 /c248/c232 /c248

2 VOUT SW

OUT min_ under VOUTIN min SW VOUTLOAD insert MIN off IN min V tL I t V C V V

2 V t t V V

/c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c180 /c68 /c61 /c180 /c68 /c180 OUT LOAD max OUT min_ over VOUTLOAD release L I C 2 V V TPS51463 www.ti.com SLUSAX2 –FEBRUARY 2012 GiventheC SLEW ,use Equation8 tocalculatethesoftstarttime. (8) Step Six CalculateOCL. The DC OCL levelofTPS51463 designisdeterminedby Equation9, (9) The minimum valleyOCL is4 A over processand temperature,and IP-P = 1.5 A, the minimum DC OCL is calculatedtobe 4.75A. Step Seven Determinetheoutputcapacitance. To determineCOUT based on transientand stabilityrequirement,firstcalculatethe the minimum output capacitancefora giventransient. Equation11 and Equation10 can be used toestimatetheamount ofcapacitanceneeded fora givendynamic loadstep/release.Pleasenotethatthereareotherfactorsthatmay impacttheamount ofoutputcapacitancefor a specificdesign,such as rippleand stability.Equation11 and Equation10 are used onlyto estimatethe transientrequirement,theresultshouldbe used inconjunctionwithotherfactorsofthedesigntodeterminethe necessaryoutputcapacitancefortheapplication. (10) (11) Equation10 and Equation11 calculatethe minimum C OUT formeeting the transientrequirement,which is 78.6µF,giventhefollowingparameters:

• ±3% voltageallowanceforloadstepand release
• MLCC capacitancederatingof50% due toDC and AC biaseffect Inthisreferencedesign,4,22-µF capacitorsareused inordertoprovidethisamount ofcapacitance. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):TPS51463

/c61 /c180 /c180 /c61/c112 CM OUT S RG1f 150 kHz2 C R /c180 /c180 /c112 /c180 /c180 /c87 /c180 /c112 /c180 /c109/c61 /c61 /c187 /c870 S OUT C M f R 2 C 150 kHz 53m 2 88 FR 5 kG 1mS /c61 /c112 /c180 /c180 = 0 Z C C f1f 2 R C 10 TPS51463 SLUSAX2 –FEBRUARY 2012 www.ti.com Step Eight Determinethestabilitybased on theoutputcapacitanceC OUT . In orderto achievestableoperation.The 0-dB frequency,f0 shouldbe kept lessthan 1/5 of the switching frequency(1MHz). (See Figure3) where

• R S = R DS(on) × G MC × R LOAD (12) (13) Using4,22-µF capacitors,thecompensationresistance,R C can be calculatedtobe approximately5 kΩ. The purposeofthecomparatorcapacitor(CC )istoreducetheDC component toobtainhighDC feedbackgain. However, as itcauses phase delay,anotherzero to cancelthiseffectat f0 is needed. This zero can be determinedby valuesofC C and thecompensationresistor,R C . (14) And sinceR C has previouslybeen derived,thevalueofC C iscalculatedtobe 2.2nF. Inordertofurtherboost phase margin,a valueof3.3-nFischosen forthisreferencedesign. Step Nine Selectdecouplingand peripheralcomponents. For TPS51463 peripheralcapacitorsuse the followingminimum valuesof ceramiccapacitance.X5R or better temperaturecoefficientisrecommended. Tightertolerancesand highervoltageratingsarealwaysappropriate.
• V5DRV decoupling≥ 2.2µF,≥ 10 V
• V5FILT decoupling≥ 1 µF,≥10 V
• VREF decoupling0.22µF to1 µF,≥ 4 V
• Bootstrapcapacitors≥ 0.1µF,≥ 10 V
• Pull-upresistorson PGOOD, 100 kΩ Layout Considerations Good layoutisessentialforstablepower supplyoperation.Followtheseguidelinesforan efficientPCB layout.
• Connect PGND pins(oratleastone ofthepins)tothethermalPAD underneaththedevice.Alsoconnect GND pinto the thermalPAD underneaththe device.Use fourviasto connectthe thermalpad to internal groundplanes.
• PlaceVIN,V5DRV, V5FILT and 2VREF decouplingcapacitorsas closetothedeviceas possible.
• Use wide tracesfortheVIN,VOUT, PGND and SW pins.These nodes carryhighcurrentand alsoserveas heatsinks.
• Placefeedbackand compensationcomponents as closetothedeviceas possible.
• Keep analogsignals(SLEW, COMP) away fromnoisysignals(SW, VBST).

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www.ti.com 10-Mar-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS51463RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS51463RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 9-Mar-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51463RGER VQFN RGE 24 3000 346.0 346.0 29.0 TPS51463RGET VQFN RGE 24 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 9-Mar-2012 Pack Materials-Page 2

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