ADP5024 (Rev. A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 28
Technical content
Dual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO Data Sheet ADP5024 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
FEATURES
Main input voltage range: 2.3 V to 5.5 V Two 1200 mA buck regulators and one 300 mA LDO 24-lead, 4 mm × 4 mm LFCSP package Regulator accuracy: ±3% Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and automatic
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V LDO: output voltage range from 0.8 V to 5.2 V LDO: input supply voltage from 1.7 V to 5.5 V LDO: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices GENERAL DESCRIPTION The ADP5024 combines two high performance buck regula- tors and one low dropout (LDO) regulator in a small, 24-lead, 4 mm × 4 mm LFCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above a predefined threshold. When the load current falls below a pre- defined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. The two bucks operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the LDO extends the battery life of portable devices. The ADP5024 LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Regulators in the ADP5024 are activated though dedicated enable pins. The default output voltages can be either externally set in the adjustable version or factory programmable to a wide range of preset values in the fixed voltage version. TYPICAL APPLICATION CIRCUIT VIN1 VIN3 EN1 PWM PSM/PWM 2.3V TO 5.5V SW1 FB1 VOUT1 PGND1 MODE 10µF VOUT1 AT 1200mA VOUT2 AT 1200mA VOUT3 AT 300mA L1 1µH EN1 BUCK1 MODE 1µF 4.7µF 4.7µF AVIN CAVIN 0.1µF VIN2 EN2 AGND EN2 BUCK2 MODE EN3 1.7V TO 5.5V ON OFF ON OFF EN3 LDO (ANALOG) HOUSEKEEPING SW2 FB2 VOUT2 PGND2 10µF L2 1µH FB3 VOUT3 1µF ADP5024 09888-001 Figure 1.
Rev. A | Page 2 of 28 TABLE OF CONTENTS Input and Output Capacitor, Recommended Specifications .. 6
REVISION HISTORY
1/1—Re v. 0 to Rev. A Ch 8/11—R evision 0: Initial Version
Rev. A | Page 3 of 28 SPECIFICATIONS GENERAL SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; VIN3 = 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VAVIN, VIN1, VIN2 2.3 5.5 V THERMAL SHUTDOWN Threshold TSSD TJ rising 150 °C Hysteresis TSSD-HYS 20 °C START-UP TIME1 BUCK1, LDO tSTART1 250 µs BUCK2 tSTART2 300 µs EN1, EN2, EN3, MODE INPUTS Input Logic High VIH 1.1 V Input Logic Low VIL 0.4 V Input Leakage Current VI-LEAKAGE 0.05 1 µA INPUT CURRENT All Channels Enabled ISTBY-NOSW No load, no buck switching 108 175 µA All Channels Disabled ISHUTDOWN TJ = −40°C to +85°C 0.3 1 µA VIN1 UNDERVOLTAGE LOCKOUT High UVLO Input Voltage Rising UVLOVIN1RISE 3.9 V High UVLO Input Voltage Falling UVLOV IN1 FAL L 3.1 V Low UVLO Input Voltage Rising UVLOVIN1RISE 2.275 V Low UVLO Input Voltage Falling UVLOVIN1FAL L 1.95 V 1 Start-up time is defined as the time from EN1 = EN2 = EN3 from 0 V to VAVIN to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal levels. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.
Rev. A | Page 4 of 28 BUCK1 AND BUCK2 SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1 Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔVOUT1/VOUT1, ΔVOUT2/VOUT2 ILOAD1 = ILOAD2 = 0 mA to 1200 mA, PWM mode −3 +3 % Line Regulation (ΔVOUT1/VOUT1)/ΔVIN1, (ΔVOUT2/VOUT2)/ΔVIN2 PWM mode −0.05 %/V Load Regulation (ΔVOUT1/VOUT1)/ΔIOUT1, (ΔVOUT2/VOUT2)/ΔIOUT2 ILOAD = 0 mA to 1200 mA, PWM mode −0.1 %/A VOLTAGE FEEDBACK VFB1, VFB2 Models with adjustable outputs 0.485 0.5 0.515 V OPERATING SUPPLY CURRENT MODE = ground BUCK1 Only IIN ILOAD1 = 0 mA, device not switching, all other channels disabled 44 μA BUCK2 Only IIN ILOAD2 = 0 mA, device not switching, all other channels disabled 55 μA BUCK1 and BUCK2 IIN ILOAD1 = ILOAD2 = 0 mA, device not switching, LDO channels disabled 67 μA PSM CURRENT THRESHOLD IPSM PSM to PWM operation 100 mA SW CHARACTERISTICS SW On Resistance RNFET VIN1 = VIN2 = 3.6 V 155 240 mΩ RPFET VIN1 = VIN2 = 3.6 V 205 310 mΩ RNFET VIN1 = VIN2 = 5.5 V 137 204 mΩ RPFET VIN1 = VIN2 = 5.5 V 162 243 mΩ Current Limit ILIMIT1, ILIMIT2 PFET switch peak current limit 1600 1950 2300 mA ACTIVE PULL-DOWN RPDWN-B Channel disabled 75 Ω OSCILLATOR FREQUENCY fSW 2.5 3.0 3.5 MHz 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Rev. A | Page 5 of 28 LDO SPECIFICATIONS VIN3 = (VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT = 1 µF; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1 Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VIN3 1.7 5.5 V OPERATING SUPPLY CURRENT Bias Current per LDO2 IVIN3BIAS IOUT3 = 0 µA 10 30 µA IOUT3 = 10 mA 60 100 µA IOUT3 = 300 mA 165 245 µA Total System Input Current IIN Includes all current into AVIN, VIN1, VIN2, and VIN3 LDO Only IOUT3 = 0 µA, all other channels disabled 53 µA OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔVOUT3/VOUT3 100 µA < IOUT3 < 300 mA −3 +3 % Line Regulation (ΔVOUT3/VOUT3)/ΔVIN3 IOUT3 = 1 mA −0.03 +0.03 %/V Load Regulation3 (ΔVOUT3/VOUT3)/ΔIOUT3 IOUT3 = 1 mA to 300 mA 0.001 0.003 %/mA VOLTAGE FEEDBACK VFB3 0.485 0.5 0.515 V DROPOUT VOL TAGE4 VDROPOUT VOUT3 = 5.2 V, IOUT3 = 300 mA 50 mV VOUT3 = 3.3 V, IOUT3 = 300 mA 75 140 VOUT3 = 2.5 V, IOUT3 = 300 mA 100 mV VOUT3 = 1.8 V, IOUT3 = 300 mA 180 mV CURRENT-LIMIT THRESHOLD5 ILIMIT3 335 600 mA ACTIVE PULL-DOWN RPDWN-L Channel disabled 600 Ω OUTPUT NOISE Regulator LDO NOISELDO 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 100 µV rms POWER SUPPLY REJECTION RATIO PSRR Regulator LDO 10 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 60 dB 100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 62 dB 1 MHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 63 dB 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 This is the input current into VIN3, which is not delivered to the output load. 3 Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
Rev. A | Page 6 of 28 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS TA = −40°C to +125°C, unless otherwise specified. Table 4. Parameter Symbol Min Typ Max Unit NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2 Input Capacitor Ratings CMIN1, CMIN2 4.7 40 µF BUCK1, BUCK2 Output Capacitor Ratings CMIN1, CMIN2 10 40 µF LDO1 Input and Output Capacitor Ratings CMIN3, CMIN4 1.0 µF CAPACITOR ESR RESR 0.001 1 Ω 1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.
Dissipation and Thermal Considerations section. soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance
- NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
- IT IS RECOMMENDED THAT THE EXPOSED PAD
BE SOLDERED TO THE GROUND PLANE.
12 EN1
Figure 2. Pin Configuration—View from Top of the Die Table 7. Pin Function Descriptions 3 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN. 5 PGND2 Dedicated Power Ground for BUCK2. 6 NC No Connect. Leave this pin unconnected. 7 EN2 BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off. BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 9 VOUT2 BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2. 10 VOUT1 BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1. BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 12 EN1 BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off. 14 PGND1 Dedicated Power Ground for BUCK1. 15 SW1 BUCK1 Switching Node. 16 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN. 17 AVIN Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2. 20 VOUT3 LDO Output Voltage. 21 VIN3 LDO Input Supply (1.7 V to 5.5 V). 22 EN3 LDO Enable Pin. High level turns on this regulator, and low level turns it off. EPAD (EP) Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane.
Figure 45. Functional Block Diagram
Rev. A | Page 17 of 28 POWER MANAGEMENT UNIT The ADP5024 is a micropower management unit (microPMU) combing two step-down (buck) dc-to-dc convertors and one low dropout linear regulator (LDO). The high switching frequency and tiny 24-lead LFCSP package allow for a small power manage- ment solution. To combine these high performance regulators into the microPMU, there is a system controller allowing them to operate together. The buck regulators can operate in forced PWM mode if the MODE pin is at a logic level high. In forced PWM mode, the buck switching frequency is always constant and does not change with the load current. If the MODE pin is at logic level low, the switching regulators operate in automatic PWM/PSM mode. In this mode, the regulators operate at a fixed PWM frequency when the load current is above the PSM current threshold. When the load current falls below the PSM current threshold, the regulator in question enters PSM, where the switching occurs in bursts. The burst repetition rate is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. The automatic PWM/PSM mode transition is controlled independently for each buck regulator. The two bucks operate synchronized to each other. The ADP5024 has individual enable pins (EN1 to EN3) that control the activation of each regulator. The regulators are activated by a logic level high applied to the respective EN pin, wherein EN1 controls BUCK1, EN2 controls BUCK2, and EN3 controls the LDO. Regulator output voltages are set through external resistor dividers or can be optionally factory programmed to default values (see the Ordering Guide section). When a regulator is turned on, the output voltage ramp rate is controlled though a soft start circuit to avoid a large inrush current due to the charging of the output capacitors. Thermal Protection In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off all of the regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient tempera- ture. A 20°C hysteresis is included so that when thermal shutdown occurs, the regulators do not return to operation until the on-chip temperature drops below 130°C. When emerging from thermal shutdown, all regulators restart with soft start control. Undervoltage Lockout To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the system. If the input voltage on VIN1 drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on VIN1 rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for USB applications. For these models, the device reaches the turn off threshold when the input supply drops to 3.65 V typical. In case of a thermal or UVLO event, the active pull-downs (if factory enabled) are enabled to discharge the output capacitors quickly. The pull-down resistors remain engaged until the thermal fault event is no longer present or the input supply voltage falls below the V POR voltage level. The typical value of VPOR is approx- imately 1 V . Enable/Shutdown The ADP5024 has an individual control pin for each regulator. A logic level high applied to the ENx pin activates a regulator whereas a logic level low turns off a regulator. Figure 46 shows the regulator activation timings for the ADP5024 when all enable pins are connected to AVIN. Also shown is the active pull-down activation.
Figure 46. Regulator Sequencing (EN1 = EN2 = EN3 = VAVIN)
VOUT1 must be connected to the output capacitor. FB1 is 0.5 V . Figure 47. BUCK1 External Output Voltage Setting enters an idle mode, which improves conversion efficiency. is below the PSM current threshold. low sets the bucks to operate in automatic PSM/PWM. switching frequency when both bucks are in PWM mode. BUCK1 PFET starts conducting. discharge, preventing a runaway of output current. connected to the input of the converter. current from reversing direction and flowing out of the load.
allowing overshoot on the output voltage. downs during regulator activation and deactivation. Figure 48. LDO External Output Voltage Setting
large load variation when working in PSM mode (see Figure 50). citor, a low ESR capacitor is recommended. Table 10. The effective capacitance needed for stability, which Table 9. Suggested 10 μF Capacitors Table 10. Suggested 4.7 μF Capacitors Table 11. Suggested 1.0 μF Capacitors Figure 50. Processor System Power Management with PSM/PWM Control
Rev. A | Page 24 of 28 POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5024 is a highly efficient micropower management unit (microPMU), and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach the maximum allowable operating limit (125°C). When the temperature exceeds 150°C, the ADP5024 turns off all of the regulators allowing the device to cool down. When the die temperature falls below 130°C, the ADP5024 resumes normal operation. This section provides guidelines to calculate the power dissi- pated in the device and ensure that the ADP5024 operates below the maximum allowable junction temperature. The efficiency for each regulator on the ADP5024 is given by 100%× = IN OUT P Pη (1) where: η is the efficiency. PIN is the input power. POUT is the output power. Power loss is given by PLOSS = PIN − POUT (2a) or PLOSS = POUT (1− η)/η (2b) Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and at all of the outputs. Perform the measurements at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor, and from this result use Equation 3 to calculate the power dissipation in the ADP5024 buck converter. A second method to estimate the power dissipation uses the effi- ciency curves provided for the buck regulator, and the power lost on the LDO can be calculated using Equation 12. When the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor, use Equa- tion 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the LDO to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of V IN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and calculating the losses in the LDO provided by Equation 12. BUCK REGULATOR POWER DISSIPATION The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (3) where: PDBUCK is the power dissipation on one of the ADP5024 buck regulators. P L is the inductor power loss. The inductor losses are external to the device and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by PL ≈ IOUT1(RMS)2 × DCRL (4) where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator. 12+ 1) ( rII OUT1RMSOUT1 × = (5) where r is the normalized inductor ripple current. r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) (6) where: L is the inductance. fSW is the switching frequency. D is the duty cycle. D = VOUT1/VIN1 (7) The buck regulator power dissipation, PDBUCK, of the ADP5024 includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is located. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator. PDBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the P-MOSFET and the N-MOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT12 (9) where RDSON-P is approximately 0.2 Ω, and RDSON-N is approxi- mately 0.16 Ω at a junction temperature of 125°C and VIN1 = VIN2 = 3.6 V. At VIN1 = VIN2 = 2.3 V , these values change to 0.31 Ω and 0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V , the values are 0.16 Ω and 0.14 Ω, respectively.
Rev. A | Page 25 of 28 Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) where: CGATE-P is the P-MOSFET gate capacitance. CGATE-N is the N-MOSFET gate capacitance. For the ADP5024, the total of (CGATE-P + CGATE-N) is approx- imately 150 pF . The transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near V OUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW . For the ADP5024, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, include a sufficient safety margin in the estimate. LDO Regulator Power Dissipation The power loss of the LDO regulator is given by PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (12) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small, and it can be ignored. JUNCTION TEMPERATURE In cases where the board temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) (14) The typical θJA value for the 24-lead, 4 mm × 4 mm LFCSP is 35°C/W (see Table 6). A very important factor to consider is that θJA is based on a 4-layer, 4 in × 3 in, 2.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. To remove heat from the device, it is important to maximize the use of copper. Copper exposed to air dissipates heat better than copper used in the inner layers. Connect the exposed pad to the ground plane with several vias. If the case temperature can be measured, the junction temperature is calculated by T J = TC + (PD × θJC) (15) where TC is the case temperature and θJC is the junction-to-case thermal resistance provided in Table 6. When designing an application for a particular ambient temperature range, calculate the expected ADP5024 power dissipation (P D) due to the losses of all channels by using Equation 8 to Equation 13. From this power calculation, the junction temperature, T J, can be estimated using Equation 14. The reliable operati on of the converter and the LDO regulator can be achieved only if the estimated die junction temperature of the ADP5024 (see Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) is highly affected by increasing the junction temperature. Additional information about product reliability can be found from the ADI Reliability Handbook, which is available at the following URL: www.analog.com/reliability_handbook. The total power dissipation in the ADP5024 simplifies to P D = PDBUCK1 + PDBUCK2 + PDLDO (13)
Rev. A | Page 26 of 28 PCB LAYOUT GUIDELINES Poor layout can affect ADP5024 performance, causing electro- magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to User Guide UG-271.
- Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas.
- Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference.
- Maximize the size of ground metal on the component side to help with thermal dissipation.
- Use a ground plane with several vias connected to the component side ground to further reduce noise interference on sensitive circuit nodes.
- Connect VIN1, VIN2, and AVIN together close to the IC using short tracks.
COMPLIANT TOJEDEC STANDARDS MO-220-WGGD-8.
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
2 UVLO3
4 Package Description Package Option
4 BUCK1, BUCK2, LDO: active pull-down resistor is programmable to be either enabled or disabled. registered trademarks are the prop erty of their respective owners.