ECJ-2FB0J226ML

IR3856MPBF IRF | Alldatasheet

Document overview

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Technical content

Features

• Greater than 95% Maximum Efficiency
• Wide Input Voltage Range 1.5V to 21V
• Wide Output Voltage Range 0.7V to 0.9*Vin
• Continuous 6A Load Capability
• Integrated Bootstrap-diode
• High Bandwidth E/A for excellent transient performance
• Programmable Switching Frequency up to 1.5MHz
• Programmable Over Current Protection
• Over Voltage Protection
• Dedicated input for output voltage monitoring
• Programmable PGood output
• Hiccup Current Limit
• Precision Reference Voltage (0.7V, +/-1%)
• Programmable Soft-Start
• Enable Input with Voltage Monitoring Capability
• Enhanced Pre-Bias Start-up
• Seq input for Tracking applications
• External Synchronization
• -40oC to 125oC operating junction temperature
• Thermal Protection
• 4mm x 5mm Power QFN Package
• Halogen Free, Lead Free and RoHS compliant Fig. 1. Typical application diagram

Description

The IR3856 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC synchronous Buck regulator. The MOSFETs co- packaged with the on-chip PWM controller make IR3856 a space-efficient solution, providing accurate power delivery for low output voltage applications. IR3856 is a versatile regulator which offers programmability of start up time, switching frequency and current limit while operating in wide input and output voltage range. The switching frequency is programmable from 250kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Pre-Bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions. HIGHLY EFFICIENT INTEGRATED 6A, SYNCHRONOUS BUCK REGULATOR SupIRBuck TM

• Distributed Point of Load Power Architectures
• Netcom Applications
• Computing Peripheral Voltage Regulators
• General DC-DC Converters

Applications

• Server Applications
• Storage Applications
• Embedded Telecom Systems

Rev 4.0 2 PD-97528 IR3856MPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND unless otherwise specified)

• Moisture sensitivity level………………...………………JEDEC Level 3@260 °C ( Note5) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Note1: Must not exceed 8V Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC W/C W/C W/C o PCBJ JA JA )FET_Ctrl( )FET_Sync( θ θ

PACKAGE INFORMATION

M PACKAGE DESIGNATOR

ORDERING INFORMATION

Fb Vsns COMP Gnd Rt SS OCSet PGood Enable Boot Seq Vcc1014 Sync * Exposed pads on underside are connected to copper pads of a 4-layer (2 oz.) PCB

Rev 4.0 3 PD-97528 IR3856MPbF Block Diagram Fig. 2. Simplified block diagram of the IR3856

Rev 4.0 4 PD-97528 IR3856MPbF Pin Description Pin Name Description 1 Fb Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier.

2 Vsns Sense pin for PGood

3 Comp Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb pin to provide loop compensation. 4;17 Gnd Signal ground for internal reference and control circuitry. 5 Rt Set the switching frequency. Connect an external resistor from this pin to Gnd to set the switching frequency. See Table 1 for Fs vs. Rt. 6 SS/SD Soft start / shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to Gnd to set the star t up time of the output voltage. T he conver ter can be shutdown by pulling this pin below 0.3V. 7 OCSet Current limit set point. A resistor from this pin to SW pin will set the current limit threshold.

8 PGood

Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to Vcc.

9 Sync Sync pin, connect external system clock to synchronize multiple POLs

10 V CC This pin powers the internal IC and the drivers. A minimum of 1uF high frequency capacitor must be connected from this pin to the power ground (PGn d). 11 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. 12 SW Switch node. This pin is connected to the output inductor.

13 V IN

Input voltage connection pin. 14 Boot Supply voltage for high side driver. A 0.1uF capacitor must be connected from this pin to SW. 15 Enable Enable pin to turn on and off the device. Use two external resistors to set the turn on threshold (see Enable section). Connect this pin to Vcc if it is not used. 16 Seq Sequence pin. Use two external resistors to set Simultaneous Power up sequencing. If this pin is not used connect to Vcc.

Rev 4.0 5 PD-97528 IR3856MPbF Recommended Operating Conditions * Note: SW node should not exceed 25V Electrical Specifications Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. Symbol Definition Min Max Units Vin Input Voltage 1.5 21* Vcc Supply Voltage 4.5 5.5 Boot to SW Supply Voltage 4.5 5.5 Vo Output Voltage 0.7 0.9*Vin V Io Output Current 0 6 A Fs Switching Frequency 225 1650 kHz Tj Junction Temperature -40 125 oC PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT POWER STAGE Power Losses P loss Vcc=5V, V in=12V, Vo=1.8V, Io=6A, Fs=600kHz, L=1.0uH, Note4 1.11 W Top Switch R ds(on)_Top VBoot -Vsw =5V, ID=6A, Tj=25oC 22 29 Bottom Switch Rds(on)_Bot Vcc=5V, ID=6A, Tj=25oC 13.4 19 mΩ Deadband Time T db Note4 5 10 30 ns Bootstrap Diode Forward Voltage I(Boot)= 30mA 180 260 470 mV Isw SW=0V, Enable=0V SW leakage Current SW=0V, Enable=high, SS=3V, Vseq=0V, Note4 uA SUPPLY CURRENT VCC Supply Current (Standby) ICC(Standby) SS=0V, Vcc=5V, Enable low , No Switching 500 uA VCC Supply Current (Dyn) I CC(Dyn ) SS=3V, Vcc=5V, Enable high, Fs=500kHz 9.25 mA REFERENCE VOLTAGE Feedback Voltage VFB 0.7 V o C<Tj<125 o C -1.0 +1.0 Accuracy -40 o C<Tj<125 o C, Note3 -2.0 -2.0 SOFT START / SD Soft Start Current ISS Source 14 20 26 uA Soft Start Clamp Voltage Vss(clamp) 2.7 3.0 3.3 Shutdown Output Threshold SD 0.3 V

Rev 4.0 6 PD-97528 IR3856MPbF Electrical Specifications (continued) Unless otherwise specified, these specifications apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT ERROR AMPLIFIER Input Offset Voltage Vos Vfb-Vseq, Vseq=0.8V -10 +10 mV Input Bias Current IFb(E/A) -1 +1 Input Bias Current IVseq(E/A) -1 +1 μA Sink Current Isink(E/A) 0.40 0.85 1.2 Source Current Isource(E/A) 8 10 13 mA Slew Rate SR Note4 7 12 20 V/μs Gain-Bandwidth Product GBWP Note4 20 30 40 MHz DC Gain Gain Note4 100 110 120 dB Maximum Voltage Vmax(E/A) Vcc=4.5V 3.4 3.5 3.75 V Minimum Voltage Vmin(E/A) 120 220 mV Seq Common Mode Voltage Note4 0 1 V OSCILLATOR Rt Voltage Vrt 0.665 0.7 0.735 V Rt=59K 225 250 275 Rt=28.7K 450 500 550 Frequency Range FS Rt=9.31K, Note4 1350 1500 1650 kHz Ramp Amplitude Vramp Note4 1.8 Vp-p Ramp Offset Ramp(os) Note4 0.6 V Min Pulse Width Dmin(ctrl) Note4 50 ns Max Duty Cycle Dmax Fs=250kHz 92 % Fixed Off Time Toff Note4 130 200 ns Sync Frequency Range Fsync 225 1650 kHz Sync Pulse Duration Tsync 100 200 ns High 2 Sync Level Threshold Low 0.6 V

Rev 4.0 7 PD-97528 IR3856MPbF PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT FAULT PROTECTION Fs=250kHz 20.8 23.6 26.4 Fs=500kHz 43 48.8 54.6 OCSET Current IOCSET Fs=1500kHz 136 154 172 uA OC comp Offset Voltage V OFFSET Note4 -10 0 +10 mV SS off time SS_Hiccup 4096 Cycles OVP Trip Threshold OVP(trip) Vsns Rising 110 115 120 %Vref OVP Fault Prop. Delay OVP(delay) Note4 150 ns Thermal Shutdown Note4 140 Thermal Hysteresis Note4 20 VCC-Start-Threshold V CC_UVLO_Start Vcc Rising Trip Level 3.95 4.15 4.35 VCC-Stop-Threshold V CC_UVLO_Stop Vcc Falling Trip Level 3.65 3.85 4.05 V INPUT/OUTPUT SIGNAL Enable-Start-Threshold Enable_UVLO_Start Supply ramping up 1.14 1.2 1.36 Enable-Stop-Threshold Enable_UVLO_Stop Supply ramping down 0.9 1.0 1.06 V Enable leakage current Ien Enable=3.3V 15 uA Power Good Threshold VPG Vsns Rising 80 85 90 %Vref PGood Comparator Delay PG(Delay) Vsns Rising 256/Fs s PGood Delay Comparator Threshold SS(Delay) Relative to charge voltage, SS rising 2 2.1 2.3 V PGood Delay Comparator Hysteresis Delay(SShys) Note4 260 300 340 mV PGood Leakage Current I(PGDlk) 0 10 uA PGood Voltage Low PG(voltage) I Pg oo d=-5mA 0.5 V Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note4: Guaranteed by Design but not tested in production. Note5: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3 for Consumer market. Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC.

Rev 4.0 8 PD-97528 IR3856MPbF Typical Efficiency and Power Loss Curves Vin=12V, Vcc=5V, Io=0.6A- 6A, Fs=600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Load Current (A) Efficiency (%) 0.10 0.30 0.50 0.70 0.90 1.10 1.30 1.50 Load Current (A) Power Loss (W) Vo (V) L (uH) P/N DCR (mOhm) 1 0.68 PCMB065T-0R68 3.9 1.2 0.82 SPM6550T-0R82M 4.2 1.5 1.0 SPM6550T-1R0M 4.7 1.8 1.0 SPM6550T-1R0M 4.7 3.3 3.3 7443340220 4.4 5 3.3 7443340220 4.4

Rev 4.0 9 PD-97528 IR3856MPbF Typical Efficiency and Power Loss Curves Vin=5V, Vcc=5V, Io=0.6A- 6A, Fs=600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Load Current (A) Efficiency (%) 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 Load Current (A) Power Loss (W) Vo (V) L (uH) P/N DCR (mOhm) 1 0.68 PCMB065T-0R68 3.9 1.2 0.68 PCMB065T-0R68 3.9 1.5 0.82 SPM6550T-0R82M 4.2 1.8 1.00 SPM6550T-1R0M 4.7 3.3 1.00 SPM6550T-1R0M 4.7

Rev 4.0 10 PD-97528 IR3856MPbF -40 -20 0 20 40 60 80 100 120 Temperature [ °C] Resistance [mΩ] Sync-FET Ctrl-FET Rdson of MOSFETs Over Temperature at Vcc=5V

Rev 4.0 11 PD-97528 IR3856MPbF Icc(Dyn) 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [mA] ISS 14.0 16.0 18.0 20.0 22.0 24.0 26.0 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [uA] Enable(UVLO) Stop 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 -40 -20 0 20 40 60 80 100 120 Temp[ οC] [V] Enable(UVLO) Start 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ oC] [V] Vcc(UVLO) Stop 3.76 3.81 3.86 3.91 3.96 4.01 4.06 4.11 4.16 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [V] Vcc(UVLO) Start 4.06 4.11 4.16 4.21 4.26 4.31 4.36 4.41 4.46 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ oC] [V] IOCSET(500kHz) 43.0 44.0 45.0 46.0 47.0 48.0 49.0 50.0 51.0 52.0 53.0 54.0 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [uA] FREQUENCY 450 460 470 480 490 500 510 520 530 540 550 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [kHz] Icc(Standby) 150 170 190 210 230 250 270 290 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [uA] Vfb 686 691 696 701 706 711 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ oC] [mV] TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC) Fs=500 kHz

Rev 4.0 12 PD-97528 IR3856MPbF Circuit Description THEORY OF OPERATION Introduction The IR3856 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3856 provides precisely regulated output voltage programmed via two external resistors from 0.7V to 0.9*Vin. The IR3856 operates with an external bias supply from 4.5V to 5.5V, allowing an extended operating input voltage range from 1.5V to 21V. The device utilizes the on-resistance of the low side MOSFET as current sense element, this method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor IR3856 includes two low R ds(on) MOSFETs using IR’s HEXFET technology. These are specifically designed for high efficiency applications. Under-Voltage Lockout and POR The under-voltage lockout circuit monitors the input supply Vcc and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc and Enable rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). Enable The Enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under-Voltage Lockout (UVLO) circuit. Therefore, the IR3856 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3856 does not turn on until the bus voltage reaches the desired level. Only after the bus voltage reaches or exceeds this level will the voltage at Enable pin exceed its threshold, thus enabling the IR3856. Therefore, in addition to being a logic input pin to enable the IR3856, the Enable feature, with its precise threshold, also allows the user to implement an Under-Voltage Lockout for the bus voltage V in. This is desirable particularly for high output voltage applications, where we might want the IR3856 to be disabled at least until V in exceeds the desired output voltage level. Figure 3b. shows the recommended start-up sequence for the non-sequenced operation of IR3856, when Enable is used as a logic input. Fig. 3a. Normal Start up, Device turns on when the Bus voltage reaches 10.2V Fig. 3b. Recommended startup sequence, Non-Sequenced operation

shutdown by pulling the soft-start pin below 0.3V. voltage at the Soft Start pin. the current limit set point. Table 1. shows I tabulates the oscillator frequency versus Rt. soft start function in hiccup mode. OCP signal resets and the converter recovers. Table 1. Switching Frequency and IOCSet vs. 160 ns after the low gate drive rises to about 3V. This delay functions to filter out switching noise.

Rev 4.0 15 PD-97528 IR3856MPbF Thermal Shutdown Temperature sensing is provided inside IR3856. The trip threshold is typically set to 140 oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20 oC hysteresis in the thermal shutdown threshold. Fig. 8b. Application Circuit for Simultaneous Sequencing Simultaneous Powerup Vo1 Vo2 Output Voltage Sequencing The IR3856 can accommodate user programmable sequencing options using Seq, Enable and Power Good pins. Boot Vcc Fb Comp Gnd PGnd SW OCSet SS/ SD 4.5V <Vcc<5.5V Vo(master) PGood PGood Enable Rt 1.5V <Vin<16V Vin Seq RA RB Boot Vcc Fb Comp Gnd PGnd SW OCSet SS/ SD 4.5V <Vcc<5.5V Vo(slave) PGood PGood Enable Rt 1.5V <Vin<16V Vin Seq Vo(master) RC RD RE RF Fig. 8a. Simultaneous Power-up of the slave with respect to the master. Through these pins, voltage sequencing such as simultaneous and sequential can be implemented. Figure 8. shows simultaneous sequencing configurations. In simultaneous power-up, the voltage at the Seq pin of the slave reaches 0.7V before the Fb pin of the master. For R E/RF =RC/RD, therefore, the output voltage of the slave follows that of the master until the voltage at the Seq pin of the slave reaches 0.7 V. After the voltage at the Seq pin of the slave exceeds 0.85V, the internal 0.7V reference of the slave dictates its output voltage. Power-Good and Over-voltage Protection If the output voltage exceeds the over voltage threshold, an over voltage trip signal asserts, this will result to turn off the high side driver and turn on the low side driver until the Vsns voltage drops below 1.15*Vref threshold. Both drivers are latched off until a reset performed by cycling either Vcc or Enable. The OVP threshold can be externally programmed to user defined value. Figure 10 shows the response in over-voltage condition. The V sns pin forms an input to a window comparator whose upper and lower thresholds are 0.805V and 0.595V, respectively. Hence, the Power Good signal is flagged when the V sns pin voltage is within the PGood window, i.e. between 0.595V to 0.805V, as shown in figure 9. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Figure 9.a shows the PGood timing diagram for non-tracking operation. In this case, during startup, PGood goes high after the SS voltage reaches 2.1V if the Vsns voltage is within the PGood comparator window. Figure 9.a and Figure 9.b also show a 256 cycle delay between the Vsns voltage entering within the thresholds defined by the PGood window and PGood going high.

Rev 4.0 16 PD-97528 IR3856MPbF SS 0.85*Vref(typical), +/-5% for Min/Max PGood 256/Fs Vsns 0.7V 1.4V 2.1V A PGood window 1.15*Vref(typical), +/-5% for Min/Max 100ns(typical) Delay 100ns(typical) Delay At point “A” the power Good signal goes low, high drive turns off, low drive turns on till Vsns is above Over Voltage threshold and the device latches off. POR (Vcc/Enable) needs to be recycled for new start up. TIMING DIAGRAM OF PGOOD FUNCTION Fig.9a IR3856 Non-Tracking Operation (Seq=Vcc) Fig.9b IR3856 Tracking Operation

Rev 4.0 17 PD-97528 IR3856MPbF TIMING DIAGRAM OF Over Voltage Protection Fig.10 IR3856 Over Voltage Timing Diagram External Synchronization The IR3856 incorporates an internal circuit which enables synchronization of the internal oscillator (using rising edge) to an external clock. An external resistor from Rt pin to Gnd is still required to set the free-running frequency close to the Sync input frequency. This function is important to avoid sub-ha rmonic oscillations due to beat frequency for embedded systems when multiple POL (point of load) regulators are used. The synchronization clock can be applied during IR3856 normal operation or before IR3856 start- up. In any case, IR3856 will perform with the external after the end of the PreBias cycle. Applying the external signal to the Sync input changes the effective value of the ramp signal (Vramp/Vosc). Therefore, since the ramp amplitude takes part in calculating the loop-gain and bandwidth of the regulator, it is recommended not to use a Sync frequency which is much higher than the free- running frequency. In addition, the effective value of the ramp signal, given by equation (5), should be used when the compensator is designed for the regulator. The pulse width of the external clock, which is applied to the sync, should be greater than 100ns and its high level should be greater than 2V, while its lower level is less than 0.6V. If this pin is left floating, the IC will run with the free running frequency set by the resistor Rt. Equation (5) shows that the effective amplitude of the ramp (Vosc(eff)) is reduced after the external Sync signal is applied. More difference between the frequency of the Sync (f Sync) and the free- running frequency (f Free_Run) results in more change in the effective amplitude of the ramp signal.

Rev 4.0 18 PD-97528 IR3856MPbF Minimum on time Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3856, the typical minimum on-time is specified as 50 ns. Any design or application using the IR3856 must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 100 ns. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. In any application that uses the IR3856, the following condition must be satisfied: The minimum output voltage is limited by the reference voltage and hence V out(min) = 0.7 V. Therefore, for Vout(min) = 0.7 V, Therefore, at the maximum recommended input voltage 21V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 333 kHz. Conversely, for operation at the maximum recommended operating frequency 1.65 MHz and minimum output voltage, any voltage above

4.2 V may not be stepped down without pulse-

skipping. V/s 107ns 100 V 0.7V V in in ×=≤×∴ ≤×∴ s (min)on (min)out s F t VF Maximum Duty Ratio Considerations A fixed off-time of 200 ns maximum is specified for the IR3856. This provides an upper limit on the operating duty ratio at any given switching frequency. It is clear, that higher the switching frequency, the lower is the maximum duty ratio at which the IR3856 can operate. To allow a margin of 50ns, the maximum operating duty ratio in any application using the IR3856 should still accommodate about 250 ns off-time. Fig 10. shows a plot of the maximum duty ratio v/s the switching frequency, with 250 ns off-time. s out s on F V F Dt V in ×= (min) (min) (min) on out sin sin out on onon t VFV FV Vt tt ≤×∴ ×≤∴ Fig. 11. Maximum duty cycle v/s switching frequency. Max Duty Cycle 250 450 650 850 1050 1250 1450 1650 Switching Frequency (kHz) Max Duty Cycle (%)

Rev 4.0 19 PD-97528 IR3856MPbF

Application Information

Design Example: The following example is a typical application for IR3856. The application circuit is shown on page 25. Enabling the IR3856 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage. For a maximum Enable threshold of V EN = 1.36 V For a Vin (min)=10.2V, R1=49.9K and R2=7.5K is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 23.7 kΩ, using Table. 1. Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.7V. The divider is ratioed to provide 0.7V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: Fb IR3624 VOUT IR3856 When an external resistor divider is connected to the output as shown in figure 12. Equation (6) can be rewritten as: For the calculated values of R8 and R9 see feedback compensation section. Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. From (1), for a desired start-up time of the converter, the soft start capacitor can be calculated by using: Where T start is the desired start-up time (ms). For a start-up time of 3.5ms, the soft-start capacitor will be 0.099 μF. Choose a 0.1 μF ceramic capacitor. Bootstrap Capacitor Selection To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected the source of the Control FET . This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C6), as shown in Fig. 13. The operation of the circuit is as follows: When the lower MOSFET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards V cc through the internal bootstrap diode, which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C6 is approximately given as When the upper MOSFET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage V in. However, if the value of C6 is appropriately chosen, the voltage Vc kHz 600= V of 5% A 6 = V 1.8= max) 13.2V ( V 12= o s o o o in F ΔV I V V ⎛ +∗= R RVV refo Fig. 12. Typical application of the IR3856 for programming the output voltage VRR refo ref −∗= IR3856 Enable Vin VRR 2 ==+ VV VRR EN)minin(

Rev 4.0 20 PD-97528 IR3856MPbF Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( Δi ) . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: Where: If Δi ≈ 43%(I o), then the output inductor is calculated to be 1.01μH. Select L=1.0 μH. The SPM6550T-1R0M from TDK provides a compact inductor suitable for this application. across C6 remains approximately unchanged and the voltage at the Boot pin becomes: A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple current generated during the on time of the upper MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by: Where: D is the Duty Cycle I RMS is the RMS value of the input capacitor current. Io is the output current. For I o=6A and D = 0.15, the IRMS = 2.14A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 3x10uF 25V ceramic capacitors C3216X5R1E106M from TDK. In addition to these, although not mandatory, a 1X330uF, 25V SMD capacitor EEV-FK1E331P may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. in o V VD = cycleDuty time on Turn frequency Switching current ripple Inductor VoltageOutput voltage input Maximum D Δt F Δi V V s o in sin o oin s oin F*iV VVVL FDt;t iLVV Δ∗∗−= ∗=ΔΔ Δ∗=− Fig. 13. Bootstrap circuit to generate Vc voltage

Rev 4.0 21 PD-97528 IR3856MPbF current ripple Inductor ripple voltage Output Δ=Δ ⎛ −=Δ Δ=Δ Δ+Δ+Δ=Δ L o so L )C(o oin )ESL(o L)ESR(o )C(o)ESL(o)ESR(oo I V F*C* IV ESL*L VVV ESR*IV VVVV Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3856 can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Four of the TDK C2102X5R0J226M (22uF, 6.3V, 3mOhm) capacitors is a good choice. Feedback Compensation The IR3856 is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0 dB crossing frequency and adequate phase margin (greater than 45 o). The output LC filter introduces a double pole, –40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see figure 13). The resonant frequency of the LC filter is expressed as follows: Figure 14 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. The IR3856 uses a voltage-type error amplifier with high-gain (110dB) and wide-bandwidth. The output of the amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in Type-II or Type-III compensation. Local feedback with Type-II compensation is shown in figure 14. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general, for Type-II compensation the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor is expressed as follows: oo LC CL F π Fig. 14. Gain and Phase of LC filter o ESR *ESR*CF π∗= Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as

Rev 4.0 22 PD-97528 IR3856MPbF The transfer function (Ve/Vo) is given by: The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: First select the desired zero-crossover frequency o): Use the following equation to calculate R3: Fig. 15. Type II compensation network and its asymptotic gain plot CsR CsR Z Z)s(HV V IN f o e +−=−== C*R*F R RsH z π= ( ) sESRo FFF *1/10~1/5 F and o ≤> LCin ESRoosc F*V R*F*F*VR = Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Use equations (21), (22) and (23) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: The pole sets to one half of the switching frequency which results in the capacitor C POLE: For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, we should implement local feedback with a Type-III compensation network. The typically used compensation network for voltage-mode controller is shown in figure 16. Again, the transfer function is given by: By replacing Z in and Zf according to figure 16, the transfer function can be expressed as: 1750 oo z LCz C*L *.F F%F π POLE POLE P CC C*C*R* F π (25)1 C*F*R C ss POLE ππ IN f o e Z ZsHV V −== )( ( )( )[] () () 710 3348 108743 CsRCC C*CsRCCsR RRsCCsR)s(H +++ +++−=

Rev 4.0 23 PD-97528 IR3856MPbF Tantalum CeramicFLC<Fo<FESRType III Electrolytic TantalumFLC<FESR<Fo<Fs/2Type II Output CapacitorFESR vs Fo Compensator Type Tantalum CeramicFLC<Fo<FESRType III Electrolytic TantalumFLC<FESR<Fo<Fs/2Type II Output CapacitorFESR vs Fo Compensator Type The compensation network has three poles and two zeros and they are expressed as follows: Cross over frequency is expressed as: Fig.16. Type III Compensation network and its asymptotic gain plot 871087 710 R*C*)RR(*C*F C*R*F C*R* CC C*CR* F C*R*F F Z Z P P P ππ π ππ π ≅+= ooosc in o C*L**V V*C*RF π= The higher the crossover frequency, the potentially faster the load transient response. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency is selected such that The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45 o for overall stability. For this design we have: Vin=12V Vo=1.8V Vosc=1.8V Vref=0.7V Lo=1.0uH Co=4x22uF, ESR=3mOhm each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design (i.e. C3216X5R1E106M from TDK) is 9.5uF at 1.8 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency F LC and using equation (16) to compute the small signal Co. These result to: FLC=25.8 kHz FESR=5.5 MHz Fs/2=300 kHz Select crossover frequency Fo=100 kHz Since FLC<Fo<Fs/2<FESR, Type-III is selected to place the pole and zeros. VOUT VREF R8R10 C4R3 Ve FZ1 FZ2 FP2 FP3 E/A Zf ZIN Frequency Gain(dB) H(s) dB Fb Comp Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. The table below shows the compensation types for relative locations of the crossover frequency.

Rev 4.0 24 PD-97528 IR3856MPbF Setting the Power Good Threshold Power Good threshold can be programmed by using two external resistors (R5, R7 on Page 24). The following formula can be used to set the threshold: Where: 0.85*Vref is reference of the internal comparator, for IR3856. V o(PGood_TH) is the selectable output voltage threshold for power good, for this design it is The PGood is an open drain output. Hence, it is necessary to use a pull up resistor R PG from PGood pin to Vcc. The value of the pull-up resistor must be chosen such as to limit the current flowing into the PGood pin, when the output voltage is not in regulation, to less than 5 mA. A typical value used is 10kΩ. Detailed calculation of compensation Type-III kΩ 2.55 :Select kΩ 2.56 ;* kΩ 4.02:Select ,kΩ 3.97 ;2 Ω 130 :Select ,Ω 130 ;2 : and , Calculate pF 270 :Select ,pF 327 ;2 nF 10 :Select nF, 94.10 ;2 k 1.65 :Select kΩ 1.63;* ****2 : and , Calculate nF 2.2C :Select kHz 300*0.5 and kHz 8.82 *5.0 :Select kHz 567.1 sin1 sin1 kHz 63.71 sin1 sin1

70 Margin Phase Desired

o === === === === =Θ− Θ+= =Θ+ Θ−= RRRVV VR R RRFCR RRFCR RRR CCRFC CCRFC R RVC VCLFR CCR FF FF FF FF refo ref Z P P Z in oscooo sP ZZ oP oZ π π π π Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (R OCSET) from the SW pin to the OCSet pin. The resistor can be calculated by using equation (4). This resistor R OCSET must be placed close to the IC. The R DS(on) has a positive temperature coefficient and it should be considered for the worst case operation. kΩ 55.2 Select kΩ 2.55R kHz) 600 (at μA 59.07I ) current output nominal over (50% A 91.5A 6 mΩ 62.611.25mΩ 4.13 7OCSet OCSet ==≅ R F II R s LIMoSET onDS R IRII )on(DS OCSetOCSet )critical(LSET ∗== Select R7=2.55KOhm Using (24): R5=3.97KOhm Select R6=4.02KOhm V ref )TH_PGood(o

Rev 4.0 25 PD-97528 IR3856MPbF Application Diagram: Fig. 17. Application circuit diagram for a 12V to 1.8 V, 6A Point Of Load Converter Suggested Bill of Materials for the application circuit: Part Reference Quantity Value Description Manufacturer Part Number 1 330uF SMD Elecrolytic, Fsize, 25V, 20% Panasonic EEV-FK1E331P 3 10uF 1206, 16V, X5R, 20% TDK C3216X5R1E106M 1 0.1uF 0603, 25V, X7R, 10% Panasonic ECJ-1VB1E104K Lo 1 1.0uH 6.9x6.5x5mm, 20%, 4.7mOhm TDK SPM6550T-1R0M100A Co 4 22uF 0805, 6.3V, X5R, 20% Panasonic ECJ-2FB0J226ML R1 1 49.9k Thick Film, 0603,1/10 W,1% Rohm MCR03EZPFX4992 R2 1 7.5k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX7501 R t 1 23.7k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX2372 Rocset 1 2.55k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX2551 RPG 1 10k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX1002 Css C6 2 0.1uF 0603, 25V, X7R, 10% Panasonic ECJ-1VB1E104K R3 1 1.65k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX1651 C3 1 270pF 50V, 0603, NPO, 5% Panasonic ECJ-1VC1H271J C4 1 10nF 0603, 50V, X7R, 10% Panasonic ECJ-1VB1H103K R8 R7 2 4.02k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX4021 R9 R5 2 2.55k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX2551 R10 1 130 Thick Film, 0603,1/10W,1% Rohm ERJ-3EKF1300V C7 1 2200pF 0603, 50V, X7R, 10% Panasonic ECJ-1VB1H222K CVcc CPVcc 2 1.0uF 0603, 16V, X5R, 20% Panasonic ECJ-BVB1C105M U1 1 IR3856 SupIRBuck, 6A, PQFN 4x5mm International Rectifier IR3856MPbF Cin

Rev 4.0 26 PD-97528 IR3856MPbF TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-6A, Room Temperature, No Air Flow Fig. 21: Output Voltage Ripple, 6A load Ch1: Vout Fig. 19: Start up at 6A Load, Ch1:Vin, Ch2:Vout, Ch3:Vss, Ch4:VPGood Fig. 18: Start up at 6A Load Ch1:Vin, Ch2:Vout, Ch3:Vss, Ch4:Enable Fig. 20: Start up with 1.62V Pre- Bias, 0A Load, Ch2:Vout, Ch3:VSS Fig. 22: Inductor node at 6A load Ch1: Switch Node Fig. 23: Short (Hiccup) Recovery Ch2:Vout , Ch3:Vss

Rev 4.0 27 PD-97528 IR3856MPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=3A- 6A, Room Temperature, No Air Flow Fig. 24: Transient Response, 3A to 6A step 2.5A/μs Ch2:Vout, Ch4:Iout

Rev 4.0 28 PD-97528 IR3856MPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=6A, Room Temperature, No Air Flow Fig. 25: Bode Plot at 6A load shows a bandwidth of 90kHz and phase margin of 51 degrees Fig. 26: Synchronization to 700kHz external clock signal at 6A load Ch2: SW (Switch Node) Ch3:Sync

Rev 4.0 29 PD-97528 IR3856MPbF TYPICAL OPERATING WAVEFORMS Simultaneous Tracking at Power Up and Power Down Vin=12V, Vo=1.8V, Io=6A, Room Temperature, No Air Flow Fig. 27: Simultaneous Tracking a 3.3V input at power-up and shut-down Ch1: SS(1.8V) Ch2:Vout (1.8V) Ch3: SEQ(3.3V) Fb IR3624 VOUT IR3856 3.3V Rs2 Rs1 Seq 4.02K4.02K 2.55K 2.55K

Rev 4.0 30 PD-97528 IR3856MPbF Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3856 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the Vin pin of IR3856. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. PGndVin AGnd Vout PGndVin AGnd Vout The connection between the OCSet resistor and the SW pin should not share any trace with the connection between the bootstrap capacitor and the SW pin. Instead, it is recommended to use a Kelvin connection of the trace from the OCSet resistor and the trace from the bootstrap capacitor at the SW pin. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 28 illustrates the implementation of the layout guidelines outlined above, on the IRDC3856 4 layer demoboard. Vout All bypass caps should be placed as close as possible to their connecting pins. Resistors Rt, SS cap, and Rocset should be placed as close as possible to their pins. Enough copper & minimum length ground path between Input and Output PGndVin AGnd Compensation parts should be placed as close as possible to the Comp pin. Fig. 28a. IRDC3856 demoboard layout considerations – Top Layer

Rev 4.0 31 PD-97528 IR3856MPbF Use separate trace for connecting Boost cap and Rocset to the switch node and with the minimum length traces. Avoid big loops. PGnd Fig. 28c. IRDC3856 demoboard layout considerations – Mid Layer 1 Fig. 28d. IRDC3856 demoboard layout considerations – Mid Layer 2 Fig. 28b. IRDC3856 demoboard layout considerations – Bottom Layer Single point connection between AGND & PGND; It should be close to the SupIRBuck, kept away from noise sources. PGnd Vin Vout SW PGnd AGnd Feedback trace should be kept away form noise sources

Rev 4.0 32 PD-97528 IR3856MPbF PCB Metal and Components Placement PCB metal pad sizing (all dimensions in mm) PCB metal pad spacing (all dimensions in mm) Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN-1132

Rev 4.0 33 PD-97528 IR3856MPbF Solder Resist IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip.

Rev 4.0 34 PD-97528 IR3856MPbF Stencil Design than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Stencil pad sizing (all dimensions in mm) Stencil pad spacing (all dimensions in mm)

Rev 4.0 35 PD-97528 IR3856MPbF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market (Note5) Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 08/12