ECJ-2FB0J226M

IR3843WMPBF_12 IRF | Alldatasheet

Document overview

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• PDF pages: 34

Technical content

Features

• Wide Input Voltage Range 1.5V to 16V
• Wide Output Voltage Range 0.7V to 0.9*Vin
• Continuous 2A Load Capability
• Integrated Bootstrap-diode
• High Bandwidth E/A for excellent transient performance
• Programmable Switching Frequency up to 1.5MHz
• Programmable Over Current Protection
• PGood output
• Hiccup Current Limit
• Precision Reference Voltage (0.7V, +/-1%)
• Programmable Soft-Start
• Enable Input with Voltage Monitoring Capability
• Enhanced Pre-Bias Start-up
• Seq input for Tracking applications
• -40oC to 125oC operating junction temperature
• Thermal Protection
• Multiple current ratings in pin compatible footprint
• 5mm x 6mm Power QFN Package, 0.9 mm height
• Lead-free, halogen-free and RoHS compliant

Applications

• Server Applications
• Storage Applications
• Embedded Telecom Systems
• Distributed Point of Load Power Architectures Fig. 1. Typical application diagram

Description

The IR3843W SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC synchronous Buck regulator. The MOSFETs co- packaged with the on-chip PWM controller make IR3843W a space-efficient solution, providing accurate power delivery for low output voltage applications. IR3843W is a versatile regulator which offers programmability of start up time, switching frequency and current limit while operating in wide input and output voltage range. The switching frequency is programmable from 250kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Pre-Bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions. HIGHLY EFFICIENT INTEGRATED 2A SYNCHRONOUS BUCK REGULATOR SupIRBuck TM Boot Vcc Fb Comp Gnd PGnd SW OCSet SS/ SD 4.5V <Vcc<5.5V Vo PGood PGood Enable Rt 1.5V <Vin<16V VinSeq

• Netcom Applications
• Computing Peripheral Voltage Regulators
• General DC-DC Converters

Rev 13.0 2 PD-97507 IR3843WMPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND unless otherwise specified)

• Moisture sensitivity level………………...………………JEDEC Level 2@260 °C (Note5) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Note1: Must not exceed 8V Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC W/C2θ W/C35θ o PCBJ o JA

PACKAGE INFORMATION

M PACKAGE DESIGNATOR

ORDERING INFORMATION

Seq FB COMP Gnd Rt SS OCSet PGood VCC Enable Boot VIN SW

Rev 13.0 3 PD-97507 IR3843WMPbF Block Diagram Fig. 2. Simplified block diagram of the IR3843W

Rev 13.0 4 PD-97507 IR3843WMPbF Pin Description Pin Name Description 1 Seq Sequence pin. Use two external resistors to set Simultaneous Power up sequencing. If this pin is not used connect to Vcc. 2 Fb Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier.

3 Comp

Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb pin to provide loop compensation. 4 Gnd Signal ground for internal reference and control circuitry. 5 Rt Set the switching frequency. Connect an external resistor from this pin to Gnd to set the switching frequency.

6 SS/SD ¯¯

Soft start / shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to Gnd to set the start up time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. 7 OCSet Current limit set point. A resistor from this pin to SW pin will set the current limit threshold. PGood Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to Vcc. If unused, it can be left open.

9 VCC

This pin powers the internal IC and the drivers. A minimum of 1uF high frequency capacitor must be connected from this pin to the power ground (PGnd). 10 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. SW Switch node. This pin is connected to the output inductor. VIN Input voltage connection pin. 13 Boot Supply voltage for high side driver. A 0.1uF capacitor must be connected from this pin to SW.

14 Enable

Enable pin to turn on and off the device. Use two external resistors to set the turn on threshold (see Enable section). Connect this pin to Vcc if it is not used. 15 Gnd Signal ground for internal reference and control circuitry.

Rev 13.0 5 PD-97507 IR3843WMPbF Recommended Operating Conditions Parameter Symbol Test Condition Min TYP MAX Units Power Loss Power Loss Ploss Vcc=5V, V in=12V, Vo=1.8V, Io=2A, Fs=600kHz, L=3.3uH, Note4 0.394 W MOSFET Rds(on) Top Switch R ds(on)_Top VBoot -Vsw =5V, ID=2A, Tj=25oC 24.5 32 Bottom Switch Rds(on)_Bot Vcc=5V, ID=2A, Tj=25oC 24.5 29.5 mΩ Reference Voltage Feedback Voltage V FB 0.7 V 0oC<Tj<125oC -1.0 +1.0 Accuracy -40oC<Tj<125oC, Note3 -2.0 +2.0 Supply Current VCC Supply Current (Standby) ICC(Standby) SS=0V, No Switching, Enable low 500 μA Vcc Supply Current (Dyn) I CC(Dyn) SS=3V, Vcc=5V, Fs=500kHz Enable high 10 mA Under Voltage Lockout VCC-Start-Threshold V CC_UVLO_Start Vcc Rising Trip Level 3.95 4.15 4.35 VCC-Stop-Threshold V CC_UVLO_Stop Vcc Falling Trip Level 3.65 3.85 4.05 Enable-Start-Threshold Enable_UVLO_Start Supply ramping up 1.14 1.2 1.36 Enable-Stop-Threshold Enable_UVLO_Stop Supply ramping down 0.9 1.0 1.06 V Enable leakage current Ien Enable=3.3V 15 μA Electrical Specifications Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. Symbol Definition Min Max Units Vin Input Voltage 1.5 16 Vcc Supply Voltage 4.5 5.5 Boot to SW Supply Voltage 4.5 5.5 Vo Output Voltage 0.7 0.9*Vin V Io Output Current 0 2 A Fs Switching Frequency 225 1650 kHz Tj Junction Temperature -40 125 oC

Rev 13.0 6 PD-97507 IR3843WMPbF Electrical Specifications (continued) Unless otherwise specified, these specifications apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. Parameter Symbol Test Condition Min TYP MAX Units Oscillator Rt Voltage 0.665 0.7 0.735 V Rt=59K 225 250 275 Rt=28.7K 450 500 550 Frequency F S Rt=9.31K, Note4 1350 1500 1650 kHz Ramp Amplitude Vramp Note4 1.8 Vp-p Ramp Offset Ramp (os) Note4 0.6 V Min Pulse Width Dmin(ctrl) Note4 100 Fixed Off Time Note4 130 200 ns Max Duty Cycle Dmax Fs=250kHz 92 % Error Amplifier Input Offset Voltage Vos Vfb-Vseq, Vseq=0.8V -10 0 +10 mV Input Bias Current IFb(E/A) -1 +1 Input Bias Current IVp(E/A) -1 +1 μA Sink Current Isink(E/A) 0.40 0.85 1.2 Source Current Isource(E/A) 8 10 13 mA Slew Rate SR Note4 7 12 20 V/μs Gain-Bandwidth Product GBWP Note4 20 30 40 MHz DC Gain Gain Note4 100 110 120 dB Maximum Voltage Vmax(E/A) Vcc=4.5V 3.4 3.5 3.75 V Minimum Voltage Vmin(E/A) 120 220 mV Common Mode Voltage Note4 0 1 V Soft Start/SD Soft Start Current ISS Source 14 20 26 μA Soft Start Clamp Voltage Vss(clamp) 2.7 3.0 3.3 Shutdown Output Threshold SD 0.3 V Over Current Protection Fs=250kHz 20.8 23.6 26.4 Fs=500kHz 43 48.8 54.6 OCSET Current I OCSET Fs=1500kHz 136 154 172 μA OC Comp Offset Voltage V OFFSET Note4 -10 0 +10 mV SS off time SS_Hiccup 4096 Cycles Bootstrap Diode Forward Voltage I(Boot)=30mA 180 260 470 mV Deadband Deadband time Note4 5 10 30 ns

Rev 13.0 7 PD-97507 IR3843WMPbF Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note4: Guaranteed by Design but not tested in production. Note5: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3 for Consumer market. Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC. Parameter SYM Test Condition Min TYP MAX Units Thermal Shutdown Thermal Shutdown Note4 140 Hysteresis Note4 20 oC Power Good Power Good upper Threshold VPG(upper) Fb Rising 0.770 0.805 0.840 V Upper Threshold Delay VPG(upper)_Dly Fb Rising 256/Fs s Power Good lower Threshold VPG(lower) Fb Falling 0.560 0.595 0.630 V Lower Threshold Delay VPG(lower)_Dly Fb Falling 256/Fs s Delay Comparator Threshold PG(Delay) Relative to charge voltage, SS rising 2 2.1 2.3 V Delay Comparator Hysteresis Delay(hys) Note4 260 300 340 mV PGood Voltage Low PG(voltage) I PGood=-5mA 0.5 V Leakage Current I leakage 0 10 μA Switch Node SW=0V, Enable=0V SW Bias Current Isw SW=0V,Enable=high,SS=3V,Vseq=0V, Note4 μA

Rev 13.0 8 PD-97507 IR3843WMPbF ISS 14.0 16.0 18.0 20.0 22.0 24.0 26.0 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ oC] [uA] Enable(UVLO) Stop 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 -40 -20 0 20 40 60 80 100 120 Temp[ οC] [V] Enable(UVLO) Start 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [V] Vcc(UVLO) Stop 3.76 3.81 3.86 3.91 3.96 4.01 4.06 4.11 4.16 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ oC] [V] Vcc(UVLO) Start 4.06 4.11 4.16 4.21 4.26 4.31 4.36 4.41 4.46 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ oC] [V] IOCSET(500kHz) 43.0 44.0 45.0 46.0 47.0 48.0 49.0 50.0 51.0 52.0 53.0 54.0 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ oC] [uA] FREQUENCY 450 460 470 480 490 500 510 520 530 540 550 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [kHz] Icc(Standby) 150 170 190 210 230 250 270 290 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [uA] TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC) Fs=500 kHz Vfb 686 691 696 701 706 711 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 Temp[ oC] [mV] Ic(Dyn) 8.5 8.6 8.7 8.8 8.9 9.0 9.1 9.2 9.3 9.4 9.5 -40 -20 0 20 40 60 80 100 120 Temp[ oC] [mA]

Rev 13.0 9 PD-97507 IR3843WMPbF Rdson of MOSFETs Over Temperature at Vcc=5V Note: Ctrl-FET and Sync-FET are identical. -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] Resistance [mΩ] Ctrl-FET/Sync-FET

Rev 13.0 10 PD-97507 IR3843WMPbF Typical Efficiency and Power Loss Curves Vin=12V, Vcc=5V, Io=0.2A-2A, Fs=600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. 28.9IHLP2525EZ-01 4.7uH4.73.3 28.9IHLP2525EZ-01 4.7uH4.72.5 19.9IHLP2525EZ-01 3.3uH3.31.8 13IHLP2525EZ-01 2.2uH2.21.2 19.9IHLP2525EZ-01 3.3uH3.31.5 32.7IHLP2525EZ-01 5.6uH5.65 13IHLP2525EZ-01 2.2uH2.21.1 13IHLP2525EZ-01 2.2uH2.21 13IHLP2525EZ-01 2.2uH2.20.9 DCR (mΩ) P/NL (uH)Vout (V) 28.9IHLP2525EZ-01 4.7uH4.73.3 28.9IHLP2525EZ-01 4.7uH4.72.5 19.9IHLP2525EZ-01 3.3uH3.31.8 13IHLP2525EZ-01 2.2uH2.21.2 19.9IHLP2525EZ-01 3.3uH3.31.5 32.7IHLP2525EZ-01 5.6uH5.65 13IHLP2525EZ-01 2.2uH2.21.1 13IHLP2525EZ-01 2.2uH2.21 13IHLP2525EZ-01 2.2uH2.20.9 DCR (mΩ) P/NL (uH)Vout (V) Iout (A) Efficiency (%) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 Iout (A) Power Loss (W)

Rev 13.0 11 PD-97507 IR3843WMPbF Typical Efficiency and Power Loss Curves Vin=5V, Vcc=5V, Io=0.2A-2A, Fs=600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. 6.7PCMB065T-1R5MS1.50.7 6.7PCMB065T-1R5MS1.50.75 13IHLP2525EZ-01 2.2uH2.23.3 19.9IHLP2525EZ-01 3.3uH3.32.5 13IHLP2525EZ-01 2.2uH2.21.8 13IHLP2525EZ-01 2.2uH2.21.2 13IHLP2525EZ-01 2.2uH2.21.5 13IHLP2525EZ-01 2.2uH2.21.1 13IHLP2525EZ-01 2.2uH2.21 6.7PCMB065T-1R5MS1.50.9 DCR (mΩ) P/NL (uH)Vout (V) 6.7PCMB065T-1R5MS1.50.7 6.7PCMB065T-1R5MS1.50.75 13IHLP2525EZ-01 2.2uH2.23.3 19.9IHLP2525EZ-01 3.3uH3.32.5 13IHLP2525EZ-01 2.2uH2.21.8 13IHLP2525EZ-01 2.2uH2.21.2 13IHLP2525EZ-01 2.2uH2.21.5 13IHLP2525EZ-01 2.2uH2.21.1 13IHLP2525EZ-01 2.2uH2.21 6.7PCMB065T-1R5MS1.50.9 DCR (mΩ) P/NL (uH)Vout (V) 100 Iout (A) Efficiency (%) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Iout (A) Power Loss (W)

of the switching frequency and hence, of Rt. shutdown by pulling the soft-start pin below 0.3V. voltage at the Soft Start pin. the current limit set point. Table 1. shows I tabulates the oscillator frequency versus Rt. soft start function in hiccup mode. OCP signal resets and the converter recovers. Table 1. Switching Frequency and IOCSet vs. 160 ns after the low gate drive rises to about 3V. This delay functions to filter out switching noise.

Rev 13.0 15 PD-97507 IR3843WMPbF Thermal Shutdown Temperature sensing is provided inside IR3843W. The trip threshold is typically set to 140 oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20 oC hysteresis in the thermal shutdown threshold. Fig. 8b. Application Circuit for Simultaneous Sequencing Simultaneous Powerup Vo1 Vo2 Output Voltage Sequencing The IR3843W can accommodate user programmable sequencing using Seq, Enable and Power Good pins. Boot Vcc Fb Comp Gnd PGnd SW OCSet SS/ SD 4.5V <Vcc<5.5V Vo(master) PGood PGood Enable Rt 1.5V <Vin<16V Vin Seq RA RB Boot Vcc Fb Comp Gnd PGnd SW OCSet SS/ SD 4.5V <Vcc<5.5V Vo(slave) PGood PGood Enable Rt 1.5V <Vin<16V Vin Seq Vo(master) RC RD RE RF Fig. 8a. Simultaneous Power-up of the slave with respect to the master. Power Good Output The IC continually monitors the output voltage via Feedback (Fb pin). The feedback voltage forms an input to a window comparator whose upper and lower thresholds are 0.805V and 0.595V respectively. Hence, the Power Good signal is flagged when the Fb pin voltage is within the PGood window, i. e., between 0.595V to 0.805V, as shown in Fig .9 The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Fig. 9a shows the PGood timing diagram for non- tracking operation. In this case, during startup, PGood goes high after the SS voltage reaches 2.1V if the Fb voltage is within the PGood show a 256 cycle delay between the Fb voltage entering within the thresholds defined by the PGood window and PGood going high. Through these pins, voltage sequencing such as simultaneous and sequential can be implemented. Figure 8. shows simultaneous sequencing configurations. In simultaneous power-up, the voltage at the Seq pin of the slave reaches 0.7V before the Fb pin of the master. For R E/RF =RC/RD, therefore, the output voltage of the slave follows that of the master until the voltage at the Seq pin of the slave reaches 0.7 V. After the voltage at the Seq pin of the slave exceeds 0.85V, the internal 0.7V reference of the slave dictates its output voltage. It is recommended that irrespective of the sequencing configuration used, the input voltage should be allowed to come up to its nominal value first, followed by V cc and Enable, before the sequencing signal is applied. For non-sequenced operation, the Seq pin should be tied to a voltage greater than 0.85V, such as 3.3V or V cc. Again, the input voltage should be allowed to come up before V cc and Enable.

Rev 13.0 16 PD-97507 IR3843WMPbF TIMING DIAGRAM OF PGOOD FUNCTION Fig.9a IR3843W Non-Tracking Operation (Seq=Vcc) Fig.9b IR3843W Tracking Operation

Rev 13.0 17 PD-97507 IR3843WMPbF Minimum on time Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3843W, the typical minimum on-time is specified as 100 ns. Any design or application using the IR3843W must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 150 ns. This is necessary for the circuit to operate without jitter and pulse- skipping, which can cause high inductor current ripple and high output voltage ripple. In any application that uses the IR3843W, the following condition must be satisfied: The minimum output voltage is limited by the reference voltage and hence V out(min) = 0.7 V. Therefore, for Vout(min) = 0.7 V, Therefore, at the maximum recommended input voltage 16V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 290 kHz. However, practical considerations dictate that any application that demands a pulse width smaller than 175ns may not exhibit jitter free operation over the entire load range. This means that for 16 V input voltage, the operation frequency should be limited to 250 kHz. V/s.ns 150 V0.7V V in (min) (min) in 610674 ×=≤×∴ ≤×∴ s on out s F t V F Maximum Duty Ratio Considerations A fixed off-time of 200 ns maximum is specified for the IR3843W. This provides an upper limit on the operating duty ratio at any given switching frequency. It is clear t hat, higher the switching frequency, the lower is the maximum duty ratio at which the IR3843W can operate. To allow a margin of 50ns, the maximum operating duty ratio in any application using the IR3843W should still accommodate about 250 ns off-time. Fig 10. shows a plot of the maximum duty ratio v/s the switching frequency, with 250 ns off-time. s out s on F V F Dt V in ×= (min) (min) (min) on out sin sin out on onon t VFV FV Vt tt ≤×∴ ×≤∴ Fig. 10. Maximum duty cycle v/s switching frequency. Max Duty Cycle 250 450 650 850 1050 1250 1450 1650 Switching Frequency (kHz) Max Duty Cycle (%)

Rev 13.0 18 PD-97507 IR3843WMPbF when an external resistor divider is connected to the output as shown in figure 11. Equation (7) can be rewritten as: For the calculated values of R8 and R9 see feedback compensation section. Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. From (1), for a desired start-up time of the converter, the soft start capacitor can be calculated by using: Where T start is the desired start-up time (ms). For a start-up time of 3.5ms, the soft-start capacitor will be 0.099 μF. Choose a 0.1 μF ceramic capacitor. Bootstrap Capacitor Selection To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected the source of the Control FET . This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C6), as shown in Fig. 12.. The operation of the circuit is as follows: When the lower MOSFET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards V cc through the internal bootstrap diode, which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C6 is approximately given as When the upper MOSFET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage V in. However, if the value of C6 is appropriately chosen,

Application Information

Design Example: The following example is a typical application for IR3843W. The application circuit is shown on page 23. Enabling the IR3843W As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage. For a typical Enable threshold of V EN = 1.2 V For a Vin (min) =10.2V, R1=49.9K and R2=7.5K is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 23.7 k Ω, using Table. 1. Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.7V. The divider is ratioed to provide 0.7V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: kHz600 =F 54mV ΔV A2 =I V1.8 =V max) 13.2V ( V12 =V s o o o in ⎛ +∗= 81 R RVV refo Fig. 11. Typical application of the IR3843W for programming the output voltage VRR refo ref −∗= 89 Fb IR3624 VOUT IR3843W IR3843W Enable Vin VRR VV VRR EN)in( min −= 12

Rev 13.0 19 PD-97507 IR3843WMPbF Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: Where: If Δi ≈ 40%(I o), then the output inductor is calculated to be 3.19μH. Select L=3.3 μH. The IHLP2525EZ-01 3.3uH from Vishay provides a compact, low profile inductor suitable for this application the voltage Vc across C6 remain s approximately unchanged and the voltage at the Boot pin becomes A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple current generated during the on time of the upper MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by: Where: D is the Duty Cycle I RMS is the RMS value of the input capacitor current. Io is the output current. For I o=2A and D = 0.15, the IRMS = 0.71 A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 1x10uF 25V ceramic capacitor C3216X5R1E106M from TDK. In addition to these, although not mandatory, a 1X330uF, 25V SMD capacitor EEV-FK1E331P may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. in o V VD = )( iΔ cycleDuty time on Turn frequency Switching current ripple Inductor VoltageOutput voltage input Maximum D Δt F Δi V V s o in sin o oin s oin FiV VVVL FDtt iLVV Δ∗∗−= ∗=ΔΔ Δ∗=− 1 L IR3843W VcC6 VIN Vcc SW Boot PGnd Fig. 12. Bootstrap circuit to generate Vc voltage

Rev 13.0 20 PD-97507 IR3843WMPbF Phase FLC -1800 Frequency Gain FLC 0 dB Frequency -40dB/decade current ripple Inductor ripple voltage Output )()()( Δ=Δ ⎛ −=Δ Δ=Δ Δ+Δ+Δ=Δ L o so L Co oin ESLo LESRo CoESLoESRoo I V FC IV ESLL VVV ESRIV VVVV Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3843W can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Two of the Panasonic ECJ- 2FB0J226ML (22uF, 6.3V, 3mOhm) capacitors is a good choice. Feedback Compensation The IR3843W is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0 dB crossing frequency and adequate phase margin (greater than 45 o). The output LC filter introduces a double pole, –40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see figure 13). The resonant frequency of the LC filter is expressed as follows: Figure 13 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. The IR3843W uses a voltage-type error amplifier with high-gain (110dB) and wide-bandwidth. The output of the amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. Local feedback with Type II compensation is shown in Fig. 14. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor is expressed as follows: oo LC CL F Fig. 13. Gain and Phase of LC filter o ESR *ESR*CF π∗= 2 Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as

Rev 13.0 21 PD-97507 IR3843WMPbF The transfer function (Ve/Vo) is given by: The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: First select the desired zero-crossover frequency o): Use the following equation to calculate R3: VOUT VREF CPOLE C4R3 Ve FZ FPOLE E/A Zf Frequency Gain(dB) H(s) dB Fb Comp ZIN Fig. 14. Type II compensation network and its asymptotic gain plot 431 CsR CsR Z ZsHV V IN f o e +−=−== CRF R RsH z π= () sESRo FFF *1/10~1/5 F and o ≤> *** LCin ESRoosc FV RFFVR = Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Use equations (20), (21) and (22) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: The pole sets to one half of the switching frequency which results in the capacitor C POLE: For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, we should implement local feedback with a type III compensation network. The typically used compensation network for voltage-mode controller is shown in figure 15. Again, the transfer function is given by: By replacing Z in and Zf according to figure 15, the transfer function can be expressed as: oo z LCz CL F FF 1750 POLE POLE P CC CCR F π s s POLE *F*R C*F*R C ππ IN f o e Z ZsHV V −== )( ()[ ] (25) .... )(*)( )()( 710 3348 108743 CsRCC CCsRCCsR RRsCCsRsH +++ +++−=

Rev 13.0 22 PD-97507 IR3843WMPbF Tantalum CeramicFLC<Fo<FESRType III Electrolytic TantalumFLC<FESR<Fo<Fs/2Type II Output CapacitorFESR vs Fo Compensator Type Tantalum CeramicFLC<Fo<FESRType III Electrolytic TantalumFLC<FESR<Fo<Fs/2Type II Output CapacitorFESR vs Fo Compensator Type The compensation network has three poles and two zeros and they are expressed as follows: Cross over frequency is expressed as: Fig.15. Type III Compensation network and its asymptotic gain plot 871087 710 RCRRCF CRF CR CC CCR F CRF F Z Z P P P ππ π ππ π ≅+= ooosc in o CLV VCRF π2 73= The higher the crossover frequency, the potentially faster the load transient response. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency is selected such that The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45 o for overall stability. For this design we have: Vin=12V Vo=1.8V Vosc=1.8V Vref=0.7V Lo=3.3 uH Co=2x22uF, ESR=3mOhm each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design is 12uF at 1.8 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency F LC and using equation (16) to compute the small signal C These result to: FLC=17.88 kHz FESR=4.4 MHz Fs/2=300 kHz Select crossover frequency: Fo=80 kHz Since FLC<Fo<Fs/2<FESR, TypeIII is selected to place the pole and zeros. VOUT VREF R8R10 C4R3 Ve FZ1 FZ2 FP2 FP3 E/A Zf ZIN Frequency Gain(dB) H(s) dB Fb Comp Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. The table below shows the compensation types and location of the crossover frequency.

Rev 13.0 23 PD-97507 IR3843WMPbF Detailed calculation of compensation TypeIII Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (R OCSET) from the SW pin to the OCSet pin. The resistor can be calculated by using equation (4). This resistor R OCSET must be placed close to the IC. The R DS(on) has a positive temperature coefficient and it should be considered for the worst case operation. Setting the Power Good Threshold A window comparator internally sets a lower Power Good threshold at 0.6V and an upper Power Good threshold at 0.8V. When the voltage at the FB pin is within the window set by these thresholds, PGood is asserted. The PGood is an open drain output. Hence, it is necessary to use a pull up resistor R PG from PGood pin to Vcc. The value of the pull-up resistor must be chosen such as to limit the current flowing into the PGood pin, when the output voltage is not in regulation, to less than 5 mA. A typical value used is 10 kΩ. Ω=Ω= ==≅ Ω=Ω= k 54.1 Select k 55.1R kHz) 600 (atμA 59.07I ) current output nominal over (50% A 31.5 A2 m 30.6251.25m 24.5 OCSet OCSet R F II R s LIMoSET onDS )( R IRII onDS OCSetOCSet criticalLSET ∗== Ω=Ω== Ω== Ω=Ω== === === Ω== =Θ− Θ+= =Θ+ Θ−= k 3.16R :Select k 3.18R ;R*VV VR k4.99 R:Select ,k 5R ;RF*C*R 158R :Select , 160R ;F*C*R :R and R ,R Calculate pF 180C :Select ,pF 193.62C ;R*F*C nF 2.8C :Select nF, 24.8C ;R*F*2 k 74.2 R :Select k 2.71R;V*C V*C*L*F*R :C and C ,R Calculate nF 2.2C :Select kHz 300F*0.5F and kHz 7.05 F*.F :Select kHz 453.7 sin sinFF kHz 14.11 sin sinFF

70 Margin Phase Desired

Z P P in oscooo sP ZZ oP oZ o 9989 810 1010 9810 433 π π π π

Rev 13.0 24 PD-97507 IR3843WMPbF Application Diagram: Fig. 16. Application circuit diagram for a 12V to 1.8 V, 2 A Point Of Load Converter Suggested Bill of Materials for the application circuit: Part Reference Quantity Value Description Manufacturer Part Number Cin 1 330uF SMD Elecrolytic, Fsize, 25V, 20% Panasonic EEV-FK1E331P 1 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M CVcc 1 1uF 1uF, 10V, X5R,0805 Panasonic ECJ-2FB1C105K Lo 1 3.3uH 3.3uH,8A,20%,6.5MMx7MM Vishay/Dale IHLP2525EZ-01 3.3uH Co 2 22uF 0805, 6.3V, X5R, 20% Panasonic ECJ-2FB0J226M R1 1 49.9k 49.9K,0603,1/10 W,1% Rohm MCR03EZPFX4992 R2 1 7.5k 7.5K,0603,1/10W,1% Rohm MCR03EZPFX7501 R t 1 23.7k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX2372 ROCSet 1 1.54K 0603,1/10 W,1% Rohm MCR03EZPFX1541 RPG 1 10K 0603,1/10 W,1% Rohm MCR03EZPFX1002 Css 1 0.1uF 0603, 25V, X7R, 10% Panasonic - ECG ECJ-1VB1E104K R3 1 2.74k 0603,1/10W,1% Rohm MCR03EZPFX2741 C3 1 180pF 50V, 0603, NP0, 5% Murata GRM1885C1H181JA01D C4 1 8200pF 0603, 50V, X7R, 10% Panasonic - ECG ECJ-1VB1H822K R8 1 4.99k 0603,1/10W,1% Rohm MCR03EZPFX4991 R9 1 3.16k 0603,1/10W,1% Rohm MCR03EZPFX3161 R10 1 158 0603,1/10W,1% Panasonic ERJ-3EKF1580V C7 1 2200pF 0603, 50V, X7R, 10% Panasonic - ECG ECJ-1VB1H222K U1 1 IR3843W SupIRBuck PQFN 5x6mm International Rectifier IR3843WMPbF

Rev 13.0 25 PD-97507 IR3843WMPbF TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-2A, Room Temperature, No Air Flow Fig. 21. Inductor node at 2A load Ch2:LX Fig. 22. Short (Hiccup) Recovery Ch2:Vo , Ch3:VSS Fig. 18. Start up at 2A Load, Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:VPGood Fig. 17. Start up at 2A Load Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:Enable Fig. 19. Start up with 1.62V Pre Bias, 0A Load, Ch2:Vo, Ch3:VSS Fig. 20. Output Voltage Ripple, 2A load Ch2: Vo

Rev 13.0 26 PD-97507 IR3843WMPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=1A-2A, Room Temperature, No Air Flow Fig. 23. Transient Response, 1A to 2A step 2.5A/μs Ch1:Vo, Ch4:Io

Rev 13.0 27 PD-97507 IR3843WMPbF TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=2A, Room Temperature, No Air Flow Fig. 24. Bode Plot at 2A load shows a bandwidth of 86kHz and phase margin of 56 degrees

Rev 13.0 28 PD-97507 IR3843WMPbF Simultaneous Tracking at Power Up and Power Down Vin=12V, Vo=1.8V, Io=2A, Room Temperature, No Air Flow Fig. 25: Simultaneous Tracking a 3.3V input at power-up and shut-down Ch2: Vout Ch3:SS Ch4: Seq Fb IR3624 VOUT IR3843W 3.3V Rs2 Rs1 Seq 4.99K4.99K 3.16K 3.16K

Rev 13.0 29 PD-97507 IR3843WMPbF Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3843W should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the Vin pin of IR3843W. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. PGndVin AGnd Vout PGndVin AGnd Vout The connection between the OCSet resistor and the Sw pin should not share any trace with the connection between the bootstrap capacitor and the Sw pin. Instead, it is recommended to use a Kelvin connection of the trace from the OCSet resistor and the trace from the bootstrap capacitor at the Sw pin. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 26 illustrates the implementation of the layout guidelines outlined above, on the IRDC3843W 4 layer demoboard. PGndVin AGnd Vout All bypass caps should be placed as close as possible to their connecting pins. Resistors Rt and Rocset should be placed as close as possible to their pins. Enough copper & minimum length ground path between Input and Output PGnd Vin AGnd Vout Compensation parts should be placed as close as possible to the Comp pin. Fig. 26a. IRDC3843W demoboard layout considerations – Top Layer

Rev 13.0 30 PD-97507 IR3843WMPbF PGnd Vin AGnd Power Ground Plane Analog Ground plane Single point connection between AGND & PGND, should be close to the SupIRBuck, kept away from noise sources. Use separate traces for connecting Boot cap and Rocset to the switch node and with the minimum length traces. Avoid big loops. Fig. 26c. IRDC3843W demoboard layout considerations – Mid Layer 1 Fig. 26d. IRDC3843W demoboard layout considerations – Mid Layer 2 Feedback trace should be kept away form noise sources Fig. 26b. IRDC3843W demoboard layout considerations – Bottom Layer

Rev 13.0 31 PD-97507 IR3843WMPbF PCB Metal and Components Placement Lead lands (the 11 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. Pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper.

Rev 13.0 32 PD-97507 IR3843WMPbF Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.

Rev 13.0 33 PD-97507 IR3843WMPbF Stencil Design

• The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.

Rev 13.0 34 PD-97507 IR3843WMPbF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market (Note5) Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 08/12 BOTTOM VIEW