E52140A62CXX2

E521.40 ELMOS | Alldatasheet

Document overview

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Technical content

Features

• Transceiver compliant with PSI5 standard v1.3 and v2.1
• Provides two independent master channels (up to 6 sensors each)
• Supporting 125 Kbit/s and 189 Kbit/s protocols
• Supporting synchronous and asynchronous opera- tion modes
• Various diagnostic features
• Internal sync-voltage generation
• Programmable PSI5 channel voltage 4.6V to 11V
• Automatic threshold adaption to sensor quiescent current
• Reverse polarity protected bus outputs up to 40V
• Enables operation in powertrain and chassis control systems
• Developed according to ISO 26262, based on safety requirements rated up to ASIL C.
• Operating temperature range -40° C to +125° C

Applications

• Safety (airbag) control systems
• Powertrain control systems
• Vehicle dynamics control system General Description The E521.40 was developed to manage the connection and communication between a micro controller unit and up to 12 sensor satellites. Data transmission from the sensor to ECU is done by current modulation on the power supply lines with data rate of 125 Kbit/s or 189 Kbit/s (Manchester coded). Data transmission from ECU to sensor is done by voltage modulation on the power supply. It supports bid- irectional communication. Two methods are supported:
• tooth gap method
• pulse width method The device is a PSI5 V1.3 and V2.1 compliant trans- ceiver which provides two independently operating channels. The channels are able to communicate in low power-, standard-, synchronous- and asynchronous operating mode. The communication to µC is done via the SPI or UART interface.

Ordering Information

Ordering-No.: Features Package E52140A62CXX2 2-channel QFN20L5 E52140A55E 2-channel SOIC20 Typical Application Circuit Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.0 4

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Functional Diagram E521.40 CSYNC CP2 CP1 VBUS Receiver Threshold Adaption Timeslot Control Status Register Manchester Decoder Data Register SYNC Control Oscillator UA RT / SPI Interface CFG Register Error Detection Current Limitation Active Discharge VSYNC Charge Pump VDD_INT Bandgap References VSUPP LY VG VBUS LDO Control NCS SDO / RXD SDI /TXD SCLK NRES TRIG VDD 2 2 SIF1 SIF2 Bus Enable Reverse Prot SYNC CTR Reverse Prot Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

1 Package Pinout QFN20L5, SOIC20

Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

1.1 Pin Description QFN20L5

Table 1.1-1: Pin Description No Name Type Description

1 DGND S Digital voltage supply

2 VDD S Digital voltage supply

3 AGND S Analog ground

4 SIF1 HV_A_O Sensor Interface 1

5 NC Not connected

6 PGND S Power ground

7 CP2 HV_A_O Sync charge pump fly capacitor

8 VBUS HV_S VBUS voltage

9 CP1 HV_A_O Sync charge pump fly capacitor

10 CSYNC HV_S Sync supply voltage

11 NC Not connected

12 SIF2 HV_A_O Sensor Interface 2

13 VG HV_A_O Gate voltage for external transistor

14 VSUPPPLY HV_S Supply voltage

15 NRES D_I Negative reset and test mode pin

16 TRIG D_I Sync pulse trigger input

17 NCS D_I SPI chip select

18 SDI_RXD D_I SPI or UART data input

19 SDO_TXD D_O SPI or UART data output

20 SCLK D_I SPI clock input

Exposed Pad. Connect to large copper ground plane for optimal heat dissipation. Connect to GNDA and GNDD. Note: A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

1.2 Pin Description SOIC20

Table 1.2-1: Pin Description No Name Type Description

1 SDO_TXD D_O SPI or UART data output

2 SCLK D_I SPI clock input

3 DGND S Digital ground

4 VDD S Digital voltage supply

5 AGND S Analog ground

6 SIF1 HV_A_O Sensor Interface 1

7 NC Not connected

8 PGND S Power ground

9 CP2 HV_A_O Sync charge pump fly capacitor

10 VBUS HV_S VBUS voltage

11 CP1 HV_A_O Sync charge pump fly capacitor

12 CSYNC HV_S Sync supply voltage

13 NC Not connected

14 SIF2 HV_A_O Sensor Interface 2

15 VG HV_A_O Gate voltage for external transistor

16 VSUPPPLY HV_S Supply voltage

17 NRES D_I Negative reset and test mode pin

18 TRIG D_I Sync pulse trigger input

19 NCS D_I SPI chip select

20 SDI_RXD D_I SPI or UART data input

Note: A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

2 Application Description

2.1 Application Circuits

2.1.1 Application Circuits

Pin NCS: terminate with GND for UART-mode only, otherwise is used internal pull-up for SPI-mode. Pin VSUPPLY: terminate with GND if LDO is not used. Pin VG: terminate with GND if LDO is not used. Pin CP1: no termination (OPEN) if charge pump is not used. Pin CP2: no termination (OPEN) if charge pump is not used (must not be connected to GND!!!). Pin CSYNC: short to VBUS for asynchronous mode. The CSYNC voltage can be supplied on pin CSYNC (if available on ECU) without using the charge pump. This option is not shown here. ATIC158 CLC E R E2 Ch1_sensor 1Wiring CL LW /2 CW CE RE2 SIF 2 SIF 1 ZS ECU LW /2 RW /2 RW /2 Ch2_sensor 1Wiring LW /2 CW ZS LW /2 RW /2 RW /2 Ch2_sensor 2 ZS VSUPPLY C BUS VBUS VG VSU PPLY (eg . battery ) CG EMC filter (TBD) NCS SCLK SDO _TXD SDI _RXD CP 1 CP 2 CSYNC CSY NC CCP Optional: VC S YN C GNDA GNDD TRIG VDD NRES CDD GNDP VDD Power supply & Reset µC SPI CEMC R EMC NMOS K CSYNC E521.40A CEMC REMC Figure 2.1.1-1: Application Circuit with LDO Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 ATIC158 CLC E R E2 Ch1_sensor 1Wiring CL LW /2 CW CE RE2 SIF 2 SIF 1 ZS ECU LW /2 RW /2 RW /2 Ch2_sensor 1Wiring LW /2 CW ZS LW /2 RW /2 RW /2 Ch2_sensor 2 ZS VSUPPLY C BUS VBUS VG VSU PPLY (eg . battery ) NCS SCLK SDO _TXD SDI _RXD CP 1 CP 2 CSYNC CSY NC CCP Optional: VC S YN C GNDA GNDD TRIG VDD NRES CDD GNDP VDD Power supply & Reset µC SPI CSYNC E521.40A Figure 2.1.1-2: Application Circuit with VBUS Supplied from ECU Table 2.1.1-1: Application Circuit Electrical Parameter Description Condition Symbol Min Typ Max Unit Capacitance at VDD CVDD 100 220 nF ECU bus capacitance CE 15 35 nF ECU resistor RE2 2.0 Ω Satellite capacitance CL 2.2 nF Total bus capacitance CE+C L_X (x=1..3) 25 107 nF LDO Output capacitor Ceramic capacitor, ΩESR<=100m CBUS 4.7 20 μF Charge pump fly capacitor Ceramic capacitor; ΩESR <= 100m CCP 270 nF Charge pump storage capacitor Ceramic capacitor; ΩESR <= 100m CSYNC 14.1 20 μF VSUPPLY EMC capacitor CEMC 220 nF VSUPPLY EMC resistor REMC 100 Ω Single wire resistance RW/2 0.5 Ω Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Description Condition Symbol Min Typ Max Unit Wire inductance 2*(L W/2) 0 8.7 μH Wire capacitance CW 0 600 pF The device can be supplied via pin V SUPPLY with an appropriate voltage. This voltage supplies an external NMOS transistor that is driven by an internal LDO via the pin V G. The following external NMOS transistor are recommended:

• IRFZ24NS,
• BUK7635-55A,
• HUFA76409D3ST,
• SQD15N06-42L. The stability of the output voltage can be achieved with an external compensation capacitor C K connected between pin V G and AGND. In the following table is shown a suitable compensation capacitor C K: Table 2.1.1-2: Recommended Compensation Capacitor Transistor CK IRFZ24NS 100nF-220nF BUK7635-55A 100nF-220nF HUFA76409D3ST 100nF-220nF SQD15N06-42L 100nF-220nF Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

3 Functional Safety

3.1 Functional Safety Requirements

The device fulfils the functional safety requirement up to ASIL-Level C (system) according to ISO 26262, depending on the safety mechanisms used.

3.2 FMEDA

The following toplevel safety requirements were analysed with FMEDA method:

• TSR1: Transceiver shall avoid transmission of corrupted data to the micro controller interface
• TSR2: Transceiver shall avoid storage of corrupted safety related data

3.2.1 Safety Measures mandatory to reach ASIL Level C

Table 3.2.1-1: mandatory safety mechanisms for ASIL C derived from FMEDA Safety Mechan- ism IC / System level

Description

SM1 IC Synchronous decoding of input data in Manchest er decoder with fixed baud rate, fixed frame length and fixed bit count. Decoding errors will be indicated in the error status and potentially corrupted data will be invalidated. SM2 IC Data consistency check using parity bit or CRC error detection mechanism. Note: These mechanisms must be enabled by interface configuration options from system level. SM3 System Observe failure rate of Manchester decoder or parity/CRC errors on system level in order to detect channels with latent faults that could degrade the robustness of decoding or even cause spurious data corruption. SM4 System / IC Internal supplies and references are monitored cyclically with a sampling interval of typ. 2ms. Diagnosis block has a separate reference voltage gener- ation independent from the reference of analyzed signals. Supervisor function is implemented for the following signals: V BUS , V CSYNC , V SIF1 , V SIF2 , VDD, V DD_INT , VCP_GATE . SM5 System Data consistencies check using CRC error d etection mechanism for SPI and UART. SM6 System Configuration data written to registers of the IC shall be (cyclically) verified by reading them back. Available configuration lock mechanisms shall be used. SM7 System Compare the SPI response with the command ( address, command,CHID,BID, except frame data, register data & XCRC) SM8 System Compare the frame ID, ch ID (if not all CH configurations are same) with respect to the configuration & calculate and compare the 3-bit CRC/parity for the sensor data SM9 System If interface/asic error indicated, read th e error status registers SM10 System If start-or stop bit in UART is not detec ted in time uC can detect UART error on transceiver SM11 System Loop Back Diagnosis: Check digital data p rocessing (Manchester decoder / Data latch / MUX / XCRC / UART/SPI). Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

4 Operating Conditions

Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the opera- tional sections of this document is not implied. Exposure to absolute maximum rated conditions for extended peri- ods may affect device reliability. All voltages referred to V(GND). Currents flowing into terminals are positive, those drawn out of a terminal are negative.

4.1 Absolute Maximum Ratings

Table 4.1-1: ESD requirements No. Description Condition Symbol Min Max Unit

1 ESD according Human Body Model (HBM),

Ωfor pins SIFx; VSUPPLY; (100pF/1.5k ) ESD pins SIFX,VSUPPL Y ±4000 V

2 ESD according Human Body Model (HBM),

Ωfor all other pins; (100pF/1,5k ) ESD all other pins ±2000 V

3 ESD according Charged Device Model (CDM),

±750 V

4 ESD according Charged Device Model (CDM),

±450 V

5 Input voltage range (supply from ECU) V

SUPPPLY -0.3 40 V 6 V BUS voltage range VBUS -0.3 40 V 7 NMOS gate voltage at pin V G VG -0.3 40 V 8 Voltage of charge pump fly cap. - negative pin V CP1 -0.3 40 V 9 Voltage of charge pump fly cap. - positive pin V CP2 -0.3 40 V

10 Voltage of charge pump storage capacitor or

CSYNC voltage supply (from ECU) VSYNC -0.3 40 V 11 Voltage at sensor interface X=1-2 V SIF_X -0.3 40 V

12 Supply voltage for analog blocks and digital I/O

VDD -0.3 19 V 13 Voltage of digital input pins VIN_DIG -0.3 19 V 14 Voltage of the digital outputs pins VOUT_DIG -0.3 19 V 15 Voltage of NRES and testmode pin VNRES -0.3 19 V

16 Junction temperature TJ -40 150 oC

17 Storage temperature TSTG -40 125 oC

18 Ambient operating temperature range TAMB -40 125 oC

19 Thermal Resistance (junction-ambient) (refer to

application notes of QFN-packages, thermal con- nection of exposed die pad very important) R TJA 23 K/W Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

4.2 Recommended Operating Conditions

Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified. All voltages are referred to ground (0V). Currents flowing into the circuit have positive values. The first electrical potential connected to the IC must be GND. (If not specified specify timing sequence of electrical contacts.) Table 4.2-1: Recommended Operation Conditions No. Description Condition Symbol Min Typ Max Unit

1 Input voltage range at pin V

1) Application with LDO and external NMOS transistor; low voltage mode; V SUPPLY_lp 5.3 19 V

2 Input voltage range at pin V SUPPLY 1) Application with

transistor; standard voltage mode; V SUPPLY_std 6.95 19 V

3 Input voltage range at pin V SUPPLY 1) Application with

transistor; increased voltage mode; V SUPPLY_inc 8.0 19 V

4 Input voltage range at pin V BUS limited

range 2) Application with (externally gen- erated) available V BUS voltage; @ I SIFX_OP =0- 25mA LDO is disabled V BUS_SUP_lr 4.6 5.05 V

5 Input voltage range at pin V BUS full range 3) Application with

(externally gen- erated) available V BUS voltage; @ I SIFX_OP =0- 65mA LDO is disabled V BUS_SUP_fr 5.05 11 V

6 V BUS voltage ripple;

50Hz<f<50kHz 3) Application with (externally gen- erated) available V BUS voltage; LDO is disabled VBUS_SUP_RPL 100 mVpp

7 V BUS voltage ripple;

50kHz<f<500kHz 3) Application with (externally gen- erated) available V BUS voltage; LDO is disabled VBUS_SUP_RPL 40 mVpp Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 No. Description Condition Symbol Min Typ Max Unit

8 V CSYNC voltage input range 4) Application with

voltage; VCSYNC Vt3 +V CSYN C_DR 35 V

9 V CSYNC voltage ripple Application with

voltage; VCSYNC_RPL 500 mVpp 10 Digital supply voltage 3V3-mode V DD 2.97 3.63 V 11 Digital supply voltage 5V-mode V DD 4.5 5.5 V 12 5) VBUS voltage rising slew rate VBUS_RISE 8/C SYN C V/µs 13 Sensor quiescent current Standard current I LOW_std -19.0 -4 mA 14 Sensor quiescent current Extended current I LOW_ext -35.0 -4 mA 15 Sensor sink current Low power mode ΔIS_lp -15.0 -13.0 -11.0 mA 16 Sensor sink current Common mode ΔIS_ext -30.0 -26.0 -22.0 mA 17 Sensor interface current, low power mode I SIFX =-(I low Δ+ I S) I SIFX_OP_lp -50.0 -4.0 mA 18 Sensor interface current,increased mode I SIFX =-(I low Δ+ I S) I SIFX_OP_inc -65.0 -4.0 mA

19 Clock frequency depending on UART data

UART mode f SCLK_EXT 13 32 MHz

20 Baud rate UART mode f UART fSCLK_EX

21 Duty cycle of f SCLK_EXT UART mode DC SCLK_EXT 30 70 %

22 Frequency deviation of f SCLK_EXT UART

mode,maximum deviation with one UART tele- gram (11 bit) FDEV SCLK_EXT -1.5 1.5 %

23 SPI frequency 50% duty cycle f SCLK 0 5 MHz

1) The following external NMOS transistors are recommended: IRFZ24NS, BUK7635-55A, HUFA76409D3ST and SQD15N06-42L. The max.input current of V SUPPLY is 350mA (operating mode). Max. value including: 4 sensor interfaces including current modulation, CSYNC charge pump avg.current, short circuit for one interface and internal current consumption. 2) Limited range of I SIFX : V BUS_min =4.6V with I SIFX_OPM =25mA (I LOW =10mA and I SINK =15mA) 3) Full range of I SIFX operating 4) V SYNC_DR is the voltage drop between V CSYNC and V SIFx , Vt3 see Figure 6.1.3.6-1 5) To limit the current through schottky diodes and CSYNC capacitor to 8A Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

5 Detailed Electrical Specification

5.1 ANALOG PART

5.1.1 SUPPLY

Table 5.1.1-1: Current Consumption: Electrical Parameter Table No. Description Condition Symbol Min Typ Max Unit 1 I VSUPPLY quiescent current consumption *) 1) Application with LDO disabled I VSUPPLY_Q 15 µA

2 I VSUPPLY current consumption operating 1) Application with

I VSUPPLY_OP 0.1 1 mA

3 I VBUS quiescent current consumption Application with

voltage; interfaces off I VBUS_Q 0.5 2 mA

4 I VBUS current consumption operating Application with

voltage; interfaces on; without load; I VBUS_OP 3 7 mA

5 I CSYNC quiescent current consumption Application with

voltage; interfaces on; without load; I CSYNC_Q 2.5 mA 6 Logic supply operating current VDD=5.5V;NRE S=0V IVDD_off 4 10 mA 7 Logic supply operating current VDD=5.5V;NRE S=VDD IVDD_on 1 10 mA *) Not tested in production 1) I VSUPPLY is the current consumption of the pin VSUPPLY

5.1.1.1 LDO Control Block

5.1.1.1.1 Electrical Parameter of LDO

Table 5.1.1.1.1-1: Electrical Parameter Table of LDO No. Description Condition Symbol Min Typ Max Unit

1 Stabilized output voltage of LDO at pin

V BUS 1) low power mode; 5mA<=I LOAD_BUS < =350mA; 5.3V<=V SUPPLY <= 19V VBUS_LP 5.15 - 5.15 5.15 + V

2 Stabilized output voltage of LDO at pin

VBUS 1) standard power mode; 5mA<=I LOAD_BUS < =350mA; 6.95V<=V SUPPLY < =19V VBUS_STD 6.65 - 6.65 6.65 + V Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 No. Description Condition Symbol Min Typ Max Unit

3 Stabilized output voltage of LDO at pin

mode; 5mA<=I LOAD_BUS < =350mA; 8.0V<=V SUPPLY <= 19V VBUS_INC 7.7 - 7.7 7.7 + V

4 Input voltage ripple rejection ratio for low

frequencies *) 50Hz<=f<=20kH V SUPPLY_AC =4V PP ; VSUPPLY_DC >9V; CBUS =4.7µF;VBU S=6.65V-setting 5mA<=I BUS <=350 mA; VBUS_RR_LF 40 dB

5 Input voltage ripple rejection ration for high

frequencies *) 100kHz<=f<=50 0kHz; V SUPPLY_AC =400m- VPP ; 5.6V<=V SUPPLY <= 6.4V; C BUS =4.7µF;VBU S=5.15V-setting 5mA<=I LOAD_BUS < =350mA; VBUS_RR_HF 20 dB 6 ΔLine regulation ( V BUS voltage for variable VSUPPLY voltage) ILOAD_BUS is con- stant during test: 5mA<=I LOAD_BUS < =350mA; V SUPPLY varies: 5.6V<=V SUPPLY <= 19V VBUS_LIR -25 0 25 mV 7 ΔLoad regulation ( V BUS voltage for variable ILOAD_BUS current) VSUPPLY is con- stant during test: 5.6V<=V SUPPLY <= 19V;I LOAD_BUS var- ies during test: 5mA<=I LOAD_BUS < =350mA VBUS_LOR -25 0 25 mV

8 V BUS voltage overshoot *) VBUS_OS 10 %

9 V BUS voltage start-up time *) 2) tstart_LDO 2)

10 Internal charge pump for LDO LDO charge

V CP_GATE 10 19 V *) Not tested in production 1) trimmed 2) Start-Up time t start_LDO can be calculated by following formula: t start_LDO =(V TH +V GS_eff )*C K/I VG_DRV ; for V TH and V GS_eff see NMOS transistor data sheet; C K is the compensations capacitor connected between VG and AGND; I VG_DRV is the driver charge current. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

5.1.1.1.2 Electrical Parameter Control Voltage

Table 5.1.1.1.2-1: Gate Control Voltage at Pin V G No. Description Condition Symbol Min Typ Max Unit 1 NMOS gate voltage at pin V G operating V SUPPLY =5.3V V G_ON VBUS + 4.5 V

2 NMOS gate voltage at pin V G non operating RDG Ω<=500k

VSUPPLY , 250µA current sink at pin VBUS (source) V G_OFF 1 V

3 Pull down current in off condition I VG_PD 30 50 70 µA

4 Clamp voltage V G - V BUS *) VGS_CLAMP 7 13 V

5 Driver capability IVG_DRV 50 80 100 µA

*) Not tested in production

5.1.1.2 Charge Pump for Sync Voltage

Table 5.1.1.2-1: Electrical Parameter Table of the Charge Pump for SYNC Voltage No. Description Condition Symbol Min Typ Max Unit

1 Charge pump output voltage at pin CSYNC

ILOAD =0mA V CSYNC_no_ld 2*V BUS -1.35V 2*V BUS V

2 Charge pump output voltage at pin CSYNC

VBUS =5.05V; ILOAD =12.5mA VCSYNC_lp 8.65 10.1 V

3 Charge pump output voltage at pin CSYNC

VBUS =5.05V; ILOAD =14mA (7mA per SIFx) VCSYNC_lp 8.6 10.1 V

4 Charge pump output voltage at pin CSYNC

VBUS_SUP =6.45V; ILOAD =14mA (7mA per SIFx) VCSYNC_std 11.35 12.9 V

5 Charge pump output voltage at pin CSYNC

VBUS_SUP =7.47V; ILOAD =14mA (7mA per SIFx) VCSYNC_inc 13.34 14.94 V

6 Start-up time for voltage at pin CSYNC *) Test condition:

80%*V SYNC at tSTART_CP_SYNC ; without load at pin V SYNC ; tSTART_CP_CSYNC 3 ms *) Not tested in production

5.1.2 POR AND POWER-UP SEQUENCE

Table 5.1.2-1: Electrical Parameter Table of POR No. Description Condition Symbol Min Typ Max Unit

1 Power ON reset threshold value Related to V

DD VPOR_ON 2.3 2.9 V 2 Power OFF reset threshold value Related to V DD VPOR_OFF 2.2 2.7 V 3 Power ON reset hysteresis *) VPOR_HYS 0.1 0.3 V

4 Minimum time NRES=low *) tNRES_LOW 1 10 μs

5 Power ON reset delay time *) 1) At power-up of

V DD_INT tPOR_D_LH 50 μs Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 No. Description Condition Symbol Min Typ Max Unit 6 Power OFF reset delay time *) tPOR_D_HL 0.5 μs 7 Input threshold NRES low *) VNRES_low 0.8 V

8 Input threshold NRES high *) VNRES_high 2 V

9 Pull down resistor NRES RNRES_PULL_DOWN 70 100 130 Ωk

*) Not tested in production 1) The output voltage of the internal VDD-regulator

5.1.3 PSI5 INTERFACE

5.1.3.1 Interface Driver

Table 5.1.3.1-1: Electrical Parameter Table of the Interface Driver No. Description Condition Symbol Min Typ Max Unit

1 Voltage at pin SIFx (x=1-2),

mode; Test condition for V SIFX_min measurement: V BUS =5.05V; ISIFX_OP =65mA and V BUS is supplied directly VSIFx_lp_VBUS_min 4.543 V BUS V

2 Voltage at pin SIFx (x=1-2), low power

mode *) Low voltage mode; V BUS =4.6V..5.05 Test condition for V SIFX_min meas- urement: V BUS =4.6V; ISIFX_OP =25mA and V BUS is supplied directly VSIFx_lp 4.405 5.05 V

3 Voltage at pin SIFx (x=1-2), common

mode *) Standard mode; Condition for V SIFX_min meas- urement: V BUS =6.45V; ISIFX_OP =65mA and V BUS is supplied directly VSIFx_std 5.943 V BUS V Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 No. Description Condition Symbol Min Typ Max Unit

4 Voltage at pin SIFx (x=1-2), common

mode *) Increased mode; Condition for V SIFX_min meas- urement: V BUS =7.47V; ISIFX_OP =65mA and V BUS is supplied directly VSIFx_inc 6.963 V BUS V

5 Resistance between pin V BUS and pins SIFx I SIFX_OP =65mA,

R VBUS_SIFx 4.5 7.8 Ω *) Not tested in production

5.1.3.2 Over Current Detection and Limitation

Table 5.1.3.2-1: Electrical Parameter Table of the Over Current Detection and Limitation No. Description Condition Symbol Min Typ Max Unit

1 Sensor interface current limitation I

LIM_SIFx -130 -100 -75 mA

2 Threshold value for detection of SCG"hard

short" *) 1) ISIFx_HaSh 200 mA

3 Activation time for over current limitation at pin

SIFx at "hard short" *) t SIFx_ HaSh_act 300 ns

4 Over current switch off delay *) t SIFx_ LIM_act 491 544 566 μs

5 SIFx over current start up delay (default

value:ASIC_CNFG_3:BL_CHANNEL_1- 4=0000) tOC_SIFx_5ms 5.007 5.248 5.458 ms

6 SIFx over current start up

delay(ASIC_CNFG_3:BL_CHANNEL_1- 4=1111) tOC_SIFx_10ms 10.014 10.464 10.882 ms *) Not tested in production 1) SCG:Short to GND

5.1.3.3 Reverse Current Detection and Limitation

5.1.3.3.1 Reverse Current Flow from SIFx to VBUS

Table 5.1.3.3.1-1: Electrical Parameter Table of the Reverse Current Detection and Limitation (Reverse Current Flow from SIFx to VBUS) No. Description Condition Symbol Min Typ Max Unit

1 Reverse current into SIFx-pin in ON-state equal to

ΔVREV_TRIG / RVBUS_SIFx ISIFx_REV_ON 200 mA

2 Reverse current into SIFx-pin in OFF-state *) ISIFx_REV_OFF 1 mA

3 Threshold value for detection of the reverse curre nt 1) ISIFx_REV_THR 10 30 60 mA

4 Activation time for reverse protection at pins SIF x *) tSIFx_REV_act 500 ns

5 SIFx reverse current shut-off activation time

(deglitcher) *) tSIFx_REV_CUR 61 96 100 μs *) Not tested in production 1) ΔVREV_TRIG =V BUS -V SIFx in short to V BAT condition Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

5.1.3.3.2 Reverse Current Flow from SIFx to CSYNC

Table 5.1.3.3.2-1: Electrical Parameter Table of the Reverse Current Detection and Limitation (Reverse Current Flow from SIFx to CSYNC) No. Description Condition Symbol Min Typ Max Unit

1 Threshold value for detection of the

I CSYNC_REV_THR -100 -4 mA

5.1.3.4 Data Comparator

Table 5.1.3.4-1: Electrical Parameter Table of the Data Comparator No. Description Condition Symbol Min Typ Max Unit

1 Data comparator threshold

low->high transition Low power mode I COMP_th_lp_lh -8.3 -6.3 -4.3 mA

2 Data comparator threshold

high->low transition Low power mode I COMP_th_lp_hl -7.7 -5.7 -3.7 mA

3 Data comparator threshold

low->high transition Common mode I COMP_th_com_lh -16.6 -12.6 -8.6 mA

4 Data comparator threshold

high->low transition Common mode I COMP_th_com_hl -15.4 -11.4 -7.4 mA 5 Data comparator hysteresis *) Low power mode I COMP_hys_lp 0.6 mA 6 Data comparator hysteresis *) Common mode I COMP_hys_com 1.2 mA

7 Data comparator filter time (deglitcher) *) Manchester

125kbps; 2bit deglitcher; resol- ution 250ns; I DATA_DGL_lf 480 750 ns

8 Data comparator filter time (deglitcher) *) Manchester

189kbps; 2bit deglitcher; resol- ution 167ns; I DATA_DGL_hf 320 500 ns *) Not tested in production

5.1.3.5 Sync Pulse Generation

5.1.3.5.1 Sync Pulse Generation DC-Parameter

Table 5.1.3.5.1-1: Sync Pulse Generation DC-Parameter No. Description Condition Symbol Min Typ Max Unit

1 Sync slope reference voltage

*) Referenced to V SIFx ; t2 defined by V t2 Vt0 0.5 V

2 Lower boundary of sync signal sustain

voltage *) Low power mode; Referenced to V SIFx ; t2 defined by V t2 Vt2_lp 2.5 V

3 Lower boundary of sync signal sustain

voltage *) Common mode; Referenced to V SIFx ; Vt2_com 3.5 V

4 Upper boundary of sync signal sustain

Low power mode V t3_lp 2.7+V S IFX 3.7+V S IFX 4.3+V S IFX V Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 No. Description Condition Symbol Min Typ Max Unit

5 Upper boundary of sync signal sustain

Common mode V t3_com 4.2+V S IFX 4.8+V S IFX 5.5+V S IFX V

6 Ripple of voltage V t3

(supply rejection between pins CSYNC and SIFx) Test condition: t=close to end of short sync signal μ=>t=t0+15 s; Vt3_rippple 100 mV PP 7 Current limitation during Sync pulse slope *) ICSYNC_LMT -210.0 -150.0 -110.0 mA

8 CSYNC voltage drop between pin CSYNC

VCSYNC_DR 0.8 V *) Not tested in production

5.1.3.5.2 Sync Pulse Generation AC Parameter

Table 5.1.3.5.2-1: Sync Pulse Generation AC-Parameter No. Description Condition Symbol Min Typ Max Unit

1 Sync slope rising slew rate Transition from

V t0 to V t2 ; 24nF<=C BUS <=10 7nF; 4mA<=I SIFx <=35 mA SR rise 0.43 1.5 V/µs

2 Sync slope falling slew rate Transition from

Vt2 to V t0 ; 24nF<=C BUS <=10 7nF; 4mA<=I SIFx <=35 mA SR fall -1.5 V/µs

3 Reference time for Sync slope *) 1) Reference time

V t0 0 µs

4 Sync signal earlist start *) 1) t1 -1 µs

5 Sync signal sustain time *) 1) Short sync pulse t 03 16 µs

6 Sync signal sustain time *) 1) Long sync pulse t 1

3 43 µs

7 Discharge time limit *) 1) Short sync pulse t 04 35 µs

8 Discharge time limit *) 1) Long sync pulse t 1

4 62 µs

9 Minimum idle time of Tx_LEN counter *) tTx_LEN_IDLE 32 µs

*) Not tested in production 1) see timing diagram Figure 6.1.3.6-1

5.1.3.6 Sync Pulse Generation by Pin TRIG

Table 5.1.3.6-1: Trigger via Pin TRIG No. Description Condition Symbol Min Typ Max Unit

1 Schmitt-Trigger - low input level at pin

V SMT_L 0.8 V

2 Schmitt-Trigger - high input level at pin

VSMT_H 2 V

3 Trigger pulse at pin TRIG - short SYNC

pulse *) 70% of rising slope to 30% of falling slope t trig_sh_pulse 10 15 20 μs Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 No. Description Condition Symbol Min Typ Max Unit

4 Trigger pulse at pin TRIG - long SYNC

pulse *) 70% of rising slope to 30% of falling slope t trig_lng_pulse 40 45 50 μs

5 Trigger pulse rise and fall *) Transition from

20% to 80% (and vice versa); t trig_RI/RA 50 ns

6 Trigger pulse filter time *) 3bit deglitcher;

resolution 1µs t DGL_trig 4.72 5 5.2 μs

7 Delay counter to distinguish between

short/long SYNC pulse *) tDLY 30 μs

8 SYNC pulse delay timer *) step size = 2µs;

t SYNC_DLY 0 8/f CLK_I NT *(2 10 - μs

9 SYNC pulse delay from counter *) tSYNC_DLY_CNT 32/f CLK_

μs

10 Time between two sync pulses on different

SIFx channels *) tSYNC_REP1 0 μs

11 Sync pulses repetition time on the SIFx

channel *) limited if charge pump is used; Applies for I SIFx_Q =4...-19mA (standard cur- rent) t SYNC_REP2_std 200 μs

12 Sync pulses repetition time on the SIFx

channel *) limited if charge pump is used; Applies for I SIFx_Q =4...-35mA (extended cur- rent) t SYNC_REP2_ext 300 μs

13 Pull down resistor TRIG, applies for voltage

VTRIG<3.3V RTRIG_PULL_DOWN 70 100 150 Ωk

14 Pull down current pin TRIG, applies for

voltage VTRIG>3.3V ITRIG_PULL_DOWN 10 60 μA *) Not tested in production

5.1.4 CLOCK GENERATION

Table 5.1.4-1: Electrical Parameter Table of the Internal Oscillator No. Description Condition Symbol Min Typ Max Unit

1 Internal oscillator clock frequency

1) fCLK_INT 11.52 12.00 12.48 MHz

2 Duty cycle of f CLK_INT

*) DC CLK_INT 40 60 % *) Not tested in production 1) trimmed Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

5.1.5 DIAGNOSIS

5.1.5.1 ADC Voltage Measurements

Table 5.1.5.1-1: Electrical Parameter Table of the ADC. No. Description Condition Symbol Min Typ Max Unit

1 Positive reference voltage V

REFH 2.6 2.7 2.75 V

2 Offset measurement of V BUS diagnosis

VBUS =4.6V .. 11V V BUS_Offset -450 250 mV

3 Gain measurement of V BUS diagnosis

4 Offset measurement of V CSYNC diagnosis

VCSYNC =8V .. 33V V CSYNC_Offset -1.8 1.4 V

5 Gain measurement of V CSYNC diagnosis

VCSYNC =8V .. 33V V CSYNC_Gain 0.85 1 1.15 V CSYNC

6 Offset measurement of VDD diagnosis

VDD=3.0V .. 5.5V VDD Offset -400 200 mV

7 Gain measurement of VDD diagnosis

VDD=3.0V .. 5.5V VDD Gain 0.93 1 1.07 VDD

8 Offset measurement of V SIFX diagnosis

VBUS = 4.6V .. 11V VSIFX_Offset -450 250 mV

9 Gain measurement of V SIFX diagnosis

VBUS = 4.6V .. 11V VSIFX_Gain 0.94 1 1.06 V BUS

10 Measurement of V CP_LDO diagnosis voltage

VSUPPPLY =5.3V,V B US =7V VCP_LDO 10.2 12.2 14.2 V

11 Measurement of V CP_LDO diagnosis voltage

VSUPPPLY =6.95V,V BUS =7V VCP_LDO 12.2 14.2 16.2 V

12 Measurement of V CP_LDO diagnosis voltage

VSUPPPLY =8V,V BUS =7V VCP_LDO 13.2 15.2 17.2 V

13 Measurement of V DD_INT diagnosis voltage

VDD=3.3V V DD_INT 3.0 3.2 3.4 V

14 Measurement of V DD_INT diagnosis voltage

VDD=5V V DD_INT 3.0 3.2 3.4 V

5.1.5.2 Over Temperature Monitoring (OT)

Table 5.1.5.2-1: Electrical Parameter Table of the Over temperature Sensing: No. Description Condition Symbol Min Typ Max Unit

1 Junction temperature threshold value; low-

high transition TJ_HI 154 165 174 ° C

2 Junction temperature threshold value; high-

low transition *) TJ_LI 145 155 165 ° C

3 Junction temperature hysteresis *) TJ_HYS 10 ° C

4 Over temperature filter time (deglitcher) *) tOT 8.1 ms *) Not tested in production Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

5.1.5.3 VBUS Over Voltage Monitoring

Table 5.1.5.3-1: VBUS over voltage monitoring No. Description Condition Symbol Min Typ Max Unit

1 V BUS over voltage comparator - threshold

VBUS_OV_THR 11.8 13 V 2 V BUS over voltage comparator - hysteresis *) VBUS_OV_HYS 0.5 V

3 V BUS over voltage filter time (deglitcher) *) tVBUS_OV 61 96 100 μs

*) Not tested in production

5.2 DIGITAL PART

5.2.1 SPI

5.2.1.1 DC Electrical Parameter Table of SPI IOs

Table 5.2.1.1-1: DC Electrical Parameter Table of the Digital Inputs and Outputs No. Description Condition Symbol Min Typ Max Unit

1 Input threshold low SDI_RXD, NCS,SCLK V

THDIG_L 0.8 V

2 Input threshold high SDI_RXD, NCS,SCLK V THDIG_H 2 V

3 Output voltage SDO_TXD low I SDO_TXD_L=3.2mA V SDO_TXD_L 0.4 V

4 Output voltage SDO_TXD high I SDO_TXD_H=-2mA V SDO_TXD_H VDD -

0.4V VDD V

5 Pull Up resistor NCS RNCS_PULL_UP 70 100 130 Ωk

6 Pull Up resistor RXD RSDO_RXD_PULL_UP 70 100 130 Ωk

5.2.1.2 AC Electrical Parameter Table of SPI I/Os

Table 5.2.1.2-1: Electrical Parameter Table of SPI No. Description Condition Symbol Min Typ Max Unit

1 SPI frequency

*) fSCLK 0 5 MHz 2 SDO_TXD rise and fall time *) 20pF...150pF load t sdo_trans 5 35 ns

3 Minimum time CLK=LOW *) tclh 75 ns

4 Minimum time CLK=HIGH *) tcll 75 ns

5 Propagation delay (SCLK to data at SDO

active) *) 150pF load; from SCLK=2.3V to SDO=0.5*V DD_SUP , applies for 3.3V/5V; t pcld 50 ns

6 NCS low to output SDO active *) 150pF load t csdv 75 ns

7 SCLK low before NCS low (setup time

SCLK to NCS change H/L) *) tsclch 75 ns

8 SCLK change L/H after NCS=low *) thclcl_app 600 ns

9 SDI input setup time (SCLK change H/L

after SDI data valid) *) tscld 15 ns

10 SDI input hold time (SDI data holdafter

SCLK change H/L) *) thcld 15 ns

11 SCLK low before NCS high *) tsclcl 100 ns

12 SCLK high after NCS high *) thclhc 100 ns

Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 No. Description Condition Symbol Min Typ Max Unit

13 NCS L/H to SDO@high impedance *) tpchdz 75 ns

14 NCS min. high time between two consecut- ive commands *) ton_NCS 700 ns

15 NCS filter time *) tfNCS 10 40 ns

*) Not tested in production Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6 Functional Description

6.1 ANALOG PART

6.1.1 SUPPLY

Various supply voltage concepts are supported by the device due to the various possible applications. The device is supplied via the pin V SUPPLY with an appropriate voltage. This voltage supplies an external transistor that is driven by an internal LDO via the pin V G. The output of the external transistor is fed back via the pin V BUS to the LDO con- trol block. If an external NMOS transistor is used, the internal error amplifier has to be compensated with an external com- pensation capacitor C K connected between V G and AGND. For low supply voltages V BUS on the ECU, the ASIC can be supplied directly at pin VBUS with the voltage provided by V SUPPLY , when no voltage drop between the pins V SUP- PLY and V BUS can be accepted. In this case the LDO must be disabled. The voltage V CSYNC , which is necessary for providing the sync pulse is generated in the block CHARGE PUMP FOR SYNC VOLTAGE (CP). The voltage V CSYNC is available at the pin CSYNC. Alternatively, the CSYNC voltage can be supplied directly at the pin CSYNC with external voltage V CSYNC . The V CSYNC charge pump must be disabled in this case. The following table gives an overview of possible supply voltage concepts, which can be chosen via SPI or UART commands. Table 6.1.1-1: Overview Supply Voltage Concepts Config Options V DD VSUPPLY VBUS VCSYNC LDO enabled CP enabled A VDD supplied directly VSUPPLY supplied directly Generated by LDO Generated by charge pump YES YES B VDD supplied directly VSUPPLY supplied directly Generated by LDO V CSYNC supplied from ECU YES NO C VDD supplied directly N.A. V BUS supplied dir- ectly Generated by charge pump NO YES D VDD supplied directly N.A. V BUS supplied dir- ectly VCSYNC supplied from ECU NO NO

6.1.1.1 LDO Control Block

A low drop out regulator (LDO) with external NMOS and compensation capacitor C K is implemented to generate a stable V BUS voltage out of the input voltage V SUPPLY . A LDO control circuit is implemented to drive the external NMOS transistor. Three voltage levels for V BUS are configurable via bit combination ASIC_CNFG_1[V_BUS] (see descrip- tion of register ASIC_CNFG_1 for details). The LDO control circuit is disabled by default value ASIC_CNFG_1[V_BUS]="00". The voltage loop has be to compensated with an external compensation capacitor CK at pin V G for stability reasons. The LDO charge pump provides an appropriate voltage V CP_GATE for control of the external NMOS transistor at pin V G. A gate source voltage clamping to the voltage V GS_CLMP is implemented.

6.1.1.2 Charge Pump for Sync Voltage

A charge pump is used to generate the SYNC pulse voltage from the voltage VBUS. The charge pump consists of two external capacitors, the fly capacitor CP connected to pins CP1 and CP2, the storage capacitor CSYNC con- nected to pin CSYNC, two diodes and two high voltage switches inside the IC. The charge pump is configurable via bit ASIC_CNFG_3[EN_CP_SYNC] (see description of register ASIC_CNFG_3).

• EN_CP_SYNC='0' means disabled
• EN_CP_SYNC='1' means enabled The charge pump circuit is disabled for the asynchronous mode. If the charge pump is not used, then it is not allowed to connect the pin CSYNC with ground. The diode path from V BUS to C SYNC will result in high current and destruction of IC. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.1.2 POR AND POWER-UP SEQUENCE

The POR-block observes the voltages V DD_INT , V ANA , NRES, V AGND and V PGND . It generates the POR-signal. During the power up time, the following actions take place:

• The voltage regulators V DD_INT and V ANA provide the voltage V DD_INT and V ANA
• The bandgap/biasing block provides the voltage VBG and the bias
• The internal oscillator starts up and provides a stable clock frequency for the digital part After power-up time, the rising edge of the NRES determines the interface mode (SPI/UART), depending on the state of the pin NCS. When NCS is LOW the UART interface is selected. When NCS is HIGH the SPI is chosen. During the power up time is not allowed to change the logic level of NRES.

6.1.3 PSI5 INTERFACE

6.1.3.1 Interface Driver

Each of the two interfaces provide a voltage V SIFx and a current I SIFx for the connected satellite sensors by "switch- ing" voltage V BUS to the pin SIFx via internal transistor switches and shunt. The interfaces are short-circuit protected to V BAT and GND. The two interfaces operate independent from each other. The interfaces can be en-/disabled via an UART/SPI command with the bits EN_CHx , described in register ASIC_CNFG_3. The default state of the inter- face is disabled. The current sensing block includes an I BASE tracking function and the DATA-comparator. Any time a channel is enable by [EN_CHx], a blanking time is started. During this delay time t SIFx_BLANKING , the Manchester decoder, SYNC pulse generator and overcurrent filter time t OC_SIFx are disabled. No channel enable possible if following error bits are set to '1': - ERROR_STATUS_1[VBUS_OV] - ERROR_STATUS_x[REV_CUR_CHx] if REV_CUR_CH_DIS='1' - ERROR_STATUS_x[OC_CHx] - ERROR_STATUS_1[DIAG_OT]

6.1.3.2 Over Current Detection and Limitation

The circuit provides an over current limitation and protection of the interfaces. The current limitation for I SIFx is imple- mented with a voltage measurement over the shunt resistor R SH and with the control of the transistor T2. If the cur- rent I SIFx exceeds the threshold current I LMT_SIFx , the comparator output signal i sifx_oc_det is set to high. This signal is filtered in the digital block by a deglitcher with the filter time t SIFX_LIM_act , latched in the register ERROR_STATUS_x[OC_CHx] and the appropriate channel is disabled,that means the affected EN_CHx bits are reset by the device automatically. To switch on the channel again it is essential to read out the appropriate error register ("clear on read"). To ensure proper over current detection, the threshold value for overcurrent limitation is higher than the over cur- rent detection threshold. In order to avoid over current switch off during start up (enable of channels), a blanking time of t OC_SIFX_5ms resp. tOC_SIFX_10ms is implemented. During this time the over current switch off is disabled. The blanking time can be pro- grammed in the Register ASIC_CONFG_3 BL_ChannelX.

6.1.3.3 Reverse Current Detection and Limitation

The IC provides two different paths of the reverse current protection:

• from pin SIFx to pin VBUS
• from pin SIFx to pin CSYNC

6.1.3.3.1 Reverse Current Flow from SIFx to VBUS

The circuit provides the reverse current detection from SIFx pin to VBUS pin. The reverse current detection is implemented with a voltage measurement over the shunt resistor R SH (like described in the chapter Over current Detection). If a reverse current is detected the comparator output signal will be set to high. The signal will be deglitched and latched in the register ERROR_STATUS_x[REV_CUR_CHx]. The affected channel will be disabled if configuration bit ASIC_CNFG_2 [REV_CUR_CH_DIS] is set to high and the affected EN_CHx bits are reset by the device automatically. To switch on the channel again it is essential to read out the appropriate error register ("clear on read"). Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.1.3.3.2 Reverse Current Flow from SIFx to CSYNC

The circuit provides the reverse current detection from pin SIFx to pin CSYNC. The reverse current detection is implemented with a MOS-transistor. The reverse current protection circuit stops the reverse current from SIFx pin to CSYNC pin when SIFx becomes higher then CSYNC.

6.1.3.4 Quiescent Current Threshold Tracking

The quiescent current of the circuit is measured and adapted continously during during operation, to avoid corrup- ted data transmission because of drift or aging processes.

6.1.3.5 Data Comparator

The satellite sensors modulate the current in order to realize a Manchester coded data transmission. The "low" level of the current is represented by the quiescent current I SAT_Q_range of the sensor, while a "high" level is created by switching on a current sink to the line, which increases the current to I SAT_OP . A current transition in the middle of the bit time represents the logical value of the transferred data. A "high cur- rent-low current" transition stand for a logical '1', a "low current-high current" transition for a logical '0'. This current can be detected by measuring the voltage drop via an internal shunt. The current threshold is automat- ically adapted to the quiescent current of the sensors. ΔThe threshold value is configured with register ASIC_CNFG_1[ Is_CHx] with 1bit per SIFx (changed indivi dually). ∆ ∆ The default value is Is='0' (common mode). Is='1' m eans the threshold value for low power mode is choosen (see register description of ASIC_CNFG1). ISAT ISAT_OP ISAT_TH ISAT_Q_range TBit BIT1 “0” BIT2 “1” BIT3 “1” t Figure 6.1.3.5-1: Current Modulation

6.1.3.6 Sync Pulse Generation

For PSI5 synchronous mode, the IC generates the SYNC pulse to synchronize the sensors. During SYNC pulse the voltage level at pins SIFx will be increased for a defined time and then decreased before the sensor to ECU communication (current modulation) starts. The SYNC pulse is shaped to limit emissions. The SYNC voltage is either generated by SYNC pulse charge pump or supplied from external via pin CSYNC. The voltage level Vt3 is configured with the register ASIC_CNFG_1[VSYNC_V3_CHx] with 1 bit per SIFx (channel individually). Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 The IC provide a reverse protection for the short circuit to the battery at the interfaces and current limitation of the SYNC pulse. The current limitation is active during SYNC sustain time only. The current limitation is disabled during rising/falling slope to guarantee slope at max. load. There are two ways to generate an event triggered SYNC pulse:

• by trigger voltage pulse at pin TRIG
• by UART/SPI command Phase Sync Start VTRIG Vt2 Vt0 VCE Base t1 t0 t2 t03 t04 t13 t14 VCE max Phase Sync Slope Phase Sync Sustain Phase Sync Discharge Long sync pulse [1] Short sync pulse [0] Trigger Point Lower Boundary Upper Boundary Vt3 Figure 6.1.3.6-1: Sync Pulse Timing Diagram

6.1.3.7 Sync Pulse Generation by Pin TRIG

Following diagram shows the timing requirements for the trigger voltage pulse at pin TRIG with:

• high time t trig_sh_pulse for a short SYNC pulse
• high time t trig_lo_pulse for a long SYNC pulse Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 ATIC158 timer SYNC_DLY long pulse (t 3 + t1) VSIFx tSYNC_DLY ttrig_lo_pulse VTRIG (Pin TRIG) Example: long SYNC pulse 70% 30% i_trig_f tDGL_itrig SYNC_time ≥t (tDGL_itrig + 1/fCLK ) i_trig tDGL_itrig Figure 6.1.3.7-1: Long SYNC Pulse Trigger via Pin TRIG ATIC158 timer SYNC_DLY VSIFx tSYNC_DLY VTRIG (Pin TRIG) Example: short SYNC pulse i_trig_f ≥t (tDGL_itrig + 1/fCLK ) i_trig tDGL_itrig SYNC_time short pulse (t0 3 + t1) 30% tDGL_itrig ttrig_sh_pulse 70% Figure 6.1.3.7-2: Short SYNC Pulse Trigger via Pin TRIG

6.1.3.8 Sync Pulse Generation by UART/SPI Command

Following timing diagrams show the SYNC pulse generation triggered by a UART or SPI command. SYNC_DLY SYNC_time short pulse (t0 3 + t1) long pulse (t1 3 + t1) VSIFx UART Stp PD 7….D0Srt syncronizer 1/(f CLK_EXT ) + 4/(fCLK_INT ) ATIC158 timer tSYNC_DLY Figure 6.1.3.8-1: Short SYNC Ptrigger via UART Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 SPI SYNC_DLY SYNC_time short pulse (t0 3 + t1) long pulse (t1 3 + t1) VSIFx ...SYNC_PULSE SPI NCS tSYN C_DLY 3*1/(fCLK_INT ) ATIC 158 timer Figure 6.1.3.8-2: Short SYNC Pulse Trigger via SPI

6.1.4 CLOCK GENERATION

The internal oscillator is the central clock source for the digital part and provides the clock signal required for the internal charge pumps. The oscillator starts up automatically as soon as V DD_INT and V ANA are stable. An external clock has to be supplied via pin SCLK for UART communication. The ratio between external clock and UART baud rate is 5/1 ( = 5 times oversampling for UART telegrams on SDI_RXD).

6.1.5 DIAGNOSIS

6.1.5.1 ADC Voltage Measurements

Several voltage levels can be measured by the ASIC with an analog-digital converter for diagnostic purposes. The digital values will be written into status registers after conversion. These registers can be read out by the micro con- troller via UART/SPI. An 8-bit ADC (Successive Approximation Register concept) is implemented for diagnosis purposes. In total 7 internal voltages are measured sequentially in a repeating (endless) loop. The measurement of one voltage is called a cycle. Steps within a cycle:

• Voltage is selected via MUX
• ADC conversion is performed
• Data is transferred into register DIAGNOSIS_ADC_1_2 to DIAGNOSIS_ADC_9_10 One sequence is performed within t CYC . Each measured voltage is stored in a dedicated register. The update rate of the register values is given by number of voltages multiplied with cycle time -> 7 x t CYC .The ADC sequence starts with release of reset automatically. For synchronous mode the values at "pin SIFx" can vary between V SIFx and V t3 , depending whether a SYNC pulse was generated during conversion time or not. For asynchronous mode the voltage at pin SIFx is measured properly. The following table shows the voltage divider ratio of the different voltages. Table 6.1.5.1-1: Voltage Divider Ratio Voltage Divider ratio V BUS 1/5 VSYNC 1/13 VCP_GATE 1/7 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Voltage Divider ratio VSIFx 1/5 VDD_INT 1/2 VDD 1/3

6.1.5.2 Over Temperature Monitoring (OT)

The junction temperature is monitored with a temperature sensor to detect excessive temperature levels. If the junction temperature exceeds T J_HI then following protection actions will be processed automatically:

• All SIFx will be disabled -> reset bit ASIC_CNFG_3[EN_CHx]='0'
• The affected EN_CHx bits are reset by the device automatically. To switch on the channel again it is essential to read out the appropriate error register ("clear on read").
• SYNC pulse charge pump will be disabled -> reset bit ASIC_CNFG_3[EN_CP_SYNC]='0'
• over temperature event is latched in status register ERROR_STATUS_1[DIAG_OT] after t OT (clear on read)
• With read of ERROR_STATUS_1[DIAG_OT], the filter timer for t OT is reseted (deglitcher reset), independently of the current error status.
• If the read cycle of ERROR_STATUS_1[DIAG_OT] is shorter than t OT , the ERROR_STATUS_1[DIAG_OT] bit will never be set.
• The channel will not be enabled automatically, if the error condition disappears.

6.1.5.3 VBUS Over Voltage Monitoring

A comparator for V BUS over voltage monitoring is implemented to avoid any damage of PSI5 sensors by exceeding their input voltage range. If VBUS exceeds the value of V BUS_OV_THR then following protection actions are processed automatically:

• All SIFx will be disabled -> reset bit ASIC_CNFG_3[EN_CHx]='0'
• The affected EN_CHx bits are reset by the device automatically. To switch on the channel again it is essential to read out the appropriate error register ("clear on read").
• SYNC pulse charge pump will be disabled -> reset bit ASIC_CNFG_3[EN_CP_SYNC]='0'
• The over voltage event is latched in status register ERROR_STATUS_1[VBUS_OV] after t VBUS_OV (clear on read)
• With read of ERROR_STATUS_1[VBUS_OV], the filter timer for t VBUS_OV is reseted (deglitcher reset), independ- ently of the current error status.
• If the read cycle of ERROR_STATUS_1[VBUS_OV] is shorter than t VBUS_OV , the ERROR_STATUS_1[VBUS_OV] bit will never be set.
• The channel will not be enabled automatically, if the error condition disappears.

6.1.5.4 Leakage to GND, Leakage to V BAT and Open Load

The detection of leakage To GND, leakage to VBAT and open load are implemented in the digital logic, based on the Ibase tracking function. The digital counter for I BASE indicates a leakage to GND for high counter values (high quiescent current) and the actual state is latched in status register ERROR_STATUS_x[DIAG_CHx]. For low counter values either a leakage to V BAT or an open load condition is indicated (low or no quiescent curret). The actual state is latched in status register ERROR_STATUS_x[DIAG_CHx]. The differentiation of leakage to V BAT / open load failure has to be done by the micro controller via the status of reverse current protection ERROR_STATUS_x[REV_CUR_CHx]

• Reverse current protection not active [REV_CUR_CHx]='0' -> Open Load
• Reverse current protection active [REV_CUR_CHx]='1' -> Leakage to VBAT or via ADC voltage measurement at pins SIFx (if flag [REV_CUR_CHx]='0'),
• VSIFx = V BUS -> Open Load
• VSIFx > V BUS -> Leakage to VBAT Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.1.5.5 GND Loss Detection

A comparator for GND loss detection is implemented to detect missing GND connections. A detected GND loss results in a reset of the IC. Following GNDs will be monitored:

• AGND
• PGND

6.1.5.6 Transfer of Error- and Diagnosis Information to µController

6.1.5.6.1 Error Information

All error analog/digital information are flagged in status registers ERROR_STATUS_1 ... ERROR_STATUS _6. Every error is latched and is cleared by a read request by SPI or UART. An overall error information is transmitted to the micro controller, included in some frames (see below) within bits Err[1:0]. For detailed error information the dedicated status registers shall be read.

• UART: Bits Err[1:0] included in header (UART frame1)
• SPI: Bits Err[1:0] included in the first response frame (SPI frame2) The error information, bits Err[1:0], are transmitted in following messages to the micro controller:
• UART
• Response to Read Command
• Transfer PSI5 Data
• SPI
• Responses to commands "cmd_get data_xxbit" μThese responses allows the Controller to know which kind of an error occurred. (All interface errors, shown in the table below, are flagged in registers ERROR_STATUS_3 to ERROR_STATUS_6. Register ERROR_STATUS_2 includes an OR-combination of all interface errors, one bit per channel. E.g. ERROR_STATUS_2[0] includes the OR-combination of bits in registers ERROR_STATUS_3 and ERROR_STATUS_4 (=error information of channel 1).) For detailed information see register table. Note : It is recommended to read out register ERROR_STATUS_2 if bit Err[0] (interface error) is set in a response of the transceiver to determine which channels are affected. In register ERROR_STATUS_2 the two LSBs [1:0] belongs to channel 2 & channel 1 and the appropriate channel bit is set in case of an interface error on the affected chan- nel. Afterwards the micro controller shall read the dedicated registers ERROR_STATUS_3 .. ERROR_STATUS_6 (depend of the affected channels) to get the detailed error information. There are two detailed error registers avail- able per channel. If bit Err[1] (asic error) is set in a message to the micro controller register ERROR_STATUS_1 shall be read for more information. It is not recommended to read out the appropriate ERROR_STATUS_X with a cycle time of less than 9ms. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.1.5.6.1-1: Overview of Possible Error Information TYPE OF ERROR ASIC INTERFACE CH1-CH4 FRAME 1-6 ERROR STATUS REGISTER ERROR BIT FLAG UART parity error. ASIC x ERROR_STATUS_1[0] Err[1] UART framing error (invalid stop bit). ASIC x ERROR_STATUS_1[1] Err[1] UART/SPI invalid com- mand received. ASIC x ERROR_STATUS_1[2] Err[1] UART/SPI collision. ASIC x ERROR_STATUS_1[3] Err[1] SPI clock error. ASIC x ERROR_STATUS_1[4] Err[1] over temperature shut down. ASIC x ERROR_STATUS_1[5] Err[1] V BUS overvoltage. ASIC x ERROR_STATUS_1[6] Err[1] MCD CRC/Parity Error. Interface x x Ch1: ERROR_STATUS_3[0]/[4]/[8]/[12], ERROR_STATUS_4[0]/[4] Ch2: ERROR_STATUS_5[0]/[4]/[8]/[12], ERROR_STATUS_6[0]/[4] Ch1: ERROR_ STATUS_2[0] Ch2: ERROR_ STATUS_2[1] MD framing error (frame too long(short, MC code violation, compensation window violation). Inter- face x x Ch1: ERROR_STATUS_3[1]/[5]/[9]/[13], ERROR_STATUS_4[1]/[5] Ch2: ERROR_STATUS_5[1]/[5]/[9]/[13], ERROR_STATUS_6[1]/[5] Ch1: ERROR_ STATUS_2[0] Ch2: ERROR_ STATUS_2[1] MD no frame received. Interface x x Ch1: ERROR_STATUS_3[2]/[6]/[10]/[14], ERROR_STATUS_4[2]/[6] Ch2: ERROR_STATUS_5[2]/[6]/[10]/[14], ERROR_STATUS_6[2]/[6] Ch1: ERROR_ STATUS_2[0] Ch2: ERROR_ STATUS_2[1] MD unexpected frame. Interface x x Ch1: ERROR_STATUS_3[3]/[7]/[11]/[15], ERROR_STATUS_4[3]/[7] Ch2: ERROR_STATUS_5[3]/[7]/[11]/[15], ERROR_STATUS_6[3]/[7] Ch1: ERROR_ STATUS_2[0] Ch2: ERROR_ STATUS_2[1] Diagnosis: leakage to GND / VBAT. Interface x Ch1: ERROR_STATUS_4[9:8] Ch2: ERROR_STATUS_6[9:8] Ch1: ERROR_ STATUS_2[0] Ch2: ERROR_ STATUS_2[1] overcurrent. Interface x Ch1: ERROR_STATUS_4[10] Ch2: ERROR_STATUS_6[10] Ch1: ERROR_ STATUS_2[0] Ch2: ERROR_ STATUS_2[1] Data buffer configuration error (width=96bit). Interface x Ch1: ERROR_STATUS_4[11] Ch2: ERROR_STATUS_6[11] Ch1: ERROR_ STATUS_2[0] Ch2: ERROR_ STATUS_2[1] Reverse current. Inter- face x Ch1: ERROR_STATUS_4[12] Ch2: ERROR_STATUS_6[12] Ch1: ERROR_ STATUS_2[0] Ch2: ERROR_ STATUS_2[1] Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.2 DIGITAL PART

6.2.1 COMMUNICATION INTERFACE TO MICRO CONTROLLER

As interface to the micro controller, either an UART or SPI interface can be selected. The pins for both interfaces are shared. μThe interface is configurable from C

• with rising edge of NRES the UART / SPI interface is latched
• depending on state of pin NCS either UART or SPI is selected
• NCS = low means UART
• NCS = high means SPI Following pins are used for UART communication:
• SDI_RXD
• SDO_TXD
• SCLK Following pins are used for SPI communication:
• SDI_RXD
• SDO_TXD
• SCLK
• NCS

6.2.2 MANCHESTER DECODER

The manchester decoder is compliant to PSI5 1.3 and 2.1. The following interface diagnosis features are suppor- ted:

• wrong data rate
• wrong start bit combination
• wrong number of data bits
• CRC or parity failure
• wrong interframe time
• no or unexpected frame

6.2.2.1 Manchester Data Handling and Buffer Architecture

For each channel are a MCD_data_buffer with a width of 36bits and a data_buffer with a width of 96bits implemented.

• Data_buffer (96bit) is used in different configurations for UART / SPI mode (see figure below).
• Data_buffer and MCD_data_buffer will be set to default bit value = '1' if the channel is disabled.
• Disabled either by writing bits ASIC_CNFG_3[EN_CHx] via UART/SPI Write_Register command or
• by automatically switch-off in an error condition (e.g. over current error). Channel4 Channel3 Channel2 Channel1 MCD (ma nch e ste r de co de r ) PS I5 Data Fra me (fro m se nso r) width = 36bit wid th = 9 6b it MCD_ data_buffer data_buffer p a ra llel u ploa d ( e n d o f valid fra me ) b it up lo a d (with e nd o f de co de d bit ) Figure 6.2.2.1-1: Buffer Architecture Overview Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.2.2.1.1 UART DATA BUFFER

UART buffer behavior:

• One frame will be stored
• Data will be filled up starting at bit0 (LSB) of buffer
• Empty bits will be filled up with default bit value = '1' ('1' not used as frame ID) μ'''With an appropriate UART baud rate, the IC transmits the data to the Controller without any overwri ting.''' PSI5 Data Frame (from sensor) S1 S2 D0 ... Dn CRC/PAR MCD shall... -remove start bits - add frame identifier Fid [0:2] - add error bits Err [0:1] default = ’1' 95 data 0 data_buffer – UART configuration parallel upload with valid stop condition of MCD (end of valid frame ) Manchester decoder MCD_data_buffer LSB MSB Figure 6.2.2.1.1-1: UART Data Buffer

6.2.2.1.2 SPI DATA BUFFER

SPI data buffer behavior:

• MCD_data_buffer has a length of 36bit; only the configured nb of bits (according 'TSx_FLEN') + Err[0:1] + Fid[0:2] are uploaded into SPI_data_buffer; the remaining bits of MCD_data_buffer are filled up (stuffed) with '1'. A special case occurs for SPI_BUFFER_CONFIG=0b00 (48bit): after upload of MCD_data_buffer, bits [0:35] includes data + stuffing '1', whereas bits [36:47] are stuffed with '0' (described as don't care bits in figure Figure MCD_data_buffer length.
• The data_buffer has to be configured during IC start up, by bits CHx_CFG7[SPI_BUFFER_CONFIG]. The buffer is divided in blocks with equal number of bits.
• Data will be filled up starting at LSB of every individual block
• Empty bits will be filled up with default bit value = '1'.
• Unused buffer identifiers (BID[x]) are filled up with value = '1' (per default). A read request will result in
• μFrame identifier - Fid[2:0] ='111'-> C can detect t hat no data were written into this block (wrong BID[x] was read).
• μError Bits - Err[1:0] = '11' -> C has to discard (d efault values instead of error information)
• It's mandatory to read block wise via commands SPI_Get_Data_xxb according the appropriate buffer configuration. This means for SPI_BUFFER_CONFIG="11" the command SPI_Get_Data_16b is mandat- ory.
• After reading, all bits per block will be filled up with default bit value = '1'
• During transfer from MCD_data_buffer to data_buffer, an error is flagged in ERROR_STATUS_4/6[11] = BUFF_ERR_CHx if number of bits(MCD_data_buffer) > number of bits per BID. In this case no data is trans- ferred.
• The data_buffer is completely erased (filled up with default value ='1') if a channel is disabled, e.g. by ASIC_CNFG_3[EN_CHx]='0', VBUS overvoltage, overtemperature or overcurrent shut down. The number of PSI5 data bits (payload) per buffer identifier (BID) is shown in the table below for all configurations. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Figure 6.2.2.1.2-1: SPI Data Buffer If number of frames higher than number of configured buffers (Fid > BID):

• A buffer has to be used for several frames
• μController has to ensure to read buffer data before new data is loaded, otherwise it's overwritten. Following example shows buffer configuration CHx_CFG7[SPI_BUFFER_CONFIG]=0b01 with 4 identical PSI5 frames: Example: 4 frames, including (Fid[0:2] + Err[0:1] + D[0:19] + CRC); ∑ = 28bit CHx_CFG7 [SPI_BUFFER_CONFIG] frame1 frame2 frame3 frame4 BID[1] 32 63 BID[2] 64 95 BID[0] 0 31 0b01 stuffing 0 27 stuffing stuffing 32 59 64 91 Table 6.2.2.1.2-1: SPI Buffer Configuration CHx_CFG7 [SPI_BUFFER_CONFIG] Σ per BID [bit] FiD + Err [bit] max payload = PSI5 data w/o start bits [bit] 0b00 48 * 5 43 0b01 32 * 5 27 0b10 24 * 5 19 0b11 16 * 5 11 *: Please note the appropriate SPI_Get_Data_xxb-comman d selected by the number of bits in this column.

6.2.2.2 Manchester Bit Encoding

6.2.2.2.1 Definition of data edge / compensation edge

According PSI5 standard, a current transition in the middle of the bit time represents the logical value of the trans- ferred data (Manchester code) with "high current -> low current" transition for a logical ' 1' , "low current -> high current" transition for a logical ' 0' . Within this specification, this transition is called data edge ; transitions at start / end of the bits are called compens- ation edge . Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.2.2.2.2 Interpretation with Manchester Decoder

The implemented Manchester Decoder (MCD) state machine converts PSI5 data (transmitted by sensors in Manchester code) into NRZ code. The input signal is filtered by the analog datacomparator. The user is able to configure the time slot in which a data edge / compensation edge is accepted via register ASIC_CNFG_1[MCD_DATA_CMP_WINDOWS]. In principle, the default configuration is recommended with MCD_DATA_CMP_WINDOWS=0b00. For certain pattern of electro-magnetic disturbers (from environment) the configuration of MCD_DATA_CMP_WIN- DOWS=0b01 could improve immunity by decreasing the data edge window, but reduces the range of MCD duty cycle.

6.2.2.2.3 Definition of Duty Cycle

D0 = '0' D1='1' 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 50 16 16 16 16 35 11,2 21 11 11 65 20,8 11 21 21 PSI5 frame @ 125kBit/s Clock 4MHz Duty cycle [%] Thigh [nb of samples of 32] Figure 6.2.2.2.3-1: Example MCD Duty Cycle

6.2.2.2.4 Decoder Error Flags

The following chapter gives some details about the setting of flags MD_PERR_CHx_Fx, MD_FERR_CHx_Fx, frame error 111 000 slot counter 001 PSI5 data MCD: valid start bit MD_FERR_CHx_Fx MD_NO_FR_CHx_Fx latched Figure 6.2.2.2.4-1: MD_FERR_CHx_F1 Note that for a special failure condition two error flags for one frame can be set. Failure condition: e.g. default IC configuration; PSI5 sensor with 189kbps connected (instead of 125kbps); depending on PSI5 data, either 1 or 2 error bits are flagged. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 frame error 111 000 slot counter 001 PSI5 data MCD: valid start bit MD_FERR_CHx_Fx MD_NO_FR_CHx_Fx latched no start bits detected in slot ‚ 000 'latched Figure 6.2.2.2.4-2: Set Of Error Flags (2errors; data=0x3FF)

6.2.3 SPI

The SPI communication between one master and multiple slaves can be operated in parallel or in daisy chain. Parallel Operation Several SPI-slaves can be connected to one SPI channel. The communication lines SDI_RXD, SDO_TXD and CLK are shared and every slave has its own chip select line (NCS). Daisy Chain Operation µ µ Several slaves can be connected to the C in daisy c hain operation to save C interface pins (one common chip select line for all slaves in the chain). thclch tsclcl tcll tclh tsclch thclcl_an NCS SCLK SDO_ TXD SDI_ RXD tpcld tscld thcld tpchdz MSB LSB LSB MSB SPI-ECU12-V3.0.vsd Data Flow tSPI _switch tSPI _switch tSPI_ switch thclcl_app tcsdv tON_NCS tSDO_trans Figure 6.2.3-1: Data Flow Graphic pins are ignored, and SDO_TXD remains in a high impedance state. After an NCS High to Low transition, the SPI response word is multiplexed from the latches that were specified by the last command into the shift register, i.e. the SDO_TXD changes from high impedance state to the state of the MSB of the last addressed SPI register, inde- pendent of the SPI clock state. The SCLK pin must be low when NCS switches to low. At each rising edge of the clock pulse after NCS goes low, the response word is serially shifted out on the SDO_TXD pin. At each falling edge of the clock pulse (after NCS goes low) the new control word is serially shifted in on the SDI_RXD pin. The SPI command bits are decoded to determine the destination address for the data bits. After the 16th (or multiple of 16, for daisy chains) clock cycle, at the next NCS low to high transition, the SPI shift register data bits are transferred into the latch whose address was decoded from the SPI shift register command bits. A command is executed after 16 SCLK (or a multiple of 16) and NCS goes high. During reset, SDO_TXD is forced into a high impedance state and any inputs from SCLK and SDI_RXD are ignored. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 SPI Format Each device is controlled with a 16 bit control command, see following chapters. The command is stored in a command register after the rising edge of NCS. The response consists of a 16 bit word which contains the before requested information like e.g. diagnostic or output state. Response after Reset or Communication Error In case of reset or communication error (not valid commands, number of clocks not multiples of 16) following response will be sent in the next valid SPI frame: "0x0000". The execution of not valid commands is blocked and command with NCS low without clock are ignored. Order of MSB/LSB Bit MSB is sent first. CRC μSPI Packet Frames from transceiver to Controller in clude a XCRC (see 6.2.5). Daisy Chain Daisy chain operation is supported.

6.2.3.1 Error Handling

Figure 6.2.3.1-1: SPI Error Handling Example 1 1: Examples invalid command for 'Read Sensor Data 16bit': Figure 6.2.3.1-2: SPI Error Handling Example 2 4a: Example: Command 'SPI_Read_Register' including invalid address A[5:0]: Figure 6.2.3.1-3: SPI Error Handling Example 3 4b: Example: Command 'SPI_Read_Register' including Stuff 0 (frame n): Figure 6.2.3.1-4: SPI Error Handling Example 4 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 4c: Example: Command 'SPI_Read_Register' including Stuff 0 (frame n+1): Table 6.2.3.1-1: SPI Communication Error 1 invalid commands ERROR_STATUS_1 [UART_SPI_INV_CMD] command rejected 2 number of clocks NOT multiples of 16 ERROR_STATUS_1 [SPI_CLK_ERR] command rejected 3a command 'SPI_Write_Register' including invalid address A[5:0] ERROR_STATUS_1 [UART_SPI_INV_ADDRESS] & [UART_SPI_INV_CMD] command rejected 3b command 'SPI_Write_Register' including stuff 0 (in frame n+1) No flag frame n+1: correct response frame n+2: wrong XCRC (6bit stuff is used for calculation) 4a command 'SPI_Read_Register' including invalid address A[5:0] see #3a command rejected 4b command 'SPI_Read_Register' including stuff 0 (in frame n) see #1 command rejected 4c command 'SPI_Read_Register' including stuff 0 (in frame n+1) no flag frame n+1: correct response frame n+2: send zero response including inverted XCRC to uC 5a commands 'SPI_Get_Data_xxb' - NOT according buffer config- uration e.g. SPI_BUFFER_CONFIG="00" and "SPI_Get_Data_16/24/32b" ERROR_STATUS_1 [UART_SPI_INV_ADDRESS] command rejected 5b commands 'SPI_Get_Data_xxb' - according buffer configuration - including invalid ChID[2:0] Invalid channel identifier '111' see #5a command rejected 5c commands 'SPI_Get_Data_ xxb' - according buffer configur- ation - including invalid BID[2:0] Invalid buffer identifier BID[2:0] depends on configuration: e.g. SPI_BUFFER_CONFIG=0b00 '110' / '111' see #5a command rejected 5d commands 'SPI_Get_Data_ xxb' - including stuff 0 (in frame n) see #1 command rejected Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 6 command 'SPI_SYNC_PULSE' - including stuff 0 (in frame n) see #1 command rejected 8 command 'SPI_NOP' - including stuff 0 (in frame n) see #1 command rejected 9 command 'SPI_SW_RESET' - including stuff 0 (in frame n) see #1 command rejected

6.2.3.2 Overview of Communication Frames

Table 6.2.3.2-1: Overview of SPI Communication Frames Communication Path Commands/Response s SPI Frame n [SPI Packet Frame] SPI Frame n+1 [SPI Packet Frame] SPI Frame n+2 [SPI Packet Frame] SPI Frame n+3 [SPI Packet Frame] SPI Frame n+4 [SPI Packet Frame] μC->transceiver SPI_NOP cmd[3:0]; Stuff [11:0] next cmd μC->transceiver Response response to previous cmd cmd[3 :0]; Stuff [11:0] μC->transceiver SPI_Write_Register cmd[3:0]; A[5:0]; D[15 :10] D[9:0]; Stuff[5:0] SPI_WRITE_Register SPI_READ_Register SPI_SYNC_Pulse SPI_NOP SPI_SW_Reset μC->transceiver Response to SPI_Write_reg response to previous cmd cmd[3:0]; A[5:0]; D[15:10]; D [9:0]; XCRC[5:0] μC->transceiver SPI_read_reg cmd[3:0]; A[5:0]; Stuff[5:0] St uff[15:0] next cmd μC->transceiver Response to SPI_Read_Register response to previous cmd cmd[3:0]; A[5:0]; D[15:10] D[ 9:0]; XCRC[5:0] μC->transceiver SPI_SYNC_Pulse cmd[3:0]; ChT[3:0]; ChL[3: 0]; Stuf f[3:0] next cmd μC->transceiver Response response to previous cmd cmd[3 :0]; ChT[3:0]; ChL[3:0]; Stuff[3:0] μC->transceiver Response response to previous cmd cmd[3 :0]; Stuff [11:0] μC->transceiver SPI_Get_Data_16b cmd[3:0]; ChID[2:0]; BID [2:0]; Stuff[5:0] Stuff[15:0] Optional: SPI_SYNC_Pulse next cmd μC->transceiver Response to SPI_Get_Data_16b response to previous cmd cmd[3:0]; ChID[2:0]; BID[2:0 ]; Stuff[5:0] D[9:0]; XCRC[5:0] μC->transceiver SP_Get_Data_24b cmd[3:0]; ChID[2:0]; BID[ 2:0]; Stuff[5:0] Stuff [15:0] Optional: SPI_SYNC_Pulse Stuff [15:0] next cmd Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Communication Path Commands/Response s SPI Frame n [SPI Packet Frame] SPI Frame n+1 [SPI Packet Frame] SPI Frame n+2 [SPI Packet Frame] SPI Frame n+3 [SPI Packet Frame] SPI Frame n+4 [SPI Packet Frame] μC->transceiver Response to SPI_Get_Data_24b response to previous cmd cmd[3:0]; CHID[2:0]; BID[2:0 ] Fid[2:0]; Err[1:0]; D[18] D[17:2] D[1:0]; Stuff [7:0]; XCRC[5:0] μC->transceiver SPI_Get_Data_32b cmd[3:0]; ChID[2:0]; BID [2:0]; Stuff [5:0] Stuff [15:0] Optional: SPI_SYNC_Pulse Stuff [15:0] next cmd μC->transceiver Response to SPI_Get_Data_32b response to previous cmd cmd[3:0]; CHID[2:0]; BID[2:0 ] Fid[2:0]; Err[1:0]; D[26] μC->transceiver SPI_Get_Data_48b cmd[3:0]; ChID[2:0]; BID [2:0]; Stuff [5:0] Stuff [15:0] Optional: SPI_SYNC_Pulse Stuff [15:0] Stuff [15:0] next cmd μC->transceiver Response to SPI_Get_Data_48b response to previous cmd cmd[3:0]; CHID[2:0]; BID[2:0 ] Fid[2:0]; Err[1:0]; D[42] μC->transceiver SPI_SW_Reset cmd[3:0]; Stuff [11:0] next cm d μC->transceiver Response response to previous cmd cmd[3 :0]; Stuff [11:0] BID = Buffer Identifier CHID = Channel Identifier ChTx = Channel Trigger for sync pulse (0=disabled; 1=enabled) ChLx = Sync pulse length (0=short; 1=long) Note:

• For 'Read Sensor Data xxbit' - commands the SPI frame n+1 includes optional the 'SYNC Pulse command' instead of NOP command to optimize the SPI bandwidth
• The idle time between consecutive SPI frames has to fulfill parameter ton_NCS .

6.2.3.3 Overview of SPI commands

All valid SPI commands are shown in the table below. Any other combinations (commands from micro controller) are rejected but flagged in register ERROR_STATUS_1[UART_SPI_INV_CMD] for diagnosis purpose. In case of reset or communication error the following response will be sent: 0x0000 in the following valid SPI frame. Execution of command is blocked. Chip select (NCS) low without any clock pulses at SCLK will be ignored. Next response to previous valid frame. Table 6.2.3.3-1: Overview SPI commands SPI command command bits[15:12] remaining bits [11:0] SPI_Write_Register 0001 0000 0000 0000 SPI_Read_Register 0010 0000 0000 0000 SPI_Sync_Pulse 0011 0000 0000 0000 SPI_Get_Data_16b 0100 0000 0000 0000 SPI_Get_Data_24b 0101 0000 0000 0000 SPI_Get_Data_32b 0111 0000 0000 0000 SPI_Get_Data_48b 1000 0000 0000 0000 SPI_NOP 1110 0000 0000 0000 SPI_SW_Reset 1111 0000 0000 0000

6.2.3.4 No Operation Command

Receiving a NOP command, the IC will perform no operation. It shall be used to get the last frame of a SPI communication sequence. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 The bit configuration of this one frame command is shown in the figure below: MSB LSB MSB LSB SDI_RXD idle 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 idle x x x x x x x x x x x x x x x x idle SDO_TXD idle x x x x x x x x x x x x x x x x idle 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 idle SPI frame n SPI frame n+1 Stuff next cmd Response to previous cmd Stuff SPI_NOP SPI_NOP Figure 6.2.3.4-1: SPI NOP Command

6.2.3.5 Write Configuration Register Command

With the command "Write Configuration Register" any 16bit register can be written. Every command consists of three consecutive SPI frames, shown in the figure below. As SPI frame n+2 on SDI_RXD are following cmds allowed: SPI_Write_Register, SPI_Read_Register, SPI_SYNC_Pulse, SPI_NOP or a SPI_SW_Reset. MSB LSB MSB LSB SDI_RXD idle 0 0 0 1 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 idle D9 D8 D7 D6 D 5 D4 D3 D2 D1 D0 0 0 0 0 0 0 idle MSB LSB MSB LSB SDO_TXD idle x x x x x x x x x x x x x x x x idle 0 0 0 1 A5 A4 A3 A2 A1 A0 D15 D14 D13 D1 2 D11 D10 idle MSB LSB SDI_RXD idle x x x x x x x x x x x x x x x x idle MSB LSB SDO_TXD idle D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X5 X4 X3 X2 X1 X0 idle Data Stuff SPI_Write_Register Address Data SPI frame n+2 X CRC Data Response to prev ious cmd SPI_Write_Register Address Data SPI frame n next cmd SPI frame n+1 Figure 6.2.3.5-1: SPI Write Register Command

6.2.3.6 Software Reset Command

With the first execution of the software reset command, all configuration registers are initialized to default values if bit ASIC_CNFG_1[CNFG_LOCK]='0'. If bit ASIC_CNFG_1[CNFG_LOCK]='1' all configuration registers are initialized to default values except register ASIC_CNFG_1 and ASIC_CNFG_2. With the second execution of the software reset command, the bit ASIC_CNFG_1[CNFG_LOCK] is reset to '0'. The Software Reset Command includes one SPI Frame only: Figure 6.2.3.6-1: SPI Software Reset Command

6.2.3.7 Read Configuration Register Command

With the command "Read Configuration Register" any 16bit register can be read. Every command consists of three consecutive SPI frames. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 MSB LSB MSB LSB SDI_RXD idle 0 0 1 0 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 idle SDO_TXD idle x x x x x x x x x x x x x x x x idle 0 0 1 0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D1 2 D11 D10 idle MSB LSB SDI_RXD idle x x x x x x x x x x x x x x x x idle SDO_TXD idle D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X5 X4 X3 X2 X1 X0 idle SPI_Read_Register Address SPI frame n+1 Stuff Response to prev ious cmd Data Data XCRC SPI frame n+2 next cmd SPI_Read_Register Address Stuff SPI frame n Figure 6.2.3.7-1: SPI Read Register Command

6.2.3.8 SYNC Pulse Command

Sync pulses with different widths can be triggered by sending the sync pulse command. For configuration of the sync pulses there are the two bits ChTx and ChLx available. Bit ChTx determines the generation of the sync pulse on the desired channel and ChLx determines the width of the pulse, whereas a logical '0' leads to a short and a logical '1' leads to a long sync pulse. The detailed bit setting is shown in the table below: Table 6.2.3.8-1: SYNC Pulse Command SPI command Command[15:12] SYNC trigger ChT[11:8]+SYN C length ChLx[7:4] Stuffing[3:0] SYNC Pulse 0011 X & X & ChT1 & ChT0 & X & X & ChL1 & ChL0 0000 Long Sync Pulse all Ch 0011 XX11XX11 0000 Long Sync Pulse Ch1 0011 00010001 0000 Long Sync Pulse Ch2 0011 00100010 0000 Short Sync Pulse all Ch 0011 XX11XX00 0000 Short Sync Pulse Ch1 0011 00010000 0000 Short Sync Pulse Ch2 0011 00100000 0000 Example: e.g. '0011 0001 0001 0000' (MSB->LSB) defines one long SYNC pulses on channel 1. Note: The application shall ensure to trigger the SYNC pulse generator only once during TSYNC by max. 1 "SYNC Pulse command" per TSYNC. More trigger commands overwrite the former command (if SYNC pulse delay counter has not exceeded) or trigger a new SYNC pulse. MSB LSB MSB LSB SDI_RXD idle 0 0 1 1 x x x x x x x x 0 0 0 0 idle x x x x x x x x x x x x x x x x idle ChT3 ChT2 ChT1 ChT0 ChL3 ChL2 ChL1 ChL0 SDO_TXD idle x x x x x x x x x x x x x x x x idle 0 0 1 1 x x x x x x x x 0 0 0 0 idle ChT3 ChT2 ChT1 ChT0 ChL3 ChL2 ChL1 ChL0 SPI_SYNC_Pulse Stuff SPI frame n SPI frame n+1 next cmd Response to previous cmd SPI_SYNC_Pulse Stuff Figure 6.2.3.8-1: SPI SYNC Pulse Command

6.2.3.9 Read Sensor Data

Sensor data is requested by executing the "Read Sensor Data" command. The number of SPI frames increases with the number of requested sensor data bits. For example, a request of 16 sensor data bits results in a communication with three SPI frames. The SPI frame 2 has to be filled with stuffing bits or (optional) it can contain the "SYNC Pulse command" to optim- ize the SPI bandwidth by "Read Sensor Data" command. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 For asynchronous sensor mode it is not possible to access the data buffer synchronous to PSI5 data. In this case it is recommended to use the UART mode.

6.2.3.9.1 Read of 16bit (11bit sensor data)

Communication template for 16bit (= 3xFrameID + 2xErrBits + 11 DataBits) is shown in the figure above. Note: Position of PSI5 parity/CRC bits in data frame is represented by highest 'used' data bit Dx of SPI buffer. See following examples:

• 10 bit data + 1 parity bit -> D10 = parity bit
• 8 bit data + 1 parity bit -> D8 = parity bit
• 8 bit data + 3 crc bits -> D10=C0, D9=C1, D8=C2 Figure 6.2.3.9.1-1: SPI Read Sensor Data 16bit cmd3 cmd2 cmd1 cmd0 ChId2 ChId1 ChId0 BID2 BID1 BID0 Channel ID 0 1 0 0 0 0 1 x x x x x x 0 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 SPI_Get_Data_16b; frame1; SDI_RXD MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB Command Buffer ID don't care Identifier Ch1 Identifier Ch2 Identifier Buffer0 Identifier Buffer1 Identifier Buffer2 Identifier Buffer3 Identifier Buffer4 Identifier Buffer5 Figure 6.2.3.9.1-2: SPI Read Sensor Data 16bit-request at SDI_RXD -1st SPI frame- The use of unused channel identifiers for channel 3 and 4 leads to 'invalid address error'. cmd3 cmd2 cmd1 cmd0 ChId2 ChId1 ChId0 BID2 BID1 BID0 Fid2 Fid1 Fid0 Err1 Err0 D0 Command Channel ID Buffer ID Frame ID Error bits Data Identifier Ch1 0 1 0 0 0 0 1 x Identifier Ch2 0 1 0 Identifier Buffer0 0 0 0 Identifier Buffer1 0 0 1 Identifier Buffer2 0 1 0 Identifier Buffer3 0 1 1 Identifier Buffer4 1 0 0 Identifier Buffer5 1 0 1 Identifier Frame1 0 0 0 Identifier Frame2 0 0 1 Identifier Frame3 0 1 0 Identifier Frame4 0 1 1 Identifier Frame5 1 0 0 Identifier Frame6 1 0 1 Error bit - no error 0 0 Error bit - Interface error 0 1 Error bit - ASIC error 1 0 Error bit - Interf. + ASIC error 1 1 SPI_Get_Data_16b; frame2; SDO_TXD MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB Figure 6.2.3.9.1-3: Response to SPI Read Sensor Data 16bit at SDO_TXD -2nd SPI frame- The unused channel identifiers for channel 3 and 4 are not available with this device version and lead to 'invalid address error'.

6.2.3.9.2 Read of 24bit (19bit sensor data)

Communication template for 24bit (= 3xFrameID + 2xErrBits + 19 DataBits): Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Figure 6.2.3.9.2-1: Read Sensor Data 24bit command

6.2.3.9.3 Read of 32bit (27bit sensor data)

Communication template for 32bit (= 3xFrameID + 2xErrBits + 27 DataBits): Figure 6.2.3.9.3-1: Read Sensor Data 32bit command

6.2.3.9.4 Read of 48bit (43bit sensor data)

Position of PSI5 parity/CRC bits -> see 'Read Sensor Data 16bit' Communication template for 48bit (= 3xFrameID + 2xErrBits + 43 DataBits): Figure 6.2.3.9.4-1: Read Sensor Data 48bit command Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Note: For bits 'don't care' in frame n+1 / n+2 on SDO_TXD there are two scenarios: all 12 bits are either '0' or '1';

6.2.4 UART

The UART data rate is derived from an external clock signal f SCLK_UART with DC SCLK_UART at pin SCLK and is calculated with the following formula f UART = . The external clock has to be supplied permanent. The bit shift direction supports "Little Endian" format with LSB sent first.

6.2.4.1 Error Handling

SDI_RXD Frame 1: ChID / Cmd SDO_TXD Fra me2: Address / Stuff Read Register Command Invalid address Frame1: ChID / Fid / Err Frame 2: Cop y fro m read request Response to Read Register Command Fra me 3: D[7:0 ] = 0x00 Fra me4: D[15:8] = 0x00 Fra me 5: Stuff / XCRC Modified data Figure 6.2.4.1-1: UART Error Handling Example 1 see #3: Command 'UART_Read_Register' including invalid address A[5:0]: The 'Response to Read Register Command' is uploaded with with data bits D[15:0] = 0x0000. SDI_RXD Frame1 SDO_TXD Fra me2 Read Register Command NO collision; read reg .cmd decoded after response finished Frame1 Fra me2 Response to Read Register Command Fra me3 Fra me4 Frame5 Fra me1 Frame2 Read Register Command SDI_RXD Frame1 SDO_TXD Fra me2 Read Register Command Frame1 Fra me2 Response to Read Register Command Fra me3 Fra me4 Frame5 Frame1 Frame2 Read Register Command collision ; read reg .cmd decoded before response finished Frame1 Frame2 Figure 6.2.4.1-2: UART Error Handling Example 2 see #6: Collision of 'UART_Read_Register' commands: While read register request command a collision with frames sent by the transceiver might occur. In case of frames sent to the transceiver at pin RXD while the transceiver is transmitting data on pin TXD the RXD frame is ignored. To ensure a response from E521.4x device to a "Read Register cmd", the SDO_TXD has to be idle during decoding of "Read Register cmd". This is feasible if "Transfer of PSI5 data" is predictable. For systems with asynchronous sensors it is recommended to use only one asynchronous sensor per chip. The probability of a response to "Read Register cmd" increases with decreased payload on SDO_TXD. The probability of a response to "Read Register cmd" increases with increased UART baud rate. To decrease payload the UART idle time can be increased by Register ASIC_CNFG_2 / UART_IDLE_TIME[3:0] set to maximum value. If synchronous mode is used the UART idle time can be predicted. Example for UART =4MBaud: Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

• t1 = tnEE (earliest end of frame) = 142us
• t2 3 x staggering + 1 UART frame = 3*10us + 55bit* 0.25us = 44us => idle time = t1 + t2 = 98us Figure 6.2.4.1-3: Syncpulse staggering Table 6.2.4.1-1: UART Error Handling 1 invalid commands ERROR_STATUS_1 [UART_SPI_INV_CMD] Command rejected 2a command 'UART_Write_Register' includ- ing invalid address A[5:0] ERROR_STATUS_1 [UART_SPI_INV_ADDRESS] Command rejected 2b command 'UART_Write_Register' includ- ing ChId 0 ERROR_STATUS_1 [UART_SPI_INV_CMD] Command rejected 2c command 'UART_Write_Register' includ- ing stuff 0 ERROR_STATUS_1 [UART_SPI_INV_ADDRESS] Command rejected 3a Command 'UART_Read_Register' includ- ing invalid address A[5:0] ERROR_STATUS_1 [UART_SPI_INV_ADDRESS] Command rejected 3b Command 'UART_Read_Register' includ- ing ChId 0 ERROR_STATUS_1 [UART_SPI_INV_CMD] Command rejected 3c Command 'UART_Read_Register' includ- ing stuff 0 ERROR_STATUS_1 [UART_SPI_INV_ADDRESS] Command rejected

4 Wrong parity bit received ERROR_STATUS_1

[UART_PERR] Command rejected

5 Frame error = invalid stop bit ERROR_STATUS_1

[UART_FERR] Command rejected Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6 Collision of

'UART_Read_Register' com- mands e.g. read request received while last read was not completed yet ERROR_STATUS_1 [UART_SPI_COLLISION] 2nd Command rejected

7 Command 'Short SYNC pulse'

including ChId >4 ERROR_STATUS_1 [UART_SPI_INV_CMD] Command rejected

8 Command 'Long SYNC pulse'

including ChId >4 ERROR_STATUS_1 [UART_SPI_INV_CMD] Command rejected

9 Command 'No SYNC pulse'

ERROR_STATUS_1 [UART_SPI_INV_CMD] Command rejected

11 Command 'SW reset' including

ERROR_STATUS_1 [UART_SPI_INV_CMD] Command rejected

6.2.4.2 Packet Frame Definition

A frame on the PSI5 interface is represented by a Packet Frame on the transmission line from the transceiver to the Controller. Also the commands on the transmission line from the Controller to the transceiver ASIC, as well as the responses, are represented by a Packet Frame. A Packet Frame can be a concatenation of 1 to 6 UART Frames. For ASIC->uC: An idle time from 1 to 16 idle bits (configurable in register ASIC_CNFG_2) is implemented between consecutive Packet Frames from the UART in order to enable a re-synchronization of the next Packet Frame. The UART frame following an idle time which is equal or greater than the minimum idle time thus is always be assumed as the header of the next Packet Frame (default configuration: one bit minimum idle time between two Packet Frames). For uC->ASIC: frames can be sent w/o idle time (back-to-back transfer possible)

6.2.4.3 UART Frame Definition

μFor transceiver to C communication a UART frame (in side a packet frame) is composed of 1 start bit, 8 data bits, optional parity bit and 1 stop bit. μFor C to transceiver communication a UART frame (in side a packet frame) is composed of 1 start bit, 8 data bits, 1 parity bit and 1 stop bit. μOdd parity is enabled by default. For transceiver to C communication the usage of a parity bit is conf igurable. There is no idle time between UART frames inside a packet frame (i.e. a stop bit of a UART frame is followed by the start bit of a potentially following UART frame without any gap). Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Communication Path idle (H) Start (L) D0 D1 D2 D3 D4 D5 D6 D7 P (odd) Stop (H) idle (H) LSB MSB t idle (H) Start (L) D0 D1 D2 D3 D4 D5 D6 D7 Stop (H) idle (H) LSB MSB idle (H) Start (L) D0 D1 D2 D3 D4 D5 D6 D7 P (odd) Stop (H) idle (H) LSB MSB t Data Transmission transceiv er -> µC µC -> transceiver UART frame UART frame (config1) UART frame (config2) Figure 6.2.4.3-1: UART Data Transmission

6.2.4.4 Overview of Communication Frames

The defined UART commands and responses, with number of UART frames per packet frame, are shown in the table below.

• μPacket frames from C to transceiver means downstrea m
• μPacket frames from transceiver to C means upstream Table 6.2.4.4-1: Overview of Communication Frames Communication Path Commands/Responses UART Frame 1 [Packet- Frame1] UART Frame 2 [PacketFrame1] UART Frame 3 [PacketFrame1] UART Frame 4 [PacketFrame1] UART Frame 5 [Pack- etFrame1] UART Frame 6 [PacketFrame1] μC -> transceiver UART_Write_Register cmd[4:0], ChId[2 :0] Stuff[1:0], A[5:0] D[7:0] D[15:8] μC -> transceiver UART_Read_Register cmd[4:0], ChId[2: 0] Stuff[1:0], A[5:0] μC -> transceiver UART_Short_SYNC_Pulse cmd[4:0], ChId[2 :0] μC -> transceiver UART_Long_SYNC Pulse cmd[4:0], ChId[2 :0] μC -> transceiver UART_No_SYNC_Pulse cmd[4:0], ChId[2:0] μC -> transceiver UART_Software_Reset cmd[4:0], ChId[2: 0] transceiver -> μC Response to Read Register Err[1:0], Fid[2:0], ChId[2 :0] CmdRes[7:0] D[7:0] D[15:8] XCRC[5:0], Stuff[1:0] transceiver -> μC Upload PSI5 data Err[1:0], Fid[2:0], ChId[2:0] D[7:0] x* x* x* x* Note: x * = depending on definition of the corresponding PSI5 frame

6.2.4.5 Overview of UART Commands

≥All valid UART commands are shown in the table below. These commands have a hamming distance 2 to each μother. Any other command from Controller is rejecte d but flagged in register ERROR_STATUS_1[UART_SPI_INV_CMD] for diagnosis purpose. Table 6.2.4.5-1: UART Command Table UART Command Command[7:3] Channel ID[2:0] UART_Write_Register 00001 000 UART_Read_Register 00010 000 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 UART Command Command[7:3] Channel ID[2:0] UART_Short_Sync_Pulse all Ch 00100 000 UART_Short_Sync_Pulse Ch1 00100 001 UART_Short_Sync_Pulse Ch2 00100 010 UART_Long_Sync_Pulse all Ch 00111 000 UART_Long_Sync_Pulse Ch1 00111 001 UART_Long_Sync_Pulse Ch2 00111 010 UART_No_Sync_Pulse 10011 000 UART_Software_Reset 10101 000

6.2.4.6 Write Register Command

The write register sequence includes 4 UART frames: UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0] UART Frame 2: Stuffing bits[1:0], Address bits A[5:0] UART Frame 3: Data Low Byte D[7:0] UART Frame 4: Data Low Byte D[15:8] Table 6.2.4.6-1: Write Register Command Write Register Command Command [7:3] Channel ID [2:0] Write Register Command 00001 000 Srt 0 0 0 1 0 0 0 0 P arity Stp Srt A0 A1 A2 A3 A4 A5 0 0 P arity Stp Srt D 0 D1 D2 D3 D4 D5 D6 D7 P arity Stp C h Id 0 C h Id 1 C h Id 2 C m d 0 C m d 1 C m d 2 C m d 3 C m d 4 Stuff Stuff Srt D8 D9 D 10 D11 D12 D13 D14 D15 P arity Stp idle UART_Write_Register UART Frame 3 Data Lo-Byte UART Frame 4 UART Frame 1 UART Frame 2 Address Data Hi-Byte Figure 6.2.4.6-1: Write Register Command Packet Frame

6.2.4.7 Read Register Command

The read register sequence includes 2 UART frames: UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0] UART Frame 2: Stuffing bits[1:0], Address bits A[5:0] Table 6.2.4.7-1: Read Register Command Read Register Command Command [7:3] Channel ID [2:0] Read Register Command 00010 000 Srt 0 0 0 0 1 0 0 0 P arity Stp Srt A0 A1 A2 A3 A4 A5 0 0 P arity Stp idle C h Id 0 C h Id 1 C h Id 2 C m d 0 C m d 1 C m d 2 C m d 3 C m d 4 Stuff Stuff UART_Read_Register UART Frame 1 UART Frame 2 Address Figure 6.2.4.7-1: Read Register Command Packet Frame

6.2.4.8 Short SYNC Pulse Command

The Short SYNC Pulse Command includes 1 UART Frame only: UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0] Following table shows the configuration of Channel IDs: Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.4.8-1: Short SYNC Pulse Command Short SYNC Pulse Command Command [7:3] Channel ID [2: 0] Short Sync Pulse all Ch 00100 000 Short Sync Pulse Ch1 00100 001 Short Sync Pulse Ch2 00100 010 Srt x x x 0 0 1 0 0 P arity Stp idle C h Id 0 C h Id 1 C h Id 2 C m d 0 C m d 1 C m d 2 C m d 3 C m d 4 UART_Short_SYNC_Pulse UART Frame Figure 6.2.4.8-1: Short SYNC Command Packet Frame

6.2.4.9 Long SYNC Pulse Command

The Long SYNC Pulse Command includes 1 UART frame only: UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0] Following table shows the configuration of Channel IDs: Table 6.2.4.9-1: Long SYNC Pulse Command Long SYNC Pulse Command Command [7:3] Channel ID [2:0 ] Long Sync Pulse all Ch 00111 000 Long Sync Pulse Ch1 00111 001 Long Sync Pulse Ch2 00111 010 Srt x x x 1 1 1 0 0 P arity Stp idle C h Id 0 C h Id 1 C h Id 2 C m d 0 C m d 1 C m d 2 C m d 3 C m d 4 UART Frame UART_Long_SYNC_Pulse Figure 6.2.4.9-1: Long SYNC Command Packet Frame

6.2.4.10 No SYNC Pulse Command

For the tooth gap method, if a logical '0' (=absence of SYNC pulse) for ECU to sensor communication is required, μa no sync pulse command can be send by the Controll er. The no sync pulse command includes 1 UART frame only. UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0] Table 6.2.4.10-1: No SYNC Pulse Command No SYNC Pulse Command Command [7:3] Channel ID [2:0] No sync pulse 10011 000 Srt 0 0 0 1 1 0 0 1 P arity Stp idle C h Id 0 C h Id 1 C h Id 2 C m d 0 C m d 1 C m d 2 C m d 3 C m d 4 UART_No_SYNC_Pulse UART Frame Figure 6.2.4.10-1: No SYNC Pulse Command Packet Frame Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.2.4.11 Software Reset Command

With the first execution of the software reset command, all configuration registers are initialized to default values if bit ASIC_CNFG_1[CNFG_LOCK]='0'. If bit ASIC_CNFG_1[CNFG_LOCK]='1' all configuration registers are initialized to default values except register ASIC_CNFG_1 and ASIC_CNFG_2. With the second execution of the software reset command, the bit ASIC_CNFG_1[CNFG_LOCK] is reset to '0'. The Software Reset Command includes 1 UART frame only: UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0] Table 6.2.4.11-1: Software Reset Command Software Reset Command Command [7:3] Channel ID [2:0] Software Reset 10101 000 Srt 0 0 0 1 0 1 0 1 P arity Stp idle C h Id 0 C h Id 1 C h Id 2 C m d 0 C m d 1 C m d 2 C m d 3 C m d 4 UART_SW_Reset UART Frame Figure 6.2.4.11-1: Software Reset Command Frame

6.2.4.12 Response to Read Register Command

Each valid read command, received by the transceiver ASIC, results in a response sequence including 5 UART Frames. UART Frame 1: Channel Identifier ChId[2:0]; Frame Identifier Fid[2:0]; Error bits Err[1:0] UART Frame 2: Command response CmdRes[4:0]; Channel Identifier[2:0]= copy from UART frame 1 of read request UART Frame 3: Data Low Byte D[7:0] UART Frame 4: Data Low Byte D[15:8] UART Frame 5: Stuffing bits Stuff[1:0]; 6bit checksum XCRC[5:0] Following table shows the bit configuration of UART Frame 1 including ChId, Fid and Err bits. Table 6.2.4.12-1: Response To Read Command Bit Configuration Response to Read Register: Configura- tion of UART Frame 1 Error bits[7:6] Frame ID[5:3] Channel ID[2:0] Error bit - no ASIC error 00 000 000 Error bit - interface error 01 000 000 Error bit - ASIC error 10 000 000 Error bit - ASIC and interface error 11 000 000 idle Srt 0 0 0 0 0 0 0 E rr1 Stp Srt 0 0 0 0 1 0 0 0 Stp Srt D0 D1 D2 D3 D 4 D 5 D6 D7 S tp C h Id 0 C h Id 1 C h Id 2 F id 0 F id 1 F id 2 E r r 0 C h Id 0 C h Id 1 C h Id 2 C m d 0 C m d 1 C m d 2 C m d 3 C m d 4 Srt D8 D9 D10 D11 D12 D13 D14 D15 Stp Srt 0 0 X0 X1 X2 X3 X4 X5 Stp idl e Stuff Stuff UART Frame 4 UART Frame 5 Data Hi-Byte X CRC UART Frame 1 UART Frame 2 UART Frame 3 Packet Frame Header Cmd Response (copy from read request) Data Lo-Byte Figure 6.2.4.12-1: Response to Read Register Command Packet Frame Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.2.4.13 Transfer PSI5 Data

μIncoming PSI5 data frames are processed and transmitted to the Controller in UART frames. The sequence includes 3 - 6 UART frames, depending on the length of the corresponding PSI5 frame. Example: Frame configuration for minimum packet frame (according to v1.3): UART Frame 1: Channel Identifier ChId[2:0]; Frame Identifier Fid[2:0]; Error bits Err[1:0] UART Frame 2: Data bits D[7:0] UART Frame 3: Parity; Stuffing bit Stuff; 6bit checksum XCRC[5:0] idle Srt ChId0 ChId1 ChId2 Fid0 Fid1 Fid2 E rr0 E rr1 Stp Srt D0 D1 D2 D 3 D4 D5 D6 D7 Stp Srt P arity 0 X0 X1 X2 X3 X4 X5 Stp idle Stuff X CRC UART Frame 3 Packet Frame Header PSI5 Message UART Frame 1 UART Frame 2 Figure 6.2.4.13-1: Example: Upload PSI5 Data Minimum Packet Frame Example: Frame configuration for maximum Packet Frame (according to v2.0): UART Frame 1: Channel Identifier ChId[2:0]; Frame Identifier Fid[2:0]; Error bits Err[1:0] UART Frame 2: Data bits D[7:0] UART Frame 3: Data bits D[15:8] UART Frame 4: Data bits D[23:16] UART Frame 5: Data bits D[27:24]; 3bit checksum C[2:0]; Stuffing bit Stuff UART Frame 6: Stuffing bits Stuff[1:0]; 6bit checksum XCRC[5:0] idle Srt ChId0 C hId1 C hId2 Fid0 Fid1 Fid2 E rr0 E rr1 Stp Srt D 0 D 1 D2 D 3 D 4 D5 D 6 D 7 Stp Srt D8 D 9 D10 D11 D 12 D13 D14 D15 Stp Srt D16 D17 D 18 D 19 D20 D21 D 22 D23 Stp Srt D24 D25 D 26 D 27 C 2 C1 C 0 0 Stp Srt 0 0 X0 X1 X2 X3 X4 X5 Stp idle Stuff Stuff Stuff UART Frame 6 Packet Frame Header PSI5 Message X CRC PSI5 Message UART Frame 4 UART Frame 5 PSI5 Message PSI5 Message UART Frame 3 UART Frame 1 UART Frame 2 Figure 6.2.4.13-2: Example: Upload PSI5 Data Maximum Packet Frame Following table shows the bit configuration of UART Frame 1 including ChId, Fid and Err bits. Table 6.2.4.13-1: PSI5 Data UART Frame1 Bit Configuration PSI5 data: Configuration of UART Frame 1 Error bits F rame ID Channel ID Identifier for channel0 (diagnosis) xx xxx 000 Identifier for channel1 xx xxx 001 Identifier for channel2 xx xxx 010 Identifier for frame1 xx 000 xxx Identifier for frame2 xx 001 xxx Identifier for frame3 xx 010 xxx Identifier for frame4 xx 011 xxx Identifier for frame5 xx 100 xxx Identifier for frame6 xx 101 xxx Error bit - no error 00 xxx xxx Error bit - Interface error 01 xxx xxx Error bit - ASIC error 10 xxx xxx Error bit - Interface + ASIC error 11 xxx xxx Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.2.5 XCRC[5:0] Calculation

A 6-bit XCRC for error detection is calculated and added at the last UART/SPI frame, transferred from transceiver μto C at pin SDO_TXD, for the defined packet frames. The generator polynomial of the six bit CRC is g(x) = + + + 1 with a binary CRC initialization value "0 10101". The transmitter extends the data bits by six zeros (= XCRC default condition) as shown in the figures above. This augmented data word is fed (LSB first) into the shift registers of the CRC generator. T TT T TTInput data 0*X5 1*X = 1 + X3 + X4 + X6 C0 C1 C2 C3 C4 C5 Figure 6.2.5-1: XCRC-calculation for SPI frames UART Packet Frames : The sequence of bit shift into the register for the CRC calculation is shown in below, starting with LSB first. The number of stuffing bits varies with the payload (not shown in the figures below). 1. Transfer PSI5 Data LSB MSB x x x x x x x x x x x x x x x x x 0 0 0 x x x x x x D0 D1 D2 …… Dn-2 Dn-1 C2 C1 C0 …. X 0 X 5 Channel ID Frame ID Error bits PSI5 frame data P/CRC X CR C; default = zeros Stuffing Figure 6.2.5-2: XCRC: Example Transfer PSI5 Data 2. Response to Read Register Command LSB MSB 0 0 0 0 0 0 0 x 0 0 0 0 1 0 0 0 x x x x x x 0 0 x x x x x x D0 D1 D2 …… D14 D15 X 0 X 5 X CRC; default = zeros Stuffing Channel ID Frame ID Error bits Cmd Response (copy from read request) Channel ID Cmd register data Figure 6.2.5-3: XCRC: Example Response to Read Command SPI Packet Frames : The sequence is done in the similar way than for UART Packet frames, except

• Starting with MSB first
• Changed payload (e.g. additional Buffer ID, SYNC_LONG bits) Example Read Sensor Data 24bit : Figure 6.2.5-4: XCRC Example Read Sensor Data 24bit Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.2.6 CONFIGURATION

6.2.6.1 ASIC Configuration

The device can be configured and maintained with configuration, diagnosis and error registers. Every register contains 16 bits, so only 16 bit read/write requests are processed. Any of the two device channels can be configured independently by writing the read/write (R/W) configuration registers ASIC_CNFG_1, ASIC_CNFG_2 and ASIC_CNFG_3. The following parameters can be modified per channel:

• Δcurrent threshold for the data comparator ( Is_CHx)
• sync sustain voltage V3 (VSYNC_V3_CHx)
• channel configuration of synchronous / asynchronous mode (ASYNC_CHx)
• PSI5 bit time [kbps] / Baud rate per channel (PSI5_BIT_TIME_CHx)
• enabling of interfaces SIF_CHx (EN_CHx) The detailed settings are described in the register table below: Table 6.2.6.1-1: ASIC CONFIGURATION Register Name Address Description ASIC_CNFG_1 0x00 ASIC Configuration Register 1 ASIC_CNFG_2 0x01 ASIC Configuration Register 2 ASIC_CNFG_3 0x02 ASIC Configuration Register 3 Reading of unused bits will always return '0' and writing of unused bits don't care. Writing of read-only- or read-on clear-registers, don't care. For SPI accesses the response via SDO_TXD is the echo of the write request (identic- ally behaviour than for write on read/write-registers). Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.1-2: Register ASIC_CNFG_1 (0x00) ASIC Configuration Register 1 MSB LSB Content CNF G_L OCK - - - MCD_DAT A_CMP_W [1:0] - - VSY NC_ V3_ CH2 VSY NC_ V3_ CH1 - - ΔIS_ CH2 ΔIS_ CH1 V_BUS[1:0 Reset value 0 0 0 0 00 0 0 0 0 0 0 0 0 00 Access R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description CNFG_LOCK : lock bit for configuration registers 0b0: registers ASIC_CNFG_1 and ASIC_CNFG_2 are not locked, an update is possible 0b1: registers ASIC_CNFG_1 and ASIC_CNFG_2 are locked, no update possible (exception: The 2nd SW_reset command resets the lock and allows this two registers to be updated) MCD_DATA_CMP_W[1:0] : Manchester data compare window setting 0b00: DATA_EDGE = 18 clock counts (low sensitive) & COMPENSATION_WINDOW = 23 clock counts @4MHz: DATA_E=(18*250ns = 4.5us; CMP=23*250ns=5.75us; => Total=10.25us @6MHz: DATA_E=18*167ns = 3us; CMP=23*167ns=3.83us; => Total = 6.83us 0b01: DATA_EDGE = 12 clock counts (low sensitive) & COMPENSATION_WINDOW = 26 clock counts @4MHz: DATA_E=12*250ns = 3us; CMP=26*250ns=6.5us; => Total=9.5us @6MHz: DATA_E=12*167ns = 2us; CMP=26*167ns=4.33us; => Total = 6.33us 0b10: DATA_EDGE = 8 clock counts (low sensitive) & COMPENSATION_WINDOW = 28 clock counts @4MHz: DATA_E=8*250ns = 2us; CMP=28*250ns=7us; => Total=9us @6MHz: DATA_E=8*167ns = 1.33us; CMP=28*167ns=4.67us; => Total = 6us VSYNC_V3_CH2 : sync sustain voltage V3 (VSYNC_V3_CHx) 0b0: V3 = 4.8V typical (common mode) 0b1: V3 = 3.7V typical (low power mode) VSYNC_V3_CH1 : sync sustain voltage V3 (VSYNC_V3_CHx) 0b0: V3 = 4.8V typical (common mode) 0b1: V3 = 3.7V typical (low power mode) ∆IS_CH2 Δ : current threshold for the data comparator ( Is_CH x) Δ0b0: IS = 26mA Δ0b1: IS = 13mA ∆IS_CH1 Δ : current threshold for the data comparator ( Is_CH x) Δ0b0: IS = 26mA Δ0b1: IS = 13mA V_BUS[1:0] : V BUS selection 0b00: LDO disabled; V BUS must be supplied externaly 0b01: VBUS = 5.15V 0b10: VBUS = 6.65V 0b11: VBUS = 7.7V Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.1-3: Register ASIC_CNFG_2 (0x01) ASIC Configuration Register 2 MSB LSB Content - - UART_IDLE_TIME[3:0] REV _CU R_C H_DI S IDAC _RE S - - PSI5 _BIT _TIM E_C PSI5 _BIT _TIM E_C - - ASY NC_ CH2 ASY NC_ CH1 Reset value 0 0 0000 0 0 0 0 0 0 0 0 0 0 Access R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description UART_IDLE_TIME[3:0] : UART idle time between two consecutive UART packet frames (to enable a re-synchronization) 0b0000: minimum idle time = DEFAULT 0b1111: maximum idle time REV_CUR_CH_DIS : Disable of channels for reverse current condition 0b0: disabled -> no switch-off of channels by IC (default) 0b1: enabled -> switch-off dedicated channel if REV_CUR_CHx='1' IDAC_RES : IDAC resolution 0b0: 300 uA per LSB (default) 0b1: 200 uA per LSB PSI5_BIT_TIME_CH2 : PSI5 bit time 0b0: bit time equal to 8us (=125kbps) 0b1: bit time equal to 5.3us (=189kbps) PSI5_BIT_TIME_CH1 : PSI5 bit time 0b0: bit time equal to 8us (=125kbps) 0b1: bit time equal to 5.3us (=189kbps) ASYNC_CH2 : channel mode configuration 0b0: channel in synchronous configuration 0b1: channel in asynchronous configuration ASYNC_CH1 : channel mode configuration 0b0: channel in synchronous configuration 0b1: channel in asynchronous configuration Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.1-4: Register ASIC_CNFG_3 (0x02) ASIC Configuration Register 3 MSB LSB Content - - - BL_ CHA NEL BL_ CHA NEL GEN _FU SE_ RD - EN_LOOP[ 1:0] EN_ CP_ SYN C EN_ UAR T_T XD_ PAR- ITY EN_ UAR T_R XD_ PAR- ITY - - EN_ CH2 EN_ CH1 Reset value 0 0 0 0 0 0 0 00 0 1 0 0 0 0 0 Access R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description BL_CHANNEL2 : blanking time of MCD/SYNC generation/ovc after channel enable 0=5ms 1=10ms BL_CHANNEL1 : blanking time of MCD/SYNC generation/ovc after channel enable 0=5ms 1=10ms GEN_FUSE_RD : Start fuse read out via UART/SPI 0b0: no fuse read out 0b1: start additional fuse read out EN_LOOP[1:0] : enable channel in loop back test mode 0b000: all Channel in normal operation 0b001: Channel1 loop back test mode enabled 0b010: Channel2 loop back test mode enabled EN_CP_SYNC : Enable Sync pulse charge pump 0b0:disabled 0b1:enabled EN_UART_TXD_PARITY : Enable parity bit addition for UART Tx frames 0b0:disabled 0b1:enabled EN_UART_RXD_PARITY : Enable parity check for UART received frames 0b0:disabled 0b1:enabled EN_CH2 : Enable Interface SIFx 0b0: Disable PSI5 Interface 0b1: Enable PSI5 Interface EN_CH1 : Enable Interface SIFx 0b0: Disable PSI5 Interface 0b1: Enable PSI5 Interface

6.2.6.1.1 Asynchronous mode

Note: Only one sensor allowed per SIFx. With enable of SIFx via configuration register ASIC_CNFG_3[EN_CHx], the sensor is supplied with voltage VSIFx and starts to transmit PSI5 sensor frames. For received frames, the implemented Manchester decoder adds to each valid frame the Fid ="0b001". For UART interface, the Packet frame is transferred to uC automatically. With appropriate UART baud rate, the IC transmits the data to the uC without any overwriting. For SPI interface, the decoded frame is available in BID[0] of SPI data buffer. The uC has to ensure to read BID[0] before a new PSI5 frame is decoded; otherwise it's overwritten. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

6.2.6.2 Timeslot Configuration

For every channel there are seven configuration registers available to configure the following parameters:

• six independent configurable PSI5 timeslots
• timeslot length
• frame length
• parity or crc selection
• error check enabling
• desired delay of sync pulse generation
• mandatory buffer for SPI access Details are described in the following register table. Table 6.2.6.2-1: CHANNEL_CONFIGURATION Register Name Address Description CH1_CFG1 0x03 Channel 1 Configuration Register 1 CH1_CFG2 0x04 Channel 1 Configuration Register 2 CH1_CFG3 0x05 Channel 1 Configuration Register 3 CH1_CFG4 0x06 Channel 1 Configuration Register 4 CH1_CFG5 0x07 Channel 1 Configuration Register 5 CH1_CFG6 0x08 Channel 1 Configuration Register 6 CH1_CFG7 0x09 Channel 1 Configuration Register 7 CH2_CFG1 0x0A Channel 2 Configuration Register 1 CH2_CFG2 0x0B Channel 2 Configuration Register 2 CH2_CFG3 0x0C Channel 2 Configuration Register 3 CH2_CFG4 0x0D Channel 2 Configuration Register 4 CH2_CFG5 0x0E Channel 2 Configuration Register 5 CH2_CFG6 0x0F Channel 2 Configuration Register 6 CH2_CFG7 0x10 Channel 2 Configuration Register 7 It is highly recommended, not to change the registers CHX_CFG1(IDAC_CNT_MODE, IDAC_CNT_INC2[1:0], IDAC_CNT_INC1[1:0]) and CHX_CFG2(IDAC_CNT_DEC2[1:0], IDAC_CNT_DEC1[1:0]) since these registers control the Ibase tracking function! Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.2-2: Register CH1_CFG1 (0x03) Channel 1 Configuration Register 1 MSB LSB Content IDAC _CN T_M ODE IDAC_CNT _INC2[1:0] IDAC_CNT _INC1[1:0] EN_ ER_ CHK T1_ CRC TS1_FLEN[4:0] T1_LEN[3:0] Reset value 0 00 00 0 0 00011 0100 Access R/W R/W R/W R/W R/W R/W R/W Bit Description IDAC_CNT_MODE : reserved IDAC_CNT_INC2[1:0] : reserved IDAC_CNT_INC1[1:0] : reserved EN_ER_CHK : Enable parity/CRC check functionality 0b0: disable functionality 0b1: enable functionality T1_CRC : PSI5 frame error detection mode of frames starting in timeslot 1 0b0: PSI5 Sensor in parity mode 0b1: PSI5 Sensor in CRC mode TS1_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 1 frame length includes start bit + data + parity/crc [TSx_FLEN] 16 = [Frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: Frame length => [11..33] 0x18 - 0x1F: reserved Default: P10P (Airbag) = 2 + 10 + 1 = 13->0x3 T1_LEN[3:0] : Timeslot 1 Length 0b_nnnn: nnnn x 32 us => [0us..480us] Default: t = 4*32us = 128us Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.2-3: Register CH1_CFG2 (0x04) Channel 1 Configuration Register 2 MSB LSB Content - IDAC_CNT _DEC2[1:0 IDAC_CNT _DEC1[1:0 EN_ ER_ CHK T2_ CRC TS2_FLEN[4:0] T2_LEN[3:0] Reset value 0 01 01 0 0 00011 0101 Access R/W R/W R/W R/W R/W R/W R/W Bit Description IDAC_CNT_DEC2[1:0] : reserved IDAC_CNT_DEC1[1:0] : reserved EN_ER_CHK : Enable parity/CRC check functionality 0b0: disable functionality 0b1: enable functionality T2_CRC : PSI5 frame error detection mode of frames starting in timeslot 2 0b0: PSI5 Sensor in parity mode 0b1: PSI5 Sensor in CRC mode TS2_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 2 frame length includes start bit + data + parity/crc [TSx_FLEN] 16 = [Frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: Frame length => [11..33] 0x18 - 0x1F: reserved Default: P10P (Airbag) = 2 + 10 + 1 = 13->0x3 T2_LEN[3:0] : Timeslot 2 Length 0b_nnnn: nnnn x 32 us => [0us..480us] Default: t = 5*32us = 160us Table 6.2.6.2-4: Register CH1_CFG3 (0x05) Channel 1 Configuration Register 3 MSB LSB Content - - - - - EN_ ER_ CHK T3_ CRC TS3_FLEN[4:0] T3_LEN[3:0] Reset value 0 0 0 0 0 0 0 00011 0101 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description EN_ER_CHK : Enable parity/CRC check functionality 0b0: disable functionality 0b1: enable functionality T3_CRC : PSI5 frame error detection mode of frames starting in timeslot 3 0b0: PSI5 Sensor in parity mode 0b1: PSI5 Sensor in CRC mode TS3_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 3 frame length includes start bit + data + parity/crc [TSx_FLEN] 16 = [Frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: Frame length => [11..33] 0x18 - 0x1F: reserved Default: P10P (Airbag) = 2 + 10 + 1 = 13->0x3 T3_LEN[3:0] : Timeslot 3 Length 0b_nnnn: nnnn x 32 us => [0us..480us] Default: t = 5*32us = 160us Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.2-5: Register CH1_CFG4 (0x06) Channel 1 Configuration Register 4 MSB LSB Content - - - - - EN_ ER_ CHK T4_ CRC TS4_FLEN[4:0] T4_LEN[3:0] Reset value 0 0 0 0 0 0 0 00000 0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description EN_ER_CHK : Enable parity/CRC check functionality 0b0: disable functionality 0b1: enable functionality T4_CRC : PSI5 frame error detection mode of frames starting in timeslot 4 0b0: PSI5 Sensor in parity mode 0b1: PSI5 Sensor in CRC mode TS4_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 4 frame length includes start bit + data + parity/crc [TSx_FLEN] 16 = [Frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: Frame length => [11..33] 0x18 - 0x1F: reserved Default: = 0 T4_LEN[3:0] : Timeslot 4 Length 0b_nnnn: nnnn x 32 us => [0us..480us] Default: t = 0*32us = 0us Table 6.2.6.2-6: Register CH1_CFG5 (0x07) Channel 1 Configuration Register 5 MSB LSB Content - - - - - EN_ ER_ CHK T5_ CRC TS5_FLEN[4:0] T5_LEN[3:0] Reset value 0 0 0 0 0 0 0 00000 0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description EN_ER_CHK : Enable parity/CRC check functionality 0b0: disable functionality 0b1: enable functionality T5_CRC : PSI5 frame error detection mode of frames starting in timeslot 5 0b0: PSI5 Sensor in parity mode 0b1: PSI5 Sensor in CRC mode TS5_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 5 frame length includes start bit + data + parity/crc [TSx_FLEN] 16 = [Frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: Frame length => [11..33] 0x18 - 0x1F: reserved Default: = 0 T5_LEN[3:0] : Timeslot 5 Length 0b_nnnn: nnnn x 32 us => [0us..480us] Default: t = 0*32us = 0us Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.2-7: Register CH1_CFG6 (0x08) Channel 1 Configuration Register 6 MSB LSB Content - - - - - EN_ ER_ CHK T6_ CRC TS6_FLEN[4:0] T6_LEN[3:0] Reset value 0 0 0 0 0 0 0 00000 0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description EN_ER_CHK : Enable parity/CRC check functionality 0b0: disable functionality 0b1: enable functionality T6_CRC : PSI5 frame error detection mode of frames starting in timeslot 6 0b0: PSI5 Sensor in parity mode 0b1: PSI5 Sensor in CRC mode TS6_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 6 frame length includes start bit + data + parity/crc [TSx_FLEN] 16 = [Frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: Frame length => [11..33] 0x18 - 0x1F: reserved Default:= 0 T6_LEN[3:0] : Timeslot 6 Length 0b_nnnn: nnnn x 32 us => [0us..480us] Default: t = 0*32us = 0us Table 6.2.6.2-8: Register CH1_CFG7 (0x09) Channel 1 Configuration Register 7 MSB LSB Content - - - - SPI_BUF- FER_CNF G[1:0] SYNC_DLY[9:0] Reset value 0 0 0 0 11 0000 Access R/W R/W R/W R/W R/W R/W Bit Description SPI_BUFFER_CNFG[1:0] : SPI buffer (=96bit) configuration 0b00: 48bit/buffer;2 partial buffers; Buffer identifiers[0,1] 0b01: 32bit/buffer;3 partial buffers; Buffer identifiers[0,1,2] 0b10: 24bit/buffer;4 partial buffers; Buffer identifiers[0,1,2,3] 0b11: 16bit/buffer;6 partial buffers; Buffer identifiers[0,1,2,3,4,5](=default) SYNC_DLY[9:0] : Sync pulse delay 0xnnn: nnn x 8/fCLK_INT =>[0us..682us] Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.2-9: Register CH2_CFG1 (0x0A) Channel 2 Configuration Register 1 MSB LSB Content IDAC _CN T_M ODE IDAC_CNT _INC2[1:0] IDAC_CNT _INC1[1:0] EN_ ER_ CHK T1_ CRC TS1_FLEN[4:0] T1_LEN[3:0] Reset value 0 00 00 0 0 00011 0100 Access R/W R/W R/W R/W R/W R/W R/W Bit Description IDAC_CNT_MODE : reserved IDAC_CNT_INC2[1:0] : reserved IDAC_CNT_INC1[1:0] : reserved EN_ER_CHK : see CH1_CFG1 T1_CRC : see CH1_CFG1 TS1_FLEN[4:0] : see CH1_CFG1 T1_LEN[3:0] : see CH1_CFG1 Table 6.2.6.2-10: Register CH2_CFG2 (0x0B) Channel 2 Configuration Register 2 MSB LSB Content - IDAC_CNT _DEC2[1:0 IDAC_CNT _DEC1[1:0 EN_ ER_ CHK T2_ CRC TS2_FLEN[4:0] T2_LEN[3:0] Reset value 0 01 01 0 0 00011 0101 Access R/W R/W R/W R/W R/W R/W R/W Bit Description IDAC_CNT_DEC2[1:0] : reserved IDAC_CNT_DEC1[1:0] : reseved EN_ER_CHK : see CH1_CFG2 T2_CRC : see CH1_CFG2 TS2_FLEN[4:0] : see CH1_CFG2 T2_LEN[3:0] : see CH1_CFG2 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.2-11: Register CH2_CFG3 (0x0C) Channel 2 Configuration Register 3 MSB LSB Content - - - - - EN_ ER_ CHK T23_ CRC TS3_FLEN[4:0] T3_LEN[3:0] Reset value 0 0 0 0 0 0 0 00011 0101 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description EN_ER_CHK : see CH1_CFG3 T23_CRC : see CH1_CFG3 TS3_FLEN[4:0] : see CH1_CFG3 T3_LEN[3:0] : see CH1_CFG3 Table 6.2.6.2-12: Register CH2_CFG4 (0x0D) Channel 2 Configuration Register 4 MSB LSB Content - - - - - EN_ ER_ CHK T4_ CRC TS4_FLEN[4:0] T4_LEN[3:0] Reset value 0 0 0 0 0 0 0 00000 0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description EN_ER_CHK : see CH1_CFG4 T4_CRC : see CH1_CFG4 TS4_FLEN[4:0] : see CH1_CFG4 T4_LEN[3:0] : see CH1_CFG4 Table 6.2.6.2-13: Register CH2_CFG5 (0x0E) Channel 2 Configuration Register 5 MSB LSB Content - - - - - EN_ ER_ CHK T5_ CRC TS5_FLEN[4:0] T5_LEN[3:0] Reset value 0 0 0 0 0 0 0 00000 0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description EN_ER_CHK : see CH1_CFG5 T5_CRC : see CH1_CFG5 TS5_FLEN[4:0] : see CH1_CFG5 T5_LEN[3:0] : see CH1_CFG5 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.2-14: Register CH2_CFG6 (0x0F) Channel 2 Configuration Register 6 MSB LSB Content - - - - - EN_ ER_ CHK T6_ CRC TS6_FLEN[4:0] T6_LEN[3:0] Reset value 0 0 0 0 0 0 0 00000 0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description EN_ER_CHK : see CH1_CFG6 T6_CRC : see CH1_CFG6 TS6_FLEN[4:0] : see CH1_CFG6 T6_LEN[3:0] : see CH1_CFG6 Table 6.2.6.2-15: Register CH2_CFG7 (0x10) Channel 2 Configuration Register 7 MSB LSB Content - - - - SPI_BUF- FER_CNF G[1:0] SYNC_DLY[9:0] Reset value 0 0 0 0 11 0000 Access R/W R/W R/W R/W R/W R/W Bit Description SPI_BUFFER_CNFG[1:0] : see CH1_CFG7 SYNC_DLY[9:0] : see CH1_CFG7

6.2.6.2.1 Timeslot Length

The timeslotx length (Bit TX_LEN) is used to assign the frame identifier (Fid) to received PSI5 frames. Tx_LEN is implemented as a counter. Once loaded, it's counting down to 0. T1_LEN is loaded with start of SYNC pulse (after SYNC_DLY has expired). If T1_LEN has expired, the following counter T2_LEN is loaded ... until T6_LEN has expired. μFor TSX_LEN=0x00(=no frame) the TX_LEN counter is also loaded with 0 and expires with the next 2 s cloc k cycle. The timeslot length (bit TX_LEN) is used to assign the frame identifier (fid) to decoded PSI5 frames. Following two examples based on PSI5-P10P-500/3L (Airbag), show the correlation of Fid to TX_LEN counter. The Fid is added to the PSI5 sensor data by the Manchester decoder (MD) once the first start bit (rising slope) is detected. Example 1, default configuration; T3_LEN expires within frame3. Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 idle frame1 SYNC NO Reset of FID due to unexpected SYNC pulse 0b001 Fid 0b000 frame2 0b010 Flag SYNC_DATA _INV_CHx = '1' 0b011 '1' -> discard decoded MCD data Target: no storage / upload of data to µC with wron g FID Clear on read Extention possible until MDC in idle state unexp. SYNC Figure 6.2.6.2.1-3: Example2: TxLEN Configuration: Unexptected Sync Pulse

6.2.6.3 Error Registers

There are ten error status registers available for reading, which are cleared on read (clear on read, RC). The following error information is available:

• MD Unexpected frame for each frame and channel
• MD No frames for each frame and channel
• MD Frame error for each frame and channel
• MD Parity error for each frame and channel
• Reverse current status of each channel
• Buffer configuration error of each channel
• Diagnosis status of each channel
• Over current status of each channel
• UART/SPI status information (invalid address, invalid command, SPI clock erreor, UART read request collision) Details are described in the following register table. Table 6.2.6.3-1: Error Status Register Register Name Address Description ERROR_STATUS_ 0x25 Global ASIC errors ERROR_STATUS_ 0x26 Channel errors ERROR_STATUS_ 0x27 Four error bits per frame (1-4) channel 1 ERROR_STATUS_ 0x28 Four error bits per frame (5-6) channel 1 and a nalog errors ERROR_STATUS_ 0x29 Four error bits per frame (1-4)channel 2 ERROR_STATUS_ 0x2A Four error bits per frame (5-6)channel 2 and an alog errors Reading of unused bits will always return '0' and writing of unused bits don't care. Writing to read only or read on clear registers don't care. The SPI echo response to a write request is independently of register type (R/W, R, RC). Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.3-2: Register ERROR_STATUS_1 (0x25) Global ASIC errors MSB LSB Content - - - - - - - - UAR T_S PI_I NV_ ADD RES S VBU S_O V DIA G_O T SPI_ CLK _ER R UAR T_S PI_C OL- LI- SIO N UAR T_S PI_I NV_ CMD UAR T_F ERR UAR T_P ERR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/C R/C R/C1 R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/ C R/C Bit Description UART_SPI_INV_ADDRESS : UART/SPI address check 0b0: valid address 0b1: invalid address VBUS_OV : VBUS over voltage bit 0b0: no over voltage; signal vbus_ov_f = 0 0b1: over voltage; signal vbus_ov_f = 1 DIAG_OT : Overtemperatur bit 0b0: no overtemperature; signal i_ot = 0 0b1: overtemperature; signal i_ot = 1 SPI_CLK_ERR : SPI clock error 0b0: no clock error 0b1: SPI clock error (number of clock cycles 16) UART_SPI_COLLISION : UART/SPI read request collision status latch (clear on read) 0b0: no collision happend 0b1: UART/SPI read request received while last read was not completed yet UART_SPI_INV_CMD : UART/SPI command error status latch (clear on read) 0b0: no command error 0b1: invalid command UART_FERR : UART frame error status latch (clear on read) 0b0: no frame error seen 0b1: frame error detected UART_PERR : UART parity error status latch (clear on read) 0b0: no parity error seen 0b1: parity error detected Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.3-3: Register ERROR_STATUS_2 (0x26) Channel errors MSB LSB ERR CH_ ERR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C Bit Description CH_ERR_2 : Channel 2 error status (overall) 0b000: all bits of ERROR_STATUS_5 + ERROR_STATUS_6 are equal to '0' (= OR combination of these bits) 0b001: number of bits with '1' of ERROR_STATUS_5 + ERROR_STATUS_6 is higher or equal to 1 (= OR combination of these bits) CH_ERR_1 : Channel 1 error status (overall) 0b000: all bits of ERROR_STATUS_3 + ERROR_STATUS_4 are equal to '0' (= OR combination of these bits) 0b001: number of bits with '1' of ERROR_STATUS_3 + ERROR_STATUS_4 is higher or equal to 1 (= OR combination of these bits) Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.3-4: Register ERROR_STATUS_3 (0x27) Four error bits per frame (1-4) channel 1 MSB LSB Content MD_ UNE X_F R_C H1_ MD_ NO_ FR_ CH1 _F4 MD_ FER R_F R_C H1_ MD_ PER R_F R_C H1_ MD_ UNE X_F R_C H1_ MD_ NO_ FR_ CH1 _F3 MD_ FER R_F R_C H1_ MD_ PER R_F R_C H1_ MD_ UNE X_F R_C H1_ MD_ NO_ FR_ CH1 _F2 MD_ FER R_F R_C H1_ MD_ PER R_F R_C H1_ MD_ UNE X_F R_C H1_ MD_ NO_ FR_ CH1 _F1 MD_ FER R_F R_C H1_ MD_ PER R_F R_C H1_ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C Bit Description MD_UNEX_FR_CH1_F4 : Manchester Decoder unexpected frame received 0b0: no unexpected frame received 0b1: unexpected frame received MD_NO_FR_CH1_F4 : Manchester Decoder no frame received (clear on read) 0b0: frame received (in expected time slot) 0b1: no frame received (in expected time slot) MD_FERR_FR_CH1_F4 : Manchester Decoder frame error status latch (clear on read) 0b0: no frame error seen 0b1: frame error detected MD_PERR_FR_CH1_F4 : Manchester Decoder Parity/CRC error status latch (clear on read) 0b0: no parity/CRC error seen 0b1: parity/CRC error detected MD_UNEX_FR_CH1_F3 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH1_F3 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH1_F3 : see MD_PERR_FR_CH1_F4 MD_UNEX_FR_CH1_F2 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH1_F2 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH1_F2 : see MD_PERR_FR_CH1_F4 MD_UNEX_FR_CH1_F1 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH1_F1 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH1_F1 : see MD_PERR_FR_CH1_F4 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.3-5: Register ERROR_STATUS_4 (0x28) Four error bits per frame (5-6) channel 1 and analog errors MSB LSB Content - - SYN C_D ATA _INV _CH REV _CU R_C BUF F_E RR_ CH1 OC_ CH1 DIAG_CH1 [1:0] MD_ UNE X_F R_C H1_ MD_ NO_ FR_ CH1 _F6 MD_ FER R_F R_C H1_ MD_ PER R_F R_C H1_ MD_ UNE X_F R_C H1_ MD_ NO_ FR_ CH1 _F5 MD_ FER R_F R_C H1_ MD_ PER R_F R_C H1_ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C Bit Description SYNC_DATA_INV_CH1 : SYNC trigger versus slot counter of channel 1 0b0: no SYNC pulse trigger during active Tx_LEN counter 0b1: SYNC pulse trigger during active Tx_LEN counter occurred REV_CUR_CH1 : Reverse current status of channel 1 0b0: no reverse current detected 0b1: reverse current detected BUFF_ERR_CH1 : Data buffer (96bit) configuration error 0b0: no configuration error 0b1: configuration error OC_CH1 : Channel 1 over current status 0b0: no over current 0b1: over current DIAG_CH1[1:0] : Channel 1 diagnosis status code (clear on read) 0b00: no error 0b01 leakage to GND 0b10: leakage to VBAT (soft short) / open load MD_UNEX_FR_CH1_F6 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH1_F6 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH1_F6 : see MD_PERR_FR_CH1_F4 MD_UNEX_FR_CH1_F5 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH1_F5 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH1_F5 : see MD_PERR_FR_CH1_F4 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.3-6: Register ERROR_STATUS_5 (0x29) Four error bits per frame (1-4)channel 2 MSB LSB Content MD_ UNE X_F R_C H2_ MD_ NO_ FR_ CH2 _F4 MD_ FER R_F R_C H2_ MD_ PER R_F R_C H2_ MD_ UNE X_F R_C H2_ MD_ NO_ FR_ CH2 _F3 MD_ FER R_F R_C H2_ MD_ PER R_F R_C H2_ MD_ UNE X_F R_C H2_ MD_ NO_ FR_ CH2 _F2 MD_ FER R_F R_C H2_ MD_ PER R_F R_C H2_ MD_ UNE X_F R_C H2_ MD_ NO_ FR_ CH2 _F1 MD_ FER R_F R_C H2_ MD_ PER R_F R_C H2_ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C Bit Description MD_UNEX_FR_CH2_F4 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH2_F4 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH2_F4 : see MD_PERR_FR_CH1_F4 MD_UNEX_FR_CH2_F3 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH2_F3 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH2_F3 : see MD_PERR_FR_CH1_F4 MD_UNEX_FR_CH2_F2 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH2_F2 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH2_F2 : see MD_PERR_FR_CH1_F4 MD_UNEX_FR_CH2_F1 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH2_F1 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH2_F1 : see MD_PERR_FR_CH1_F4 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.3-7: Register ERROR_STATUS_6 (0x2A) Four error bits per frame (5-6)channel 2 and analog errors MSB LSB Content - - SYN C_D AC_I NV_ CH2 REV _CU R_C BUF- FER _ER R_C OC_ CH2 DIAG_CH2 [1:0] MD_ UNE X_F R_C H2_ MD_ NO_ FR_ CH2 _F6 MD_ FER R_F R_C H2_ MD_ PER R_F R_C H2_ MD_ UNE X_F R_C H2_ MD_ NO_ FR_ CH2 _F5 MD_ FER R_F R_C H2_ MD_ PER R_F R_C H2_ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C Bit Description SYNC_DAC_INV_CH2 : SYNC trigger versus slot counter of channel 2 0b0: no SYNC pulse trigger during active Tx_LEN counter 0b1: SYNC pulse trigger during active Tx_LEN counter occurred REV_CUR_CH2 : Reverse current status of channel 2 0b0: no reverse current detected 0b1: reverse current detected BUFFER_ERR_CH2 : Data buffer (96bit) configuration error 0b0: no configuration error 0b1: configuration error OC_CH2 : Channel 2 over current status 0b0: no over current 0b1: over current DIAG_CH2[1:0] : Channel 1 diagnosis status code (clear on read) 0b00: no error 0b01 leakage to GND 0b10: leakage to VBAT (soft short) / open load MD_UNEX_FR_CH2_F6 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH2_F6 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH2_F5 : see MD_PERR_FR_CH1_F4 MD_UNEX_FR_CH2_F5 : see MD_UNEX_FR_CH1_F4 MD_FERR_FR_CH2_F5 : see MD_FERR_FR_CH1_F4 MD_PERR_FR_CH2_F5 : see MD_PERR_FR_CH1_F4

6.2.6.4 Diagnosis Registers

There are 8 (read only, R) registers available for diagnosis purposes. Following diagnosis informations are available:

• Voltages VDD,VBUS,VSYNC,VDD_INT
• Voltages SIFX Table 6.2.6.4-1: Diagnosis register Register Name Address Description DIAGNOSIS_ADC_ 1_2 0x2F ADC data:VDD,VDD_INT DIAGNOSIS_ADC_ 3_4 0x30 ADC data:VSIF2,VSIF1 n/a 0x31 n/a Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Register Name Address Description DIAGNOSIS_ADC_ 7_8 0x32 ADC data:VSYNC,VBUS DIAGNOSIS_ADC_ 9_10 0x33 ADC data:VCP_GATE Reading of unused bits will always return '0' and writing of unused bits don't care. Writing to read only or read on clear registers don't care. The SPI echo response to a write request is independently of register type (R/W, R, RC). Table 6.2.6.4-2: Register DIAGNOSIS_ADC_1_2 (0x2F) ADC data:VDD,VDD_INT MSB LSB Content ADC_DATA_2[7:0] ADC_DATA_1[7:0] Reset value 0 0 Access R R Bit Description ADC_DATA_2[7:0] : ADC data Voltage level VDD_INT ADC_DATA_1[7:0] : ADC data Voltage level VDD Table 6.2.6.4-3: Register DIAGNOSIS_ADC_3_4 (0x30) ADC data:VSIF2,VSIF1 MSB LSB Content ADC_DATA_4[7:0] ADC_DATA_3[7:0] Reset value 0 0 Access R R Bit Description ADC_DATA_4[7:0] : ADC data Voltage level VSIF2 ADC_DATA_3[7:0] : ADC data Voltage level VSIF1 Table 6.2.6.4-4: Register n/a (0x31) n/a MSB LSB Content - - Reset value 0 0 Access R R Bit Description Table 6.2.6.4-5: Register DIAGNOSIS_ADC_7_8 (0x32) ADC data:VSYNC,VBUS MSB LSB Content ADC_DATA_8[7:0] ADC_DATA_7[7:0] Reset value 0 0 Access R R Bit Description ADC_DATA_8[7:0] : ADC data Voltage level VSYNC ADC_DATA_7[7:0] : ADC data Voltage level VBUS Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Table 6.2.6.4-6: Register DIAGNOSIS_ADC_9_10 (0x33) ADC data:VCP_GATE MSB LSB Content - - - - - - - - ADC_DATA_9[7:0] Reset value 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R Bit Description ADC_DATA_9[7:0] : ADC data Voltage level VCP_GATE Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

7 Package Information

7.1 QFN20L5

The E521.40 is available in a Pb free, RoHs compliant QFN20L5 plastic package according to JEDEC MO-220 K, variant VHHC-2. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a soldering peak temperature of (260+5) ° C. Description Symbol mm inch min typ max min typ max Thickness of terminal leads, including lead finish A3 -- 0.20 REF -- -- 0.0079 REF -- Package length / width D / E -- 5.00 BSC -- -- 0.197 BSC -- Lead pitch e -- 0.65 BSC -- -- 0.026 BSC -- Number of terminal positions N 20 20 Note: the mm values are valid, the inch values contains rounding errors Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

7.2 SOIC20

The E521.40 is available in a Pb free, RoHs compliant SOIC20 plastic package according to JEDEC MS-013-E , variant AC . The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a soldering peak temperature of (260+5)° C. Description Symbol mm inch min typ max min typ max Package height A -- -- 2.65 -- -- 0.104 Stand off A1 0.10 -- 0.30 0.004 -- 0.012 Package body thickness A2 2.05 -- -- 0.081 -- -- Width of terminal leads, inclusive lead finish b 0.31 -- 0.51 0.012 -- 0.020 Thickness of terminal leads, inclusive lead finish c 0.20 -- 0.33 0.008 -- 0.013 Package length D 12.80 BSC 0.504 BSC Package width E 10.30 BSC 0.406 BSC Package body width E1 7.50 BSC 0.295 BSC Lead pitch e 1.27 BSC 0.050 BSC Length of terminal for soldering to substrate L 0.4 -- 1.27 0.016 -- 0.050 body chamfer (45° ) h 0.25 -- 0.75 0.010 -- 0.030 Angle of lead mounting area phi [° ] 0 -- 8 0 -- 8 mold release angle phi1 [° ] 5 -- 15 5 -- 15 Number of terminal positions N 20 20 Note: the mm values are valid, the inch values contains rounding errors Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 WARNING – Life Support Applications Policy Elmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor AG products, to observe standards of safety, and to avoid situations in which malfunction or failure of an Elmos Semiconductor AG Product could cause loss of human life, body injury or damage to property. In the development of your design, please ensure that Elmos Semiconductor AG products are used within specified operating ranges as set forth in the most recent product specifications. General Disclaimer Information furnished by Elmos Semiconductor AG is believed to be accurate and reliable. However, no responsib- ility is assumed by Elmos Semiconductor AG for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Elmos Semiconductor AG. Elmos Semiconductor AG reserves the right to make changes to this document or the products contained therein without prior notice, to improve performance, reliability, or manufacturability. Application Disclaimer Circuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of Elmos Semiconductor AG or others. Contact Information Headquarters Elmos Semiconductor AG Heinrich-Hertz-Str. 1 • D-44227 Dortmund (Germany) ℡: +492317549100 /envelopeback: sales-germany@elmos.com /globe1: www.elmos.com Sales and Application Support Office North America Elmos NA. Inc.

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2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016

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Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04

2 Channel Multi-Mode PSI5 Transceiver E 521.40 Production Data – Apr 27, 2016 Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Elmos Semiconductor AG Data Sheet QM-No.: 25DS0110E.04