E38E70DC

F38E70 FAIRCHILD | Alldatasheet

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a feel F. FAIRCHILD 38E70 : . a Single-Chip Microcomputer A Schlumberger Company Microprocessor Product Microprocessor Product Description Connection Diagram 40-Pin DIP The Fairchild single-chip microcomputer series offers a variety of circuits for the high-volume, cost-sensitive amu Cf oD vee markets. The F38E70 is a complete 8-bit microcomputer xu C2 os Faeser on a single MOS integrated circuit. The F38E70 is wf xe functionally identical to the F3870, except the F38E70 — HH ex wr has 2K bytes of EPROM in place of 2K bytes of ROM. as) 4 a7 Fioimy The F38E70 can execute the F8 instruction set of more ms a6 Fim than 70 commands. The device features 2048 bytes of Ps = EPROM, 64 bytes of scratchpad RAM, a programmable q* 35 FT Piaite binary timer, 32 bits of /O, and a single +5 V power Sraowe (] 7 PD Fine supply requirement mae am 4 | mm, x Utilizing Fairchild’s double-ion-implant, N-channel ™Oe i aie technology and advanced circuit design techniques, the paw 31) Pe single-chip F38E70 offers maximum cost-effectiveness in Fn 0% many low-to-medium volume systems. When production a Ge aly volume requires large quantities, the transition to the _ _ mask-programmed F3870 is very straightforward, with no Pas (hn 20h) Ps circuit design changes. Pas C]14 27) Ps Par C) 1s 267) Pe * Single-Chip Microcomputer & = * Software-Compatible with F8 Family oe 25h] Pirrest 2 + 2048-Byte EPROM (F38E70-2) ‘ate C17 2417] FieiPwOG * 64-Byte Scratchpad RAM Asis C} 10 231] Fiske * 32-Bit (4-Port) TTL-Compatible /0 w i. * Programmable Binary Timer mre C0 22h] Pray Interval Timer Mode ono [] 20 21 [7] Test wee Pulse Width Measurement Mode Teves Event Counter Mode ad * External Interrupt - * Crystal, LC, RC, External, or Internal Time Base F38E70 Architecture + Low Power (375 mW Typical) * Single +5 V + 10% Power Supply + Simple EPROM Programming [_voronto Pin Names P0,-P0, Bidirectional 1/0 Port O/Address* | Pip-Pi, Bidirectional /O Port 1/Address* Pap-Pa, Bidirectional /O Port 4/Data Out® ll P5o-P5, Bidirectional /O Port 5/Data In* rests fe rasraeovencer] STROBE Ready Strobe Output EXT INT External Interrupt Input RESET [ POWER ON RESET | RESET External Reset Input amy TEST 1/Vpp_ Test Line/PROG Voltage Input wm, SPL_Socctoae_] XTLy, XTLy Time Base Input Vec. GND Power Supply Lines we “aa shown In tha connection dlagtam, some port © and port 1 pins are ern address inputs for programming the Fa8E70 EPROM section. Ports 4 Veo and 5, Data Out and In, reter to the programming and test modes. eNO: [woronrs ] Caution: applying +25 V to the Vpp pin without the presence of Voc STROBE SS 4-47

Signal Functions bits are an immediate register address or an immediate 4-bit operand. Once latched into the IR, the main control exrint. — logic decodes the instruction and provides the necessary a reset control gating signals to all circuit elements. CONTROL x tests od a EPROM Address Registers amy a There are four 11-bit registers associated with the 2K x 8 ctock { wy ® | voronr EPROM. These are the program counter (P0), the stack le» 65, | ADDRESS register (P), the data counter (DC), and the auxiliary data Vee iy counter (DC1). The program counter is used to address power | ono Fe instructions or immediate operands. The stack register is es used to save the contents of PO during an interrupt or subroutine cell. Thus, P contains the return address at Fis which processing is to resume upon completion of the a subroutine or the interrupt routine. iz fs | vorort The data counter (DC) is used to address data tables. Fy | SUADORESS This register is auto-incrementing. Of the two data Fis counters, only DC can access the EPROM. However, the <> Fa XDC instruction allows DC and DC1 to be exchanged. Fir Associated with the address registers is an 11-bit adder! Fy incrementer. This logic element is used to increment PO i, or DC when required, and is also used to add Fi displacements to PO on relative branches or to add the | vorort accumulator contents to DC1 with the ADC (add data Fay { ADATA OUT counter) instruction. Pig Fi 2048 x 8 EPROM Pay The microcomputer program and data constants are _ stored in the program EPROM. When an EPROM access Fe is required, the appropriate address register (PO or DC) is Fy gated onto the EPROM address bus and the EPROM Fe output is gated onto the main data bus. The first byte in | woront the EPROM is location zero. 5a | SDATAIN Ld Scratchpad and ISAR ad The scratchpad provides 64 8-bit registers that may be bad used as general-purpose read/write data memory. The indirect scratchpad address register (ISAR) is a 6-bit a register used to address the 64 registers. All 64 registers may be accessed using ISAR. In addition, the lower order Device Organization 12 registers may also be directly addressed. This section describes the basic functional elements of The ISAR can be visualized as holding two octal digits. the F38E70 as shown in Figure 1. This division of ISAR is important, since a number of instructions increment or decrement only the least Main Control Logic significant three bits of ISAR when referencing The instruction register (IR) receives the operation code scratchpad bytes via ISAR. This makes it easy to (OP code) of the instruction to be executed from the reference a buffer consisting of up to eight contiguous program EPROM via the data bus. During all OP code scratchpad bytes. For example, when the low-order octal fetches, eight bits are latched into the IR. Some digit is incremented or decremented, ISAR is instructions are completely specified by the upper four incremented from 27g to 203 or is decremented from 20g bits of the OP code. In those instructions, the lower four to 27s. This feature of the ISAR is very useful in many SS 4-48

Fig. 1 Block Diagram — 'x-0 poet) {_rmen_ ed mou bY Te. sooness Twrennorr 2,06, ct -— mu N ee ae N ——e en N. 4 st Bas ADORESS — Ny = ase naaisren SS---- oA Sh --. = Figarsr ft s pea irr ERT TTOR SS ene srarus = ris aisven J rere a [UF = Pas Kyamnarert. — cay oH SS grom—1 — = ee nonannen nnn n-=- Paes coe = ee SS ES a ee eee Pin Functions PinName | Type | Description PO,-PO, | Input/Output | Thirty-two lines that can be individually used as either TTL-compatible inputs or as latched Pig-Pi, outputs. For EPROM programming, 11 lines of ports 0 and 1 are used as address inputs Pao-Pa, and one line of port 1 is a program control. Port § is EPROM data input, and port 4 is P5o-P5, EPROM output for verification. STROBE This pin, which is normally HIGH, provides a single LOW pulse after valid data is present ‘on the P4,-P4 pins during an output instruction. RESET RESET may be used to externally reset the F38E70. When pulled LOW, the F38E70 resets. When then allowed to go HIGH, the F38E70 begins program execution at the program location H ‘0000’. RESET is held LOW during EPROM programming. EXT INT The external interrupt input. Its active state is software-programmable. This input is also used in conjunction with the timer for pulse width measurement and event counting. XTLy, XTLy The time base inputs to which a crystal (1 to 4 MH2), LC network, RG network, or an external single-phase clock may be connected. If timing is not critical, the F38E70 operates from its internal oscillator with no external components. TEST 1Vpp | Input An input used only in testing and programming the F38E70. For normal circuit functionality, this pin is left unconnected or may be grounded. For EPROM programming, the test pin is connected to the programming voltage (typically 23 V). P1,TEST2| Input __| 1/0 during normal operation; must be HIGH when in verify mode Veo Voc is the power supply input (+5 V * 10%). Se en 449

a program sequences. All six bits of ISAR may be loaded Summary of Status Bits at one time, or either half may be loaded independently. OVERFLOW= CARRY, © GARRY, Scratchpad registers 9 through 15 (decimal) are given ZERO = ALU; A ALU, A ALUs A ALU, A mnemonic names (J, H, K, and Q) because of special ALU, A ALU, A ALU, A ALU, linkages between these registers and other registers, CARRY — =CARRY, such as a stack register. These special linkages facilitate SIGN _ A, the implementation of multi-level interrupts and eae subroutine nesting. For example, the instruction LR K, P . stores the lower eight bits of the stack register into Ieterrupt Control baal eo be used to ae upper or kU least significant bits of register control port (ICP). If the ICB is set and the F38E70 2 } interrupt logic communicates an interrupt request to the CPU section, the interrupt is acknowledged and Arithmetic and Logic Unit (ALU y ‘ After recelving Lople Unit a) the main control logic, processed upon completion of the first non-privileged Me Decree The required arithmetic or logic instruction. If the ICB is cleared, an interrupt operations (using the data presented on the two input request is not acknowledged or processed until the ICB busses) and provides the result on the result bus. The 's set again. arithmetic operations that can be performed in the ALU vo Ports are binary add, decimal adjust, add with carry, , . Georemert, and increment. The logic operations that can The F38E70 provides four complete bidirectional input! seeretonted are AND, OR, excluslveOR, ones output ports: these are ports 0, 1, 4, and 5. An output complement, shift right, and shift left. Besides providing inerweron oe or ours) causes the contents of the the result on the result bus, the ALU also provides four 0 be latched into the addressed port. An input cierie teprosenting the status of the reeult These instruction (IN or INS) transfers the contents of the signals, stored in the status register (W), represent the port to the ACC (port 6 is an exception, which is sone, OVERFLOW, SIGN, and ZERO condition of the described later). The VO buffers on the F38E70 are Caen cl theceeratien. logically inverted. The schematic of an I/O port is shown : in Figure 2. Accumulator , . . The accumulator (ACC) is the principal register for data An output ready strobe is associated with port 4. This manipulation within the F38E70. The ACC serves as one flag may be used to signal a peripheral device that the input to the ALU for arithmetic or logical operations, The aera ee rd cinale ton eulge’ sho ciyatter results of ALU operations are stored back into the ACC. the cutput operation Ia completed, so either edge may be used to signal the peripheral. The STROBE signal may Status Register ° : . also be used to request new input information from a I The status register (W) holds five status flags, as follows: peripheral simply by doing a dummy output of H00' to ee Ts port 4 after completing the input operation HEEEBE STATUS REGISTER (™) Timer and Interrupt Control Port The timer is an 8-bit binary down counter that is software-programmable to operate in one of three modes: sion the interval timer mode, the pulse width measurement canny mode, or the event counter mode (the timer characteristics are described in Table 1). As shown in ZERO Figure 3, associated with the timer are an 8-bit register ovenriow called the interrupt control port, a programmable prescaler, and an 8-bit modulo-N register; Figure 4 SHTERRUPT CONTROL BIT illustrates the timer/interrupt function. el 4-50

Fig. 2 /0 Port Diagram Vee g | oureur

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i | C . | E Veo exove, tne STANDARD The STROBE output is always configured similar to @ standard output, except that it's capable of driving three TTL loads, Fig. 3 Timer and Interrupt Control Port Block Diagram PRESCALER ™ TER EXTERNAL 6 cLock | err powN COUNTER INTERRUPT Tie BASE peoples neQuEST +2,5.10,20 40,100,020 taToH wODULO.N i REGISTER wr eBiTs ‘REO InTennuer CONTROL PORT ‘ome Toe eT ee ortho, Seencscate 3 ot TEPRESCALE S88 TIMER INTERRUPT ENABLE Tletpneson st Tiopnescate = St ot extwt TMoopnescate = et STARTISTOP TIMER iipnescae = ttt PULSE WIOTHINTERVAL TIMER See Figure 4 for a more detailed functional diagram SS 451

Table 1 Timer Characteristics Interrupt Control Port (Port 6) Somiigag Bit 0 — External Interrupt Enable Definitions ‘ Error= indicated time value — actual time value Bit 1 — Timer Interrupt Enable tpsea tex prescale value Bit 2 — EXT INT Active Level Bit 3 — Start/Stop Timer Interval Timer Mode Bit 4 — Pulse Width/interval Timer Single interval error, free-running (note 3) £6t6 Bit 5 — +2 Timer Prescale Values Cumulative interval error, free-running (note 3) 9 —_—=BIt B — +5 Timer Prescale Values Error between two timer reads (note 2) + (tpsc+ te) Bit 7 — +20 Timer Prescale Values sera. Stop timer error ‘toto = (tpse+t) A special situation exists when reading the interrupt eo tsimer to read timer error control port (with an IN or INS instruction). The ‘notes 1-2) ~ 5t to = (tpse+ 714) accumulator is not loaded with the content of the ICP; deter nar to interrupt request error instead, accumulator bits 0 through 6 are loaded with 0s, ‘notes 1.2) ~2teto ~8te while bit 7 is loaded with the logic level being applied to ne imor to stop timer error the EXT INT pin, thus allowing the status of EXT INT to rote 1) 16 to —(tpac+ 206) be determined without the necessity of servicing an ot ier to read timer error external interrupt request. This capability is useful in ous see ee establishing a high-speed polled handshake procedure or ned imer to interrupt request error for using EXT INT as an extra input pin if external (notes 1,3) = 2te to 96 interrupts are not required and the timer is used only in p the interval timer mode, rae aitont acer (n ain 4 toto —(tpse-+ 2te) The rate at which the timer is clocked in the interval Mitsu wutse width of EXTINT pin aed timer mode is determined by the frequency of an internal 6 clock and by the division value selected for the prescaler. (The internal ¢ clock operates at one-half the Sane of EXTINTpin 2to extemal time base frequency) I IGP bit 51 sot and bite active tim ' and 7 are cleared, the prescaler divides by two. _Minimum inactivetime of EXTINT pin 2 Likewise, if bit 6 or 7 is individually set, the prescaler Notes divides 6 by 5 or 20, respectively. Combinations of bits 5, 1. All times that ental! loading, starting, or stopping the timer are 6, and 7 may also be selected, For example, if bits 5 and Ses ae etc ine end of the last machine cycle of the OUT or 7 are set while 6 is cleared, the prescaler divides by 40. 2 QUTSinauc sng th ier rlroced rom he ona ot -_—-‘THUS, Possible prescaler values are +2, ~6, +10, = 20, items aneaeyce ot te I orINS inaction, +40, +100, and + 200. ‘3. All times that ental! the generation of an intarupt request are feferanced trom the start of the machine cycle in which the Any of three conditions causes the prescaler to be reset: Ot eeuest ote ane srinepedor multhayote elapse if when the timer is stopped by clearing the ICP bit 3, on {he Interur execution of an output instruction to port 7 (the timer is roe ce cumulative it operation i repetitively performed. assigned port address 7), or on the trailing edge transition of the EXT INT pin when in the pulse width measurement mode. These last two conditions are explained in more detail below. ‘The desired timer mode, prescale value, starting and stopping the timer, active level of EXT INT pin, and local ‘An OUT or OUTS instruction to port 7 loads the content enabling or disabling of interrupts are selected by of the accumulator to both the timer and the 8-bit outputting the proper bit configuration from the modulo-N register, resets the prescaler, and clears any accumulator to the interrupt control port (port 6) with an previously stored timer interrupt request. As previously OUT or OUTS instruction. Bits within the interrupt noted, the timer is an 8-bit down counter that is clocked control port are defined as follows: by the prescaler in the interval timer mode and in the pulse width measurement mode. The prescaler is not used in the event counter mode. The modulo-N register is a buffer whose function is to save the value that was most recently output to port 7. The modulo-N register is used in all three timer modes. el 452

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a Interval Timer Mode—When ICP bit 4 is cleared (logic 0) again set. Recall, however, that the prescaler is reset and at least one prescale bit is set, the timer operates in whenever the timer is stopped; thus, a series of starting the interval timer mode. When bit 3 of the ICP is set, the and stopping results in a cumulative truncation error, timer starts counting down from the modulo-N value. After counting down to H ‘01’, the timer returns to the A summary of other timer errors is given in the timing modulo-N value at the next count. On the transition from section, For a free-running timer in the interval timer H ‘01' to H‘N’, the timer sets a timer interrupt request mode, the time interval between any two interrupt latch, Note that the interrupt request latch is set by the requests may be in error by +6 ¢ clock periods, although transition of H ‘N’ in the timer, thus allowing a full 266 the cumulative error over many intervals is zero. The counts if the modulo-N register is preset to H ‘00’. If bit 1 prescaler and timer generate precise intervals for setting of the ICP is set, the interrupt request is passed on to the timer interrupt request latch, but the time-out may the CPU section of the F38E70. However, if bit 1 of the occur at any time within a machine cycle. (There are two ICP is a logic 0, the interrupt request is not passed on to types of machine cycles: short cycles, which consist of 4 the CPU section but the interrupt request latch remains @ clock periods, and long cycles, which consist of 6 ¢ set. If ICP bit 1 is subsequently set, the interrupt request clock periods.) In the multi-chip F8 family, there is a is then passed on to the CPU section. (Recall from the signal called the write clock that corresponds to a discussion of the status register interrupt control bit that machine cycle. Interrupt requests are synchronized with the interrupt request is acknowledged by the CPU the internal write clock, thus giving rise to the possible section only if ICB is set.) Only two events can reset the 6 ¢ error. Additional errors may arise due to the timer interrupt request latch: when the timer interrupt interrupt request occurring while a privileged instruction request is acknowledged by the CPU section, or when a or multi-cycle instruction is being executed. new load of the modulo-N register is performed. Nevertheless, for most applications all of the above errors are negligible, especially if the desired time Consider an example in which the modulo-N register is interval is greater than 1 ms. loaded with H ‘64’ (decimal 100). The timer interrupt request latch is set at the 100th count following the Pulse Width Measurement Mode—When ICP bit 4 is set timer start, and the timer interrupt request latch is (logic 1) and at least one prescale bit is set, the timer repeatedly set on precise 100-count intervals. If the operates in the pulse width measurement mode. This prescaler is set at + 40, the timer interrupt request latch mode is used for accurately measuring the duration of a is set every 4000 ¢ clock periods. For a 2 MHz ¢ clock pulse applied to the EXT INT pin. The timer is stopped (4 MHz time base frequency), this produces 2 ms and the prescaler is reset whenever EXT INT is at its intervals. inactive level. The active level of EXT INT is defined by The range of possible intervals is from 2 to 51,200 ICP bit 2: if cleared, EXT INT is active LOW; if set, EXT ° INT is active high. If ICP bit 3 is set, the prescaler and clock periods (1 4s to 25.6 ms for a 2 MHz ¢ clock). n However, approximately 50 periods is a practical timer start counting when EXT INT transitions to the ow ‘i level. When EXT INT returns to the inactive level, minimum because the time between setting the interrupt active H Jevel, request latch and the execution of the first instruction of tne timer stape, the prenodler reset ake the interrupt service routine is at least 29 ¢ periods (the Se eae ta cre not la (one en response time is dependent upon how many privileged top inte errs. orbitis mot eat) are not latched if the instructions are encountered when the request occurs). interrupt enable bit Is not set.) To establish time intervals greater than 51,200 ¢ clock As in the interval timer mode, the timer may be read at periods is simply a matter of using the timer interrupt . any time and may be stopped at any time by clearing ICP service routine to count the number of interrupts, saving “ 4 : bit 3; the prescaler and ICP bit 1 function as previously the result in one or more of the scratchpad registers Cetcrtbed end the timer stilt a bit bing until the desired interval is achieved. With this Sewn counter with the timer Interrupt request atch ee a a aloe, Interval, or several time being set on the timer transition from H ‘01’ to H'N’. . Note that the EXT INT pin has nothing to do with loading The timer may be read at any time and in any mode using the timer; its action is that of automatically starting and an input instruction (IN 7 or INS 7) and may take place stopping the timer and of generating external interrupts. “on-the-fly” without interfering with normal timer Pulse widths longer than the prescale value times the operation. Also, the timer may be stopped at any time by modulo-N value are easily measured by using the timer clearing bit 3 of the ICP. The timer holds its current interrupt service routine to store the number of timer contents indefinitely and resumes counting when bit 3 is, interrupts in one or more scratchpad registers. SS 4-54

As for accuracy, the actual pulse duration is typically interrupt control bit is set and the CPU section slightly longer than the measured value because the acknowledges the interrupt or the interrupt request is status of the prescaler is not readable and is reset cleared as previously described. when the timer is stopped. Thus, for maximum accuracy, it is advisable to use a small division setting for If there are both a timer interrupt request and an external the prescaler. interrupt request when the CPU section starts to process the requests, the timer interrupt is handled first Event Counter Mode—When ICP bit 4 is cleared and all prescale bits (ICP bits 5, 6, and 7) are cleared, the timer When an interrupt is allowed, the CPU section requests operates in the event counter mode. This mode is used that the interrupting element pass its interrupt vector for counting pulses applied to the EXT INT pin. If ICP bit address to the program counter via the data bus. The 3 is set, the timer decrements on each transition from vector address for a timer interrupt is H ‘020’. The vector the inactive level to the active level of the EXT INT pin. address for external interrupts is H ‘OA0’. After the vector The prescaler is not used in this mode, but, as in the address is passed to the program counter, the CPU ‘other two timer modes, the timer may be read at any section sends an acknowledge signal to the appropriate time and may be stopped at any time by clearing ICP bit interrupt request latch, which clears that latch, The 3; ICP bit 1 functions as previously described, and the execution of the interrupt service routine then timer interrupt request latch is set on the timer transition commences. The return address of the original program from H ‘01’ to H‘N’ is automatically saved in the stack register, P. Normally, ICP bit 0 should be kept cleared in the event Power-on Clear counter mode; otherwise, external interrupts are When power is applied to the F38E70, the program generated on the transition from the inactive level to the counter and the ICB bit of the status register are active level of the EXT INT pin. cleared. Ports 4, 5, 6, and 7 are loaded with H ‘00’ (thus, the /0 pins for ports 4 and 5 are at Voy). The contents of For the event counter mode, the minimum pulse width other registers and ports are undefined. The first required on EXT INT is 2 ¢ clock periods and the program instruction is then fetched from EPROM minimum inactive time is 2 ¢ clock periods; therefore, location H ‘000. the maximum repetition rate is 500 Hz. External Reset External Interrupts When RESET is taken LOW, the content of the program When the timer is in the interval timer mode, the EXT INT counter is pushed to the stack register, and the program pin is available for non-timer-related interrupts. If ICP bit counter and the ICB bit of the status register are then 0 is set, an external interrupt request latch is set when cleared, The original stack register content is lost. As there is a transition from the inactive level to the active with power-on clear, ports 4, 5, 6, and 7 are loaded level of EXT INT. (EXT INT is an edge-triggered input.) with H ‘00’. The contents of all other registers and The interrupt request is latched either until acknowleged ports are unchanged. When RESET is taken HIGH, the by the CPU section or until ICP bit 0 is cleared (unlike first program instruction is fetched from EPROM location timer interrupt requests, which remain latched even when H ‘000. ICP bit 1 is cleared). External interrupts are handled in the same fashion when the timer is in the pulse width Test Logic measurement mode or in the event counter mode, except Special test logic is implemented to allow access to the that only in the pulse width measurement mode is the internal main data bus for test purposes. external interrupt request latch set on the trailing edge of EXT INT, that is, on the transition from the active level In normal operation, the TEST pin is unconnected or is to the inactive level connected to GND. When TEST is placed at a TTL level (2.0 V to 2.6 V), port 4 becomes an output of the internal Interrupt Handling data bus and port 5 becomes a wired-OR input to the When either a timer or an external interrupt request is internal data bus. The data appearing on the port 4 pins communicated to the CPU section of the F38E76, it is is logically true, whereas input data forced on port 5 acknowledged and processed at the completion of the must be logically false. When TEST is placed at a HIGH first non-privileged instruction if the interrupt control bit level (6.0 V to 7.0 V), the ports act as above and, of the status register is set. If the interrupt control bit is additionally, the 2K x 8 program ROM is prevented from not set, the interrupt request continues until either the driving the data bus. In this mode, operands and SS 455

instructions may be forced externally through port § Fig. 5 Clock Configurations instead of being accessed from the program ROM. When TEST is in either the TTL state or the HIGH state, Crystal Mode External Mode STROBE ceases its normal function and becomes a cycle clock (identical to the F8 multi-chip system write clock, xcept inverted), Ee] Oo Timing complexities render the capabilities associated s aune with the TEST pin impractical for use in a user's srours~ aun onmnPeuoc application, but these capabilities are sufficient to enable Fairchild to implement a rapid method for thoroughly testing the F38E70. RC Mode Le Mode F38E70 Clocks Voc The time base for the F38E70 may originate in one of fe] four external sources. The four external configurations ® 4 L are shown in Figure 5. There is an internal 20 pF > + Coren, capacitor between XTL, and GND, and also between ® ore Le4e-4 XTLg and GND. Thus, external capacitors are not + cerremnas OPONAL) required. in all external clock modes, the external time ma base frequency is divided by two to form the internal Minimum R= 4ko Mininum Lad mH ¢ clock. Minimum Q= 40 instruction Set =205 pF 225 pF+Cexremnat Maximum Cecrepwat = 90 PF The F38E70 executes the entire instruction set of the tum # —t— cx t0pr213pF+6, multi-chip F8 family (F3850 family), as shown in Table 2. 1.1RC+65ns EXTERNAL Of course, the STORE instruction is of little use in the 1 1 F38E70 because only read-only memory exists in the wax” oRGe iene oe addressing range of the data counter (the data counter, however, is incremented if STORE is executed). Example with Cextennat =O Example with CextennaL=0 A=15 Kx 5% L203 ms 10% A summary of programmable registers and ports is given 1m 20MHzs 26% 1 = 3.0 MH22 10% in Figure 6, followed by a summary of the F38E70 (F8-compatible) instruction set. Also, for convenient reference, a programming model of the F38E70 is given in Figure 7. Hee eee el 4-56

a Table 2 F38E70 Instruction Set Table 2 FSSE7O Inatruction Set Accumulator Group Instructions Tomanie San Operation OP Code | ovF [Zeno [ony [sian Add Carry LNK ACC—(ACC)+ CRY 19 1 1 10} 10 0 110 Aad iorbaete i aed au | 2 | 2s | wl ae lie] te AND immediate a acenacey ne au} 2 | 38 | Ph ae] ete ‘Clear CLR ACC—H'00" 70 1 1 ‘Compare immediate cr Hiii'+ ACT) +9 25 ii 2 25 Ww} Ww | 1m | 10 Conpienen cu Roo Acoe FE ve | LY pte le lw Exclusive OR immediate xt ACC—{ACC)e Hii’ 23th 2 25 oO wo 0 10 Increment 1NC ACC—(ACC)+1 1F 1 1 10 110 vo 0 (teeta v pean av | 2 fa |e) eyel™ tees immedits Short us acento ele] | zpr dtc OR Immediate ol ACC~(ACC) V Hii" 2241 2 25 oO v0 oO 110 rit iat One A Perth a |i | | 8 fae ls [te St tat Peer SHETLEET« eta {a | sfwle fs Sri igh Gee i SHIFT Rigas e far ]a |efmleyt anit ign Pose a Siaet AGT & ew {ifs fede ds Branch Instructions (In All Conditional Branches, PO (P0)+ 2 if the Test Conditions Are Not Met. Execution Is Complete in 30 Cycles.) Theononie stats i Opecaton OF Code [ove [2eRo [oay [sian Tanah on Gory 0 PacWea Ts ee FORT tes sas = Branch on Positive BP PO-{(PO)+ 1]+ H’aa’ if SIGN=1 81 aa was" - Branch on Zero. ez PO—[(PO)+ 1}+ H’aa’ it ZERO=1 84 aa 35°" = Branch on True BT PO—[(PO) + 1]+ H’aa’ if any test is true Bt aa 38.5"* - t= TEST CONDITION [TT] [zeRo [nv [sen] Branch Negative ow po-(Poenewarnsan=0 | ores sas - Branch if No Carry BNC PO-[(PO) + 1] + H’aa’ if CARRY #0 92aa was"* - Branch if No Overflow BNO PO~[(PO)+ 1)+ H'aa’ if OVF =0 Baa was"? - Branch if Not Zero BNZ PO-[(PO)+ 1]+ H’aa’ if ZERO=0 94aa ws" = tn tTeeT conommon EARArnEs [ove |zeR0 [ony [son] Branch if ISAR (Lower) 7 ‘BRT PO~[(PO) + 1]+ H'aa’ if ISARL #7 ‘BF aa 25 - PO—(PO)+ 2 if SSARL=7 20 - branch Paine en Pocjpoe te nas om 3 : ine" Je Poctinase aoeesa 3s _ Memory Reference instructions (In All Memory Reference Instructions, the Data Counter Is incremented DC—DC+1.) Mnemonic Status Bits Operation OF Code [ove [zeKo [env [sion Add Binary AM ACC-—(ACC)+ [(0C)} iJ 10 170 110 10 Add Decimal AMD ACC—(ACC) + [(0C)} 8 v0 10 Ww | 10 ‘AND. NM ‘ACC—(ACC) A (0C)} 8A o | w]o | w Compare. cM [(OC)] + ACT) +1 8D 170 10 WoO wo Exclusive OR XM ACC~(ACC)e [(DC)]_ 8c oO wo oO 0 ised on soe pel ‘e o}eyeye Logical OR OM ACC (ACC) V (OC) 8B ° v0 0 10 Store st (DC)—(ACC) Ww = - = =~ Wot a 457

a Table 2 F38E70 Instruction Set (Cont.) Address Register Group Instructions Sia oe Operation [ovr [zERO [CRY [SIGR Add to Data Counter ‘ADC DC—({OC)+ (ACC) 8E 25 = Call to Subroutine PK* P—(PO}; POU—(r12); PL—(r13) oc 4 = Caltosuoutineimmedate | pr | eaaa | puipy PO-Hasant aaa és = Exchange DC x0C oc—oc1 2 2 - teed Data Counter Tr | ooo |peu-re oct 18) oF i = teed beta Counter tk | ben |pounnos oct—Wn) 0 i = te be Inertate oot | toca | Do rraaoa aaiaaa ‘ = {ad Program Counter tn | poo [pouty POL-(r8) ry ‘ = Load Stack Register uR PK PU—(r12); PL—(r13) 8 4 - Return From Subroutine PoP* PO-(P) 1c 2 - Store bata Courtr TR | apc Jne—cu; 5-(cty oe i = ‘Store Data Counter LR H.C 10—(OCU), 11—(DCL) Ww 4 _ Store Stack Register th | ke [necro & ‘ = ‘Scratchpad Register Instructions (Refer to Scratchpad Addressing Modes.) Status Bits: Operation cyclen | OVF [ZERO [CRY [SIGN Add Binary AS if ACC—(ACC)+ (0) cr 1 1 1} v0 | 0 | 10 fa Doct wo | + lacc-wocrs o | | 2 | wf ae [a0 | te Decement os | ot femener & | 3 | as | i] tw | to | io Load wR Ar ACC—(n) 4 1 1 - - - - teed th | anu [acon wo fafa jcpoqcyc teed th | ane [acomn3) es fa} a foto qcqc toad th | xo facoine ® {+ )a fsyofeyc Load RR AQL ACC —(r15) 03 1 1 - - _ = toed te | WA |eSacey e fad a pots qsyc toe ta | Kua frasaco & ft fa [ofl ycic Load LR KLA 113—(ACC) 05 1 1 - - - - teed tr | gua. |rectaces e |i fa fafsqtye Load LR LA 115—(ACC) or 1 1 - = - - AND ne | Or acoAce a me 1s] | olm]o | iw Exclusive OR xs id ACC~(ACC)@(r) er 1 1 oO 10 oO 110 Miscellaneous Instructions Tnemonie Stas Bie Operation ‘OP Code [OVF [ZERO [CRY [SIGN Diab erat 0 RESET CB onl a Enable Interrupt* e ‘SETICB 18 1 = = - - Input IN aa ‘ACC—(INPUT PORT aa) 26aa 2 ° v0 ° 170 Input Shon ws | 2 [aco-onpur Pont a ne | o |i | o | 1 Load ISAR un ISA ISAR—(ACC) 08 1 = = - _ Cond ISAR Lower us | SS [samc “e ono] 4 tli jofc Lond ISAR Upper tsy | a [teanune ovioos=| 4 tyro fats ‘Load Status Register" oR Ws W—(19) 10 1 w | 0 vo | ‘No-Operation NOP” PO-(PO)+ 1 2 1 - - - - Output OUT aa OUTPUT PORT aa—(ACC) 27aa 2 = - - _~ Output Short ouTs a OUTPUT PORT a—(ACC) Ba 1 - =- - - ‘Store ISAR uR AIS /ACC—(ISAR) 0A q - - - — Store Status Register ta | Sw_fe-w * da ={= ee “Prioged nstucton = tal it ***Two machine cycles for CPU ports +Contents of ACC destroyed a 458

Each lower case character represents a hexadecimal digit. J scratchpad register #9 Each cycle equals four machine clock periods. K registers #12 ana #13 Lower case denotes variables specified by the programmer. KL register #13 KU register #12 Function Detinitons PO program counter - is replaced by POL —_least significant eight bits of program counter () the contents of POU most significant eight bits of program counter (-) binary ones complement of P stack register + arithmetic add (binary or decimal) PL least significant eight bits of program counter © logical OR exclusive PU most significant eight bits of active stack register A logical AND Q registers #14 and #15 V__fogical OR inclusive QL register #15, HW hexadecimal digit QU register #14 ' ‘cratchpad register (any address through 11) Register Names W status register a address variable A accumulator ‘Scratchpad Addressing Modes (Machine Code Format) oc data counter (indirect address register) r=C (hexadecimal) register addressed by ISAR (unmodified) DCt data counter #1 (auxiliary data counter) 1=D (hexadecimal) register addressed by ISAR; ISARL incremented DCL least significant eight bits of data counter addressed T=E (hexadecimal) register addressed by ISAR; ISARL decremented DCU most significant eight bits of data counter addressed =F (90 operation performed) H”_scratchpad register #10 and #11 1=0-B (hexadecimal) register 0 through 11 addressed directly from the ‘and ii immediate operand instruction {CB interrupt contro! bit Is indirect scratchpad address register ‘Status Register ISAR indirect scratchpad address register - no change in condition ISARL least significant three bits of ISAR 110 _is set to 1 oF 0, depending on conditions ISARU most significant three bits of ISAR CRY carry flag EPROM Programming F38E70 Erasing Instructions When Vpp is applied to the TEST 1 pin, the device goes The contents of the F38E70 EPROM can be erased by into the program or verify mode and the 1/0 ports take on exposure to high-intensity shortwave ultraviolet (UV) light the different functions of DATA IN (port 5), DATA OUT with a wavelength of 2537 Angstroms (A). This can be (port 4), EPROM address (11 pins of ports 0 and 1), and accomplished with ultraviolet light EPROM erasure PROG (port 1g). The verify mode exists when PROG is devices that are available from several U.S. HIGH and TEST 2= Vcc. Port 4 outputs the data content manufacturers. These erasure devices contain a UV light of the EPROM according to the address Ag through Aig. source, which is usually placed approximately 1 or 2 The logical sense is true, and for an unprogrammed inches from the EPROM so that the transparent window location, the outputs are high. During verify mode, the on top of the device is illuminated. The minimum data on port 5 has no effect on the port 4 output. The required integrated dose (intensity x exposure time) program mode exists when PROG is taken low. All of UV light energy incident on the window of the addresses and DATA IN must be stable before going into device in order to reliably ensure complete erasure is this mode. During this mode, the data appearing on port 15 watt-secicm?, The UV erasure unit should be 5 is “burned in" to the EPROM. Note that the sense of periodicaily calibrated if minimum exposure times are to port 5 is logically false. At the same time, port 4 outputs be used. (Minimum exposure times range from 10 to 45 the data on the internal data bus, which is exactly equal minutes, depending on the model type and age of UV to the inversion of the data going in on port 5. Port 4 lamp,) If longer exposure times are possible, variations does not indicate satisfactory completion of the EPROM in the output light intensity of the UV light source are programming in the program mode. The PROG pin must not critical. be high before the Vpp is applied in order to prevent a pro- gramming error. CAUTION Applying Vpp to the TEST 1/Vpp pin without the presence Of Voc will damage the device. —— ey 459

Fig. 6 Programmable Registers and Ports 1 ° scomsen [| status evTe aooness abcisten w 7 SCRATCHPAD 9 DEG HEX oCT - - o 8 8 to 1 aa ; prota inoiRecT Senarcnpan SSonese t oo nearsren a A 4 s 8 ow Py wo A vx ota a! Sounren | ne 8 i” woe om i 9 Kw nooo os para a! “woe Counter | ow wor ow nr) 10 a De ‘STACK i] | . neoieren De | In oa on 10. 2 wo cy n PROGRAM bed bad ™ OuNTER now on e «x 7 oe ow 7 ? Q 1 ° many vo Pont 0 men ? 2 a font [wer] eee el 4-60

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a ‘Supplementary Notes For total software compatibility when expanding into a When an external reset of the F38E70 occurs, PO is multi-chip configuration, the F3871 Peripheral pushed into P and the old contents of P are lost. It must Input/Output circuit should be used. The F3871 has be noted that an external reset is recognized at the start the same improved timer (binary count, readable, and of the machine cycle and not necessarily at the end of three modes of operation) and ready strobe output as an instruction. Thus, if the F38E70 is executing a multi- the F38E70. cycle instruction, that instruction is not completed and the contents of P upon reset may not necessarily be the The interrupt control bit of the status register is address of the instruction that would have been automatically reset when an interrupt request is executed next. It may, for example, point to an acknowledged, It is then the programmer's responsibility immediate operand if the reset occurred during the to determine when ICB is again set (by executing an El second cycle of an LI or Cl instruction. Additionally, instruction). This action prevents an interrupt service ‘several instructions (JMP, PI, PK, LR, PO, Q) as well as routine from being interrupted unless the programmer the interrupt acknowledge sequence modify PO in parts. so desires. That is, they alter PO by loading first one part, then the other, and the entire operation takes more than one When reading the interrupt control port (port 6), bit 7 of cycle. Should reset occur during this modification the accumulator is loaded with the actual logic level process, the value pushed into P is part of the old PO being applied to the EXT INT pin, regardless of the (the as-yet unmodified part) and part of the new PO (the status of ICP bit 2 (the EXT INT active level bit); that is, if already modified part). Thus, care should be taken EXT INT is at +5 V, bit 7 of the accumulator is set to a (perhaps by external gating) to ensure that reset does not logic 1, but if EXT INT is at GND, accumulator bit 7 is occur at an undesirable time if any significance is to be reset to logic 0. given to the contents of P after a reset occurs. In the “F38E70 (F8-compatible) Instruction Set” Absolute Maximum Ratings summary, the number of cycles shown is “nominal” The absolute maximum ratings of the F38E70 are machine cycles. A nominal machine cycle is defined as 4 as follows: @ clock periods, thus requiring 2 us for a 2 MHz ¢ clock Temperature (Ambient Under Bias) orc, +70°C frequency (4 MHz external time base frequency). Storage Temperature — 55°C, + 150°C Voltage on any Pin with Respect to Also, the summary uses the following nomenclature for Ground (Except Test Pin) -1.0V, +7V register names: Test Pin Voltage with Respect to Vss_ =-1.0V, +27V Fe F38E70 CAUTION roee p coo Counter Applying Vpp to the TEST 1/Vpp pin without the presence += ack Register pp E pe 0 DG,=DC Data Counter Of Veg will damage the device. DC;=0C1 Auxiliary Data Counter. Power Dissipation 10W This nomenclature is used in order to be consistent with ‘These are stress catings ‘only, and Lira iprstante these ratings, or under any conditions abore those indicated in this data sheet, is not the assembly language mnemonics. Implied. Exposure tothe absolute maximum rating conditions for For the F38E70, execution of an INS or OUTS instruction caer pene an ese rated may cause pemaven damage to requires two machine cycles tor ports 0 and 1, while the device. ports 4 and 5 require four machine cycles, ES 462

Timing Characteristics Voc = +5 V + 10%, Ta=0°C to + 70°C Signal_| Symbol | ___Characteristic | Min [Max [Unit [Comments (Note 3) XTLy to(XTL) | Time Base Period, Crystal Mode | 250 | 5000 | ns | 4MHz-2 MHz XTLe to(LO) Time Base Period, LC Mode | 250 | 5000 | ns | 4MHz-2MHz to(RC) Time Base Period, RC Mode | 250 | S000 | ns | 4MHz-2MHz tolEX) | Time Base Period, External Mode _| 250 | 5000 | ns | 4MHz-2 MHz External Clock Pulse Width, High | 90 |i(EX)-100| ns | tex) External Clock Pulse Width, Low | 90 [t(Ex-100|_ns_| é [to | Internal @ Clock Period 2to typ. [ns [ 0.5ysat4 MHzext. time base STROBE Port Output to STROBE Delay 3t6— 1000 min Note 1 3tg + 250 max ts STROBE Pulse Width, Low 8td— 250 min 12t+ 250 max RESET | tay _| RESET Hold Time, Low 6tg+750min | ns | EXTINT | ten | EXTINTHold Time, Active State [6to+750min | ns | Note2 Notes 1. Load is 50 pF plus 1 standard TTL input. 2. Specification Is applicable when the timer isin the interval timer ‘mode. See “Timer Characteristics" for EXT INT requirements when in the pulse width measurement mode or the event counter mode. 3. The timing diagrams are given in Figure 8 Fig. 8 Timing Diagrams ‘en tex00 EXTERNAL tock te: fey etock vo pont OUTPUT x hos sTmowe ‘RESET vce err2=0 ent vor orra= Note ‘All measurements are referenced to Vi, max, Vin min, Vou MAX. OF Von min. SS 463

Symbol Parameter [Min] Max[Unit tserup [23 V Applied to PROG fs] [us tas ___ [Address Set-up Time [a] [us tan __ [Address Hold Time [a] [as tps _[Data Set-up Time [a] [as ton __ [Data Hold Time fa[ [as tav___ [Address to DataOutinverify | | 5 | us tev _ [PROG to Data Out in Verify | [2 [as tpo __ [PROG toDataOutinProgramming| | 5 | us. tprog [Programming Time [ 50 | 60 [ms Note Timing diagrams are given in Figure 9 a Fig. 9 Program/Verity Timing Diagrams nv vest chs ae ‘ —_— Pon) ( \\ wexr para POUR (ROD) toes wy ty “wens { 7, a, (oer two LS 4-64

OC Characteristics Voc =5 V + 10%, Ta=0°C to + 70°C Tco__| Power Supa Curent |__| 76 | 100 | ma | Supe Open Po | Power Desipaton | _[ 75 | —s80-[ mw | Outputs Open na | External Clock nput High Vatge | aa] | sa | v | Visuex | External Clock nput Low votage | -03| | 06 | v | inex | External Glo input High Curent [| | 100 [oA | Vag av (Except Open-Drain and Direct-Drive I/O Ports) (Except Open-Drain and Direct-Drive Ports) (Except Open-Drain and Direct-Drive Ports) lon] ouiputtow Curent] | | [ma | Varroa ious | Output Low Curent STROBE Outpu | 50 | [ma | Var=0av Veesr_| Tet Pin Votage for Progamventymose [29 | asl] v | Capacitance T,= 25°C, f=2 MHz Symbol | ____Characierate | win | wax [unt] Test Conaion Gn | Tapa Capactiance: vO Ports, RESET EXTINT | __[__7 | pF | Unmeasured pine returned GND Typical Thermal Resistance Values Plastic 8, (Junction to ambient) 60°C/W (still air) —Sialunctiontocase) 42°C Ceramic 6, (Junction to ambient) 48°CIW (still air) 8, (Junction to case) 33°Cw ee 465

—— ed F38E70 a

Ordering Information

PartNumber | Package | Temperature Range’ F38E70DC Ceramic c F38E700L Ceramic L F38E700M Ceramic M F38E70PC Plastic c F38E70PL Plastic L F38E70PM Plastic M *C= Commercial Temperature Range 0°C to + 70°C L= Limited Temperature Range 40°C to +85°C Mz Miltary Temperature Range — 55°C to + 125°C el 4-66