DTC501 FS | Alldatasheet
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Technical content
NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transi stors is designed to replace a s ingle device and its exter nal resistor bias network. The BRT (B ias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single de vice. The use of a BRT can reduce both system cost and board space. The device is housed in the SC-89 package which is designed for low power surface mount applications.
- Simplifies Circuit Design
- Reduces Board Space
- Reduces Component Count
- The SC-89 package can be soldered using wave or reflow. The modified gull-winged leads absorb thermal stress during soldering eliminating the possibility of damage to the die. SC-89 MAXIMUM RATINGS (TA = 25 C unless otherwise noted) THERMAL CHARACTERISTICS 1. F R–4 @ Minimum Pad 2. F R–4 @ 1.0 × 1.0 Inch Pad DEVICE MARKING AND ORDERING INFORMATION PIN 3 COLLECTOR (OUTPUT) PIN 2 EMITTER (GROUND) PIN 1 BASE (INPUT) 2008. 1. 28 1/3 SEMICONDUCTOR TECHNICAL DATA DTC501 Revision No : 0 Device Marking Shipping 3000/Tape&ReelDTC501T1G 8J 10000/Tape&ReelDTC501T3G 8J Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc Characteristic Symbol Max Unit Total Device Dissipation, FR–4 Board (Note 1.) @ TA = 25 C Derate above 25 C PD 200 1.6 mW mW/ C Thermal Resistance, Junction to Ambient (Note 1.) RθJA 600 C/W Total Device Dissipation, FR–4 Board (Note 2.) @ TA = 25 C Derate above 25 C PD 300 2.4 mW mW/ C Thermal Resistance, Junction to Ambient (Note 2.) RθJA 400 C/W Junction and Storage Temperature Range TJ, Tstg –55 to +150 C
- 1. 28 2/3 DTC501 Revision No : 0 ELECTRICAL CHARACTERISTICS (TA = 25 C unless otherwise noted) (Continued) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Collector-Base Cutoff Current (VCB = 50 V, IE = 0) ICBO – – 100 nAdc Collector-Emitter Cutoff Current (VCE = 50 V, IB = 0) ICEO – – 500 nAdc Emitter-Base Cutoff Current (VBE = 6.0 V) IEBO – – 1.5 mAdc Collector-Base Breakdown Voltage (IC = 10 µA, IE = 0) V(BR)CBO 50 – – Vdc Collector-Emitter Breakdown Voltage (Note 3) (IC = 2.0 mA, IB = 0) V(BR)CEO 50 – – Vdc ON CHARACTERISTICS (Note 3) DC Current Gain (VCE = 10 V, IC = 5.0 mA) hFE 15 – Collector-Emitter Saturation Voltage (IC = 10 mA, IB = 1 mA) VCE(sat) – – 0.25 Vdc VOL – – 0.2 Vdc 3. P ulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kΩ) Output Voltage (on) 3.3 R1/R2Resistor Ratio Input Resistor R1 kΩ (VCC = 5.0 V, VB= 0.25 V, RL= 1.0 kΩ) Output Voltage (off) VOH – Vdc4.9 0.8 1.0 1.2 4.7 6.1
G M0.08 (0.003) X D 3 PL J -X- -Y- NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14 5M, 1982
2 CONTROLLING DIMENSION: MILLIMETERS
3 MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL 4 463C-01 OBSOLETE, NEW STANDARD 463C-02 A B Y 1 2 N 2 PL K C -T- SEATING PLANE M HH L G RECOMMENDED PATTERN OF SOLDER PADS S SC-89 2008. 1. 28 3/3 DTC501 Revision No : 0 DIM A B C D G H J K L M N S MIN 1 50 0 75 0 60 0 23 0 10 0 30 1 50 NOM 1 60 0 85 0 70 0 28 0 50BSC 0 53RBF 0 15 0 40 1 10RBF 1 60 MAX 1 70 0 95 0 80 0 33 0 20 0 50 10˚ 10˚ 1 70 MIN 0 059 0 030 0 024 0 009 0 004 0 012 0 059 NOM 0 063 0 034 0 028 0 011 0 020BSC 0 021RBF 0 006 0 016 0 043RBF 0 063 MAX 0 067 0 040 0 031 0 013 0 008 0 020 10˚ 10˚ 0 067 MILLIMETERS INCHES