DTA114EET1 ONSEMI | Alldatasheet

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 Semiconductor Components Industries, LLC, 2000 May, 2000 – Rev. 0

1 Publication Order Number:

/C0068/C0084/C0065/C0049/C0049/C0052/C0069/C0069/C0084/C0049 /C0083/C0069/C0082/C0073/C0069/C0083 Preferred Devices /C0066/C0105/C0097/C0115 /C0082/C0101/C0115/C0105/C0115/C0116/C0111/C0114 /C0084/C0114/C0097/C0110/C0115/C0105/C0115/C0116/C0111/C0114 PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. The device is housed in the SC–75/SOT–416 package which is designed for low power surface mount applications.

  • Simplifies Circuit Design
  • Reduces Board Space
  • Reduces Component Count
  • The SC–75/SOT–416 package can be soldered using wave or reflow. The modified gull–winged leads absorb thermal stress during soldering eliminating the possibility of damage to the die.
  • Available in 8 mm, 7 inch/3000 Unit Tape & Reel MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc DEVICE MARKING AND RESISTOR VALUES Device Marking R1 (K) R2 (K) Shipping DTA114EET1 DTA124EET1 DTA144EET1 DTA114YET1 DTA114TET1 DTA143TET1 DTA123EET1 DTA143ZET1 DTA124XET1 DTA123JET1 4.7 2.2 4.7 2.2 2.2 3000/Tape & Reel http://onsemi.com CASE 463 SOT–416/SC–75 STYLE 1 Preferred devices are recommended choices for future use and best overall value. PNP SILICON BIAS RESISTOR TRANSISTORS COLLECTOR BASE EMITTER

http://onsemi.com THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Total Device Dissipation, FR–4 Board (1.) @ TA = 25°C Derate above 25°C PD 200 1.6 mW mW/ °C Thermal Resistance, Junction to Ambient (1.) R θJA 600 °C/W Total Device Dissipation, FR–4 Board (2.) @ TA = 25°C Derate above 25°C PD 300 2.4 mW mW/ °C Thermal Resistance, Junction to Ambient (2.) R θJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg –55 to +150 °C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Collector–Base Cutoff Current (VCB = 50 V, IE = 0) ICBO — — 100 nAdc Collector–Emitter Cutoff Current (VCE = 50 V, IB = 0) ICEO — — 500 nAdc Emitter–Base Cutoff Current DTA114EET1 (VEB = 6.0 V, IC = 0) DTA124EET1 DTA144EET1 DTA114YET1 DTA114TET1 DTA143TET1 DTA123EET1 DTA143ZET1 DTA124XET1 DTA123JET1 IEBO — 0.5 0.2 0.1 0.2 0.9 1.9 2.3 0.18 0.13 0.2 mAdc Collector–Base Breakdown Voltage (IC = 10 µA, IE = 0) V(BR)CBO 50 — — Vdc Collector–Emitter Breakdown Voltage (3.) (IC = 2.0 mA, IB = 0) V(BR)CEO 50 — — Vdc ON CHARACTERISTICS (3.) DC Current Gain DTA114EET1 (VCE = 10 V, IC = 5.0 mA) DTA124EET1 DTA144EET1 DTA114YET1 DTA114TET1 DTA143TET1 DTA123EET1 DTA143ZET1 DTA124XET1 DTA123JET1 hFE 35 160 160 8.0 100 140 140 250 250 140 130 140 Collector–Emitter Saturation Voltage (IC = 10 mA, IE = 0.3 mA) (IC = 10 mA, IB = 5 mA) DTA123EET1 (IC = 10 mA, IB = 1 mA) DTA114TET1/DTA143TET1/ DTA143ZET1/DTA124XET1 VCE(sat) — — 0.25 Vdc Output Voltage (on) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kΩ ) DTA114EET1 DTA124EET1 DTA114YET1 DTA114TET1 DTA143TET1 DTA123EET1 DTA143ZET1 DTA124XET1 DTA123JET1 CC = 5.0 V, VB = 3.5 V, RL = 1.0 kΩ ) DTA144EET1 VOL 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 Vdc 1. FR–4 @ Minimum Pad 2. FR–4 @ 1.0 × 1.0 Inch Pad 3. Pulse Test: Pulse Width < 300 µs, Duty Cycle < 2.0%

http://onsemi.com MINIMUM RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 1.4 0.5 min. (3x) 0.5 min. (3x) TYPICAL 0.5 SOLDERING PATTERN Unit: mm SOT–416/SC–75 POWER DISSIPATION The power dissipation of the SOT–416/SC–75 is a function of the pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T J(max), the maximum rated junction temperature of the die, RθJA , the thermal resistance from the device junction to ambient; and the operating temperature, T A . Using the values provided on the data sheet, PD can be calculated as follows: PD = TJ(max) – TA R θJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 200 milliwatts. PD = 150°C – 25°C = 200 milliwatts 600°C/W The 600°C/W assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 200 milliwatts. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad . Using a board material such as Thermal Clad, a higher power dissipation can be achieved using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

  • Always preheat the device.
  • The delta temperature between the preheat and soldering should be 100°C or less.*
  • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10°C.
  • The soldering temperature and time should not exceed 260°C for more than 10 seconds.
  • When shifting from preheating to soldering, the maximum temperature gradient should be 5°C or less.
  • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.
  • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

or stainless steel with a typical thickness of 0.008 inches. board, i.e., a 1:1 registration. being used. This profile shows temperature versus time. degrees cooler than the adjacent solder joints. Figure 24. Typical Solder Heating Profile

40 TO 80 SECONDS

http://onsemi.com PACKAGE DIMENSIONS SC–75 (SOT–416) CASE 463–01 ISSUE B DIM MIN MAX MIN MAX INCHESMILLIMETERS A 0.70 0.80 0.028 0.031 B 1.40 1.80 0.055 0.071 C 0.60 0.90 0.024 0.035 D 0.15 0.30 0.006 0.012 G 1.00 BSC 0.039 BSC J 0.10 0.25 0.004 0.010 K 1.45 1.75 0.057 0.069 L 0.10 0.20 0.004 0.008 S 0.50 BSC 0.020 BSC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. M0.20 (0.008) B –A– –B– S D G 3 PL 0.20 (0.008) AK J L C H STYLE 1: PIN 1. BASE 2. EMITTER 3. COLLECTOR STYLE 2: PIN 1. ANODE 2. N/C 3. CATHODE STYLE 3: PIN 1. ANODE 2. ANODE 3. CATHODE STYLE 4: PIN 1. CATHODE 2. CATHODE 3. ANODE

http://onsemi.com Notes

http://onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone : 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–asia@hibbertco.com JAPAN : ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone : 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. DTA114EET1/D Thermal Clad is a trademark of the Bergquist Company NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support German Phone : (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time) Email: ONlit–german@hibbertco.com French Phone : (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time) Email: ONlit–french@hibbertco.com English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland