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Technical content
Features
- Four low skew, low additive jitter LVDS output pairs
- Two selectable differential clock input pairs
- Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
- Maximum input clock frequency: 2GHz
- LVCMOS/LVTTL interface levels for the control input select pin
- Output skew: 20ps (maximum)
- Propagation delay: 300ps (maximum)
- Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 95fs (maximum)
- Full 2.5V supply voltage
- Lead-free (RoHS 6), 16-Lead VFQFN packaging
- -40°C to 85°C ambient operating temperature nQ0 nQ1 nQ2 nQ3 PCLK1 nPCLK1 VDD Pullup/Pulldown Pulldown SEL Pullup/Pulldown PCLK0 nPCLK0 VDD GND Pullup/Pulldown Pulldown VDD GND Reference Voltage Generator VREF GND GND GND 1 2 3 4 12 11 10 9 nQ2 nQ3 VREF nPCLK0 PCLK0 VDD GND SEL PCLK1 nPCLK1 nQ0 nQ1 Pin Assignment IDT8SLVD1204I 16 lead VFQFN 3.0mm x 3.0mm x 0.9mm package body 1.7mm x 1.7mm ePad Top View Block Diagram
Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. SEL Input Selection Function Table NOTE: SEL is an asynchronous control. 1G N D P o w e r Power supply ground.
2 SEL Input Pullup/
3 PCLK1 Input Pulldown Non-inverting differential clock/data input. Pulldown Inverting differential clock/data input. VDD/2 default when left floating. 5V DD Power Power supply pin. 6 PCLK0 Input Pulldown Non-inverting differential clock/data input. Pulldown Inverting differential clock/data input. VDD/2 default when left floating. 8V REF Output Bias voltage reference for the PCLK, nPCLK inputs. 9, 10 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 13, 14 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 15, 16 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. 0 PCLK0, nPCLK0 is the selected differential clock input. 1 PCLK1, nPCLK1 is the selected differential clock input. Open (default) Input buffers are di sabled and outputs are static.
REVISION A 07/10/14 3 2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
Electrical Characteristics
Table 4A. Power Supply Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA VREF current Sink/Source, IREF ±2mA Maximum Junction Temperature, TJ,MAX 125°C Storage Temperature, TSTG -65C to 150C ESD - Human Body Model, NOTE 1 2000V ESD - Charged Device Model, NOTE 1 1500V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units V DD Power Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current SEL = 0 or 1; fREF = 100MHz; Q0 to Q3 terminated 100 between nQx, Qx 84 100 mA SEL = 0 or 1; fREF = 800MHz; Q0 to Q3 terminated 100 between nQx, Qx 84 100 mA SEL = 0 or 1; fREF = 2GHz; Q0 to Q3 terminated 100 between nQx, Qx 84 100 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VdI3 Open-Pin Voltage (Default State) SEL Open V DD / 2 V VIH Input High Voltage SEL 0.7 * V DD VDD + 0.3 V VIL Input Low Voltage SEL -0.3 0.2 * V DD V IIH Input High Current SEL V DD = VIN = 2.625V 150 µA IIL Input Low Current SEL V DD = 2.625V, VIN = 0V -150 µA
2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V 4 REVISION A 07/10/14 Table 4C. Differential Input DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined at the crosspoint. Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85° Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current PCLK0, nPCLK1 PCLK1, nPCLK1 VDD = VIN = 2.625V 150 µA IIL Input Low Current PCLK0, PCLK1 V DD = 2.625V, VIN = 0V -10 µA nPCLK0, nPCLK1 VDD = 2.625V, VIN = 0V -150 µA VREF Reference Voltage for Input Bias I REF = ±1mA V DD – 1.50 V DD – 1.35 V DD – 1.15 V VPP Peak-to-Peak Voltage; NOTE 1 fREF < 1.5 GHz 0.1 1.5 V fREF > 1.5 GHz 0.2 1.5 V VCMR Common Mode Input Voltage; NOTE 1, 2 1.0 V DD – 0.6 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage 250 450 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.15 1.45 V VOS VOS Magnitude Change 50 mV
Table 5. AC Electrical Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C has been reached under these conditions. NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint. NOTE 5: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V 6 REVISION A 07/10/14 Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the noise floor of the input source and measurement equipment. Measured using a Wenzel 156.25MHz Oscillator as the input source. Additive Phase Jitter @ 156.25MHz, VPP = 1V, Integration Range (12kHz to 20MHz) = 65fs (typical) SSB Phase Noise (dBc/Hz) Offset from Carrier Frequency (Hz)
REVISION A 07/10/14 7 2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V Parameter Measurement Information LVDS Output Load Test Circuit Pulse Skew Part-to-Part Skew Differential Input Level Output Skew Output Rise/Fall Time VDD tPLH tPHL tsk(p) = |tPHL - tPLH| PCLK[0:1] nPCLK[0:1] Qy nQy tsk(pp) Part 1 Part 2 Qx nQx Qy nQy VDD GND nPCLK[0:1] PCLK[0:1] Qx nQx Qy nQy nQ[0:3] Q[0:3] 20% 80% 80% 20% tR tF VOD
2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V 8 REVISION A 07/10/14 Parameter Measurement Information, continued Input Skew Propagation Delay Differential Output Voltage Setup MUX Isolation Offset Voltage Setup tPD2 tPD1 tsk(i) = |tPD1 - tPD2| tsk(i) nPCLK1 PCLK1 nQ[0:3] Q[0:3] nPCLK0 PCLK0 tPD nQ[0:3] Q[0:3] nPCLK[0:1] PCLK[0:1] Amplitude (dB) Spectrum of Output Signal Q MUX_ISOLATION = A0 – A1 (fundamental) Frequencyƒ MUX selects other input MUX selects active input clock signal
and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below. Table 6. Thermal Resistance JA for 16-Lead VFQFN, Forced Convection
Table 7. JA vs. Air Flow Table for a 16-Lead VFQFN
REVISION A 07/10/14 15 2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V 16-Lead VFQFN Package Outline and Package Dimensions
2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V 16 REVISION A 07/10/14
Ordering Information
Table 8. Ordering Information Table 9. Pin 1 Orientation in Tape and Reel Packaging
8 Quadrant 1 (EIA-481-C)
REVISION A 07/10/14 17 2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V Revision History Sheet Rev Table Page Description of Change Date A 1 Corrected part number 7/8/2014
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