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3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING

2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4664/4 FUNCTIONAL BLOCK DIAGRAM

FEATURES

  • •••• Memory storage capacity: IDT72V3654 – 2,048 x 36 x 2 IDT72V3664 – 4,096 x 36 x 2 IDT72V3674 – 8,192 x 36 x 2
  • •••• Clock frequencies up to 100 MHz (6.5ns access time)
  • •••• Two independent clocked FIFOs buffering data in opposite directions
  • •••• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRB flag functions)
  • •••• Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024 )
  • •••• Serial or parallel programming of partial flags
  • •••• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
  • •••• Big- or Little-Endian format for word and byte bus sizes
  • •••• Retransmit Capability
  • •••• Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
  • •••• Mailbox bypass registers for each FIFO
  • •••• Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)
  • •••• Auto power down minimizes power dissipation
  • •••• Available in space saving 128-pin Thin Quad Flatpack (TQFP)
  • •••• Pin and functionally compatible version of the 5V operating IDT723654/723664/723674
  • •••• Pin compatible to the lower density parts, IDT72V3624/72V3634/ 72V3644
  • •••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available Mail 1 Register Programmable Flag Offset Registers Input Register RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 Write Pointer Read Pointer Status Flag Logic Input Register Output Register RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 Write Pointer Read Pointer Status Flag Logic CLKA CSA W/RA ENA MBA Port-A Control Logic FIFO1, Mail1 Reset Logic MRS1 Mail 2 Register MBF2 CLKB CSB W/RB ENB MBB BE BM SIZE Port-B Control Logic FIFO2, Mail2 Reset Logic MRS2 MBF1 FIFO1 FIFO2 EFB/ORB AEB FFB/IRB AFB B0-B35 FFA/IRA AFA FS2 FS0/SD FS1/SEN A0-A35 EFA/ORA AEA 4664 drw01 Output Bus- Matching Output Register PRS2 PRS1 Timing Mode FWFT 36 36 36 36 Input Bus- Matching FIFO1 and FIFO2 Retransmit Logic RT1 RT2 RTM

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 PIN CONFIGURATION TQFP (PK128-1, order code: PF) TOP VIEW W/RA CLKB 4664 drw 02 ENA CLKA GND A35 A34 A33 A32 Vcc A31 A30 GND A29 A28 A27 A26 A25 A24 A23 BE/FWFT GND A22 Vcc A21 A20 A19 A18 GND A17 A16 A15 A14 A13 Vcc A12 GND A11 A10 100 102 101 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PRS2/RT2 Vcc B35 B34 B33 B32 RTM GND B31 B30 B29 B28 B27 B26 Vcc B25 B24 BM GND B23 B22 B21 B20 B19 B18 GND B17 B16 Vcc B15 B14 B13 B12 GND B11 B10 CSA FFA/IRA EFA/ORA PRS1/RT1 Vcc AFA AEA MBF2 MBA MRS1 FS0/SD GND GND FS1/SEN MRS2 MBB MBF1 Vcc AEB AFB EFB/ORB FFB/IRB GND CSB W/RB ENB GND Vcc GND GND Vcc 104 103 INDEX SIZE FS2

DESCRIPTION

The IDT72V3654/72V3664/72V3674 are pin and functionally compat- ible versions of the IDT723654/723664/723674, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are mono- lithic, high-speed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual- port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchro- nous control. Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers’ width matches the selected Port B bus width. Each Mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on these FIFOs: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array, configures the FIFO for Big- or Little-Endian byte arrangement and selects serial flag programming, parallel flag programming, or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024. There are two Master Reset pins, MRS1 and MRS2. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1 and PRS2. Both FIFO's have Retramsmit capability, when a Retransmit is performed on a respective FIFO only the read pointer is reset to the first memory location. A Retransmit is performed by using the Retransmit Mode, RTM pin in conjunction with the Retransmit pins RT1 or RT2, for each respective FIFO. Note that the two Retransmit pins RT1 and RT2 are muxed with the Partial Reset pins. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first word written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does neces- sitate a formal read request). The state of the BE/FWFT pin during Master Reset determines the mode in use. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first long- word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation is required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/FWFT pin during FIFO operation determines the mode in use. Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/ORB) and a combined Full/Input Ready Flag ( FFA/IRA and FFB/ IRB). The EF and FF functions are selected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a programmable Almost-Full flag ( AFA and AFB). AEA and AEB indicate when a selected number of words remain in the FIFO memory. AFA and AFB indicate when the FIFO contains more than a selected number of words. FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are two-stage synchronized to the port clock that reads data from its array. Programmable offsets for AEA, AEB, AFA and AFB are loaded in parallel using Port A or in serial via the SD input. Five default offset settings are also provided. The AEA and AEB threshold can be set at 8, 16, 64, 256 or 1,024 locations from the empty boundary and the AFA and AFB threshold can be set at 8, 16, 64, 256 or 1,024 locations from the full boundary. All these choices are made using the FS0, FS1 and FS2 inputs during Master Reset. Interspersed Parity can also be selected during a Master Reset of the FIFO. If Interspersed Parity is selected then during parallel programming of the flag offset values, the device will ignore data line A8. If Non-Interspersed Parity is selected then data line A8 will become a valid bit. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (I CC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V3654/72V3664/72V3674 are characterized for operation from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available. They are fabricated using IDT’s high speed, submicron CMOS technology.

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 PIN DESCRIPTIONS Symbol Name I/O Description A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. AEA Port A Almost- O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in Empty Flag FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2. AEB Port B Almost- O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in Empty Flag FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1. AFA Port A Almost- O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty Full Flag locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1. AFB Port B Almost- O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty Full Flag locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2. B0-B35 Port A Data I/O 36-bit bidirectional data port for side B. BE/FWFT Big-Endian/ I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. First Word In this case, depending on the bus size, the most significant byte or word on Port A is read from Fall Through Port B first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Select Little-Endian operation. In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static throughout device operation. BM(1) Bus-Match Select I A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of (Port B) SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The level of BM must be static throughout device operation. CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH transition of CLKB. CSA Port A Chip Select I CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. EFA/ORA Port A Empty/ O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA Output Ready Flag indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA. EFB/ORB Port B Empty/ O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates Output Ready Flag whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on the B0-B35 outputs, available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. FFA/IRA Port A Full/ O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates Input Ready Flag whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA. FFB/IRB Port B Full/ O This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates Input Ready Flag whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 Symbol Name I/O Description FS0/SD Flag Offset Select 0/ I FS1/ SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Serial Data Master Reset, FS1/ SEN and FS0/SD, together with FS2, select the flag offset programming method Three offset register programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024), parallel load from Port A, and serial load. FS1/SEN Flag Offset Select 1/ I Serial Enable, When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA FS2 (1) Flag Offset Select 2 I load the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 44 for the IDT72V3654, 48 for the IDT72V3664, and 52 for the IDT72V3674. The first bit write stores the Y-register (Y1) MSB and the last bit write stores the X-register (X2) LSB. MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When Select the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2 output register data for output. MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the Select B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output register data for output. MBF1 Mail1 Register O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Flag Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1. MBF2 Mail2 Register O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes Flag to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2. MRS1 FIFO1 Master I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Reset Port B output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or parallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW. MRS2 FIFO2 Master I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets Reset the Port A output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects the programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW. PRS1/ Partial Reset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM RT1 Retransmit FIFO1 pin. If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read pointer only to the first memory location. PRS2/ Partial Reset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM RT2 Retransmit FIFO2 pin. If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer only to the first memory location. RTM Retransmit Mode I This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on FIFO1 or FIFO2 respectively. SIZE (1) Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation PIN DESCRIPTIONS (CONTINUED) NOTE: 1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or V CC.

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 Symbol Name I/O Description W/RA Port-A Write/ I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH Read Select transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH. W/RB Port-B Write/ I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH Read Select transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW. PIN DESCRIPTIONS (CONTINUED)

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE- AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol Rating Commercial Unit VCC Supply Voltage Range –0.5 to +4.6 V VI(2) Input Voltage Range –0.5 to V CC+0.5 V VO(2) Output Voltage Range –0.5 to VCC+0.5 V IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA IOK Output Clamp Current (VO = < 0 or VO > VCC) ±50 m A IOUT Continuous Output Current (VO = 0 to VCC) ±50 m A ICC Continuous Current Through VCC or GND ±400 m A TSTG Storage Temperature Range –65 to 150 °C NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)(1) RECOMMENDED OPERATING CONDITIONS NOTE: 1. For 10ns speed grade: Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant Symbol Parameter Min. Typ. Max. Unit VCC(1) Supply Voltage for 10ns 3.15 3.3 3.45 V VCC Supply Voltage for 15ns 3.0 3.3 3.6 V VIH High-Level Input Voltage 2 — V CC+0.5 V VIL Low-Level Input Voltage — — 0.8 V IOH High-Level Output Current — — –4 mA IOL Low-Level Output Current — — 8 mA TA Operating Temperature 0 — 70 °C NOTES: 1. All typical values are at V CC = 3.3V, T A = 25 °C. 2. Commercial-10ns speed grade only: Vcc = 3.3V ± 0.15V, T A = 0 ° to +70 °; JEDEC JESD8-A compliant. 3. For additional I CC information, see Figure 1, Typical Characteristics: Supply Current (I CC) vs. Clock Frequency (f S). 4. Characterized values, not currently tested. IDT72V3654 IDT72V3664 IDT72V3674 Commercial tCLK = 10, 15 ns(2) Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit VOH Output Logic "1" Voltage V CC = 3.0V, I OH = –4 mA 2.4 — — V VOL Output Logic "0" Voltage V CC = 3.0V, I OL = 8 mA — — 0.5 V ILI Input Leakage Current (Any Input) V CC = 3.6V, V I = VCC or 0 — — ±10 µ A ILO Output Leakage Current V CC = 3.6V, V O = VCC or 0 — — ±10 µ A ICC2(3) Standby Current (with CLKA & CLKB running) V CC = 3.6V, V I = VCC –0.2V or 0V — — 5 mA ICC3(3) Standby Current (no clocks running) V CC = 3.6V, V I = VCC –0.2V or 0V — — 1 mA CIN(4) Input Capacitance V I = 0, f = 1 MHz — 4 — pF COUT(4) Output Capacitance V O = 0, f = 1 MHZ — 8 — pF

HIGH levels are known, the power dissipation can be calculated with the equation below. Figure 1. Typical Characteristics: Supply Current (I CC) vs. Clock Frequency (f S)

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE IDT72V3654L10(1) IDT72V3654L15 IDT72V3664L10(1) IDT72V3664L15 IDT72V3674L10(1) IDT72V3674L15 Symbol Parameter Min. Max. Min. Max. Unit fS Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns tCLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns tCLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 3—4 — n s tENS1 Setup Time, CSA and W/RA before CLKA↑; CSB and 4 — 4.5 — ns W/RB before CLKB↑ tENS2 Setup Time, ENA, and MBA before CLKA↑; ENB, and 3 — 4.5 — ns MBB before CLKB↑ tRSTS Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before 5 — 5 — ns CLKA↑ or CLKB↑(2) tFSS Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns tBES Setup Time, BE/FWFT before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns tSDS Setup Time, FS0/SD before CLKA↑ 3—4 — n s tSENS Setup Time, FS1/SEN before CLKA↑ 3—4 — n s tFWS Setup Time, BE/FWFT before CLKA↑ 0—0 — n s tRTMS Setup Time, RTM before RT1; RTM before RT2 5—5 — n s tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, 0.5 — 1 — ns W/RB, ENB, and MBB after CLKB↑ tRSTH Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ 4—4 — n s or CLKB↑(2) tFSH Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH 2 — 2 — ns tBEH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 2 — 2 — ns tSDH Hold Time, FS0/SD after CLKA↑ 0.5 — 1 — ns tSENH Hold Time, FS1/SEN HIGH after CLKA↑ 0.5 — 1 — ns tSPH Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH 2 — 2 — ns tRTMH Hold Time, RTM after RT1; RTM after RT2 5—5 — n s tSKEW1(3) Skew Time between CLKA↑ and CLKB↑ for EFA/ORA, 5 — 7.5 — ns EFB/ORB, FFA/IRA, and FFB/IRB tSKEW2(3,4) Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA,1 2—1 2 — n s and AFB NOTES: 1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; T A = 0 ° to +70°. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship b etween CLKA cycle and CLKB cycle. 4. Design simulated, not tested. (For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0° C to +70° C; JEDEC JESD8-A compliant)

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF IDT72V3654L10(1) IDT72V3654L15 IDT72V3664L10(1) IDT72V3664L15 IDT72V3674L10(1) IDT72V3674L15 Symbol Parameter Min. Max. Min. Max. Unit tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 6.5 2 10 ns tWFF Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ 2 6.5 2 8 ns to FFB/IRB tREF Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ 1 6.5 1 8 ns to EFB/ORB tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to 1 6.5 1 8 ns AEB tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to 1 6.5 1 8 ns AFB tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 0 6.5 0 8 ns HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH tPMR Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ 382 1 0 n s to A0-A35(3) tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to 3 6.5 2 10 ns B0-B35 valid t RSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB 11 01 1 5 n s LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH tEN Enable Time, CSA or W/RA LOW to A0-A35 Active and 2 6 2 10 ns CSB LOW and W/RB HIGH to B0-B35 Active tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high 1 6 1 8 ns impedance and CSB HIGH or W/RB LOW to B0-B35 at high impedance NOTES: 1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0 ° to +70 °. 2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. (For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 SIGNAL DESCRIPTION MASTER RESET (MRS1, MRS2) After power up, a Master Reset operation must be performed by providing a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, each of the two FIFO memories of the IDT72V3654/72V3664/72V3674 undergoes a complete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW- to-HIGH transitions. The Master Reset inputs can switch asynchronously to the clocks. A Master Reset initializes the associated write and read pointers to the first location of the memory and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW and forces the Almost-Full flag (AFA, AFB) HIGH. A Master Reset also forces the associated Mailbox Flag (MBF1, MFB2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/Input Ready flag is set HIGH after two write clock cycles. Then the FIFO is ready to be written to. A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input latches the values of the Big-Endian (BE) input for determining the order by which bytes are transferred through Port B. It also latches the values of the Flag Select (FS0, FS1 and FS2) inputs for choosing the Almost-Full and Almost- Empty offset programming method. A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears the Flag Offset Registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) together with the FIFO1 Master Reset (MRS1) input latches the value of the Big-Endian (BE) input for Port B and also latches the values of the Flag Select (FS0, FS1 and FS2) inputs for choosing the Almost- Full and Almost-Empty offset programming method. (For details see Table 1, Flag Programming, and the Programming the Almost-Empty and Almost-Full Flags section). The relevant FIFO Master Reset timing diagram can be found in Figure 3. PARTIAL RESET (PRS1, PRS2) Each of the two FIFO memories of these devices undergoes a limited reset by taking its associated Partial Reset (PRS1, PRS2) input LOW for at least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously to the clocks. A Partial Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag ( EFA/ORA, EFB/ORB) LOW, the Almost-Empty flag ( AEA, AEB) LOW, and the Almost-Full flag (AFA, AFB) HIGH. A Partial Reset also forces the Mailbox Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two write clock cycles. Then the FIFO is ready to be written to. Whatever flag offsets, programming method (parallel or serial), and timing mode (FWFT or IDT Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will be remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient. See Figure 4 for the Partial Reset timing diagram. RETRANSMIT (RT1, RT2) The FIFO1 memory of these devices undergoes a Retransmit by taking its associated Retransmit (RT1) input LOW for at least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit initializes the read pointer of FIFO1 to the first memory location. The FIFO2 memory undergoes a Retransmit by taking its associated Retransmit (RT2) input LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC) LOW-to-HIGH transitions. The Retransmit initializes the read pointer of FIFO2 to the first memory location. The RTM pin must be HIGH during the time of Retranmit. Note that the RT1input is muxed with the PRS1 input, the state of the RTM pin determining whether this pin performs a Retransmit or Partial Reset. Also, the RT2input is muxed with the PRS2 input, the state of the RTM pin determining whether this pin performs a Retransmit or Partial Reset. BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/ FWFT) — ENDIAN SELECTION This is a dual purpose pin. At the time of Master Reset, the BE select function is active, permitting a choice of Big or Little-Endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data are transferred through this port. For the following illustrations, assume that a byte (or word) bus size has been selected for Port B. (Note that when Port B is configured for a long word size, the Big-Endian function has no application and the BE input is a “don’t care” 1.) A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs go from LOW to HIGH will select a Big-Endian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the long word written to Port A will be read from Port B first; the least significant byte (word) of the long word written to Port A will be read from Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from Port A as the most significant byte (word) of the long word; the byte (word) written to Port B last will be read from Port A as the least significant byte (word) of the long word. A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs go from LOW to HIGH will select a Little-Endian arrangement. When data is moving in the direction from Port A to Port B, the least significant byte (word) of the long word written to Port A will be read from Port B first; the most significant byte (word) of the long word written to Port A will be read from Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from Port A as the least significant byte (word) of the long word; the byte (word) written to Port B last will be read from Port A as the most significant byte (word) of the long word. Refer to Figure 2 for an illustration of the BE function. See Figure 3 (Master Reset) for the Endian select timing diagram. — TIMING MODE SELECTION After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: IDT Standard mode or First Word Fall Through (FWFT) mode. Once the Master Reset ( MRS1, MRS2) input is HIGH, a HIGH on the BE/ FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode uses the Empty Flag function ( EFA, EFB) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function (FFA, FFB) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation. NOTE: 1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheles s, inputs that are temporarily "don't care" (along with unused inputs) must not be left open, rather they must be either HIGH or LOW.

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/ FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. Following Master Reset, the level applied to the BE/FWFT input to choose the desired timing mode must remain static throughout FIFO operation. Refer to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram. PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS Four registers in the IDT72V3654/72V3664/72V3674 are used to hold the offset values for the Almost-Empty and Almost-Full flags. The Port B Almost- Empty flag (AEB) Offset register is labeled X1 and the Port A Almost-Empty flag (AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset register is labeled Y1 and the Port B Almost-Full flag (AFB) Offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO, programmed in parallel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1). FS0/SD, FS1/SEN and FS2 function the same way in both IDT Standard and FWFT modes. — PRESET VALUES To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with one of the five preset values listed in Table 1, the flag select inputs must be HIGH or LOW during a master reset. For example, to load the preset value of 64 into X1 and Y1, FS0, FS1 and FS2 must be HIGH when FlFO1 reset (MRS1) returns HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 Master Reset ( MRS2), toggled simultaneously with FIFO1 Master Reset (MRS1). For relevant preset value loading timing diagram, see Figure 3. PARALLEL LOAD FROM PORT A To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master Reset on both FlFOs simultaneously with FS2 HIGH or LOW, FS0 and FS1 LOW during the LOW-to-HIGH transition of MRS1 and MRS2. The state of FS2 at this point of reset will determine whether the parallel programming method has Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag Programming Flag Offset setup . It is important to note that once parallel programming has been selected during a Master Reset by holding both FS0 & FS1 LOW, these inputs must remain LOW during all subsequent FIFO operation. They can only be toggled HIGH when future Master Resets are performed and other programming methods are desired. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non- Interspersed Parity mode the Port A data inputs used by the Offset registers are (A10-A0), (A11-A0), or (A12-A0) for the IDT72V3654, IDT72V3664, or IDT72V3674, respectively. For Interspersed Parity mode the Port A data inputs used by the Offset registers are (A11-A9, A7-A0), (A12-A9, A7-A0), or (A13- A9, A7-A0) for the IDT72V3654, IDT72V3664, or IDT72V3674, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 2,044 for the IDT72V3654; 1 to 4,092 for the IDT72V3664; and 1 to 8,188 for the IDT72V3674. After all the offset registers are programmed from Port A, NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. 3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity. 4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity. 5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation. FS2 FS1/ SEN FS0/SD MRS1 MRS2 X1 AND Y1 REGlSTERS(1) X2 AND Y2 REGlSTERS(2) HH H ↑ X6 4 X HH HX ↑ X6 4 HH L ↑ X1 6 X HH LX ↑ X1 6 HL H ↑ X8 X HL HX ↑ X8 LH H ↑ X 256 X LH HX ↑ X 256 LL H ↑ X 1,024 X LL HX ↑ X 1,024 LH L ↑↑ Serial programming via SD Serial programming via SD HL L ↑↑ Parallel programming via Port A(3, 5) Parallel programming via Port A(3, 5) LL L ↑↑ IP Mode(4, 5) IP Mode(4, 5) TABLE 1 — FLAG PROGRAMMING

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 offset values, the device will ignore data line A8. If Non-Interspersed Parity is selected then data line A8 will become a valid bit. If Interspersed Parity is selected serial programming of the offset values is not permitted, only parallel program- ming can be done. — SERIAL LOAD To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset with FS2 LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is LOW. There are 44-, 48-, or 52- bit writes needed to complete the programming for the IDT72V3654, IDT72V3664, or IDT72V3674, respectively. The four registers are written in the order Y1, TABLE 3 — PORT B ENABLE FUNCTION TABLE the Port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal operation. Refer to Figure 5 for a timing diagram illustration of parallel programming of the flag offset values. INTERSPERSED PARITY Interspersed Parity is selected during a Master Reset of the FIFO. Refer to Table 1 for the set-up configuration of Interspersed Parity. The Interspersed Parity function allows the user to select the location of the parity bits in the word loaded into the parallel port (A0-An) during programming of the flag offset values. If Interspersed Parity is selected then during parallel programming of the flag CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O Port Function H X X X X High-Impedance None L H L X X Input None LHH L ↑ Input FIFO1 write LHH H ↑ Input Mail1 write L L L L X Output None LL H L ↑ Output FIFO2 read L L L H X Output None LL H H ↑ Output Mail2 read (set MBF2 HIGH) TABLE 2 — PORT A ENABLE FUNCTION TABLE CSB W /RB ENB MBB CLKB Data B (B0-B35) I/O Port Function H X X X X High-Impedance None L L L X X Input None LL H L ↑ Input FIFO2 write LL H H ↑ Input Mail2 write L H L L X Output None LHH L ↑ Output FIFO1 read L H L H X Output None LHH H ↑ Output Mail1 read (set MBF1 HIGH) X1, Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1 register and the last-bit write stores the least significant bit of the X2 register. Each register value can be programmed from 1 to 2,044 (IDT72V3654), 1 to 4,092 (IDT72V3664), or 1 to 8,188 (IDT72V3674). When the option to program the offset registers serially is chosen, the Port A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written. FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFB/ IRB) flag also remains LOW throughout the serial programming process, until all register bits are written. FFB/IRB is set HIGH by the LOW-to-HIGH transition of CLKB after the last bit is loaded to allow normal FIFO2 operation. See Figure 6 for Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes) timing diagram. FIFO WRITE/READ OPERATION The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select (CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in the High- impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are active outputs when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW,

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 Synchronized Synchronized Number of Words in FIFO Memory(1,2) to CLKA to CLKB IDT72V3654(3) IDT72V3664(3) IDT72V3674(3) EFA/ORA AEA AFB FFB /IRB

000 L L H H

1 to X2 1 to X2 1 to X2 H L H H (2,048-Y2) to 2,047 (4,096-Y2) to 4,095 (8,192-Y2) to 8,191 H H L H 2,048 4,096 8,192 H H L L TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes) TABLE 5 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes) Synchronized Synchronized Number of Words in FIFO Memory(1,2) to CLKB to CLKA IDT72V3654(3) IDT72V3664(3) IDT72V3674(3) EFB/ORB AEB AFA FFA /IRA 00 0 L L H H 1 to X1 1 to X1 1 to X1 H L H H (2,048-Y1) to 2,047 (4,096-Y1) to 4,095 (8,192-Y1) to 8,191 H H L H 2,048 4,096 8,192 H H L L ENA is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and writes on Port A are independent of any concurrent Port B operation. The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35 lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO reads and writes on Port B are independent of any concurrent Port A operation. The setup and hold time constraints to the port clocks for the port Chip Selects and Write/Read selects are only for enabling write and read operations NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming. 4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode. NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming. 4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode. and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/Read select may change states during the setup and hold time window of the cycle. When operating the FIFO in FWFT mode and the Output Ready flag is LOW, the next word written is automatically sent to the FIFO’s output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH. When the Output Ready flag is HIGH, subsequent data is clocked to the output registers only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in IDT Standard mode, the first word will cause the Empty Flag to change state on the second LOW-to-HIGH transition of the Read Clock. The data word will not be automatically sent to the output register. Instead, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. Write and read timing diagrams for Port A can be found in Figure 7 and 14. Relevant Port B write and read cycle timing diagrams together with Bus-Matching and Endian select operations can be found in Figures 8 through 13.

COMMERCIAL TEMPERATURE RANGE IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB) These are dual purpose flags. In the FWFT mode, the Output Ready (ORA, ORB) function is selected. When the Output-Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. In the IDT Standard mode, the Empty Flag (EFA, EFB) function is selected. When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory for reading to the output register. When the Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT and IDT Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is empty, empty+1, or empty+2. In FWFT mode, from the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FlFO output register and three cycles of the port Clock that reads data from the FIFO have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta- neously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. In IDT Standard mode, from the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FlFO output register and two cycles of the port Clock that reads data from the FIFO have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty Flag HIGH; only then can data be read. A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t SKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 15, 16, 17, and 18). FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB) This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB) function is selected. In IDT Standard mode, the Full Flag ( FFA and FFB) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored. The Full/Input Ready flag of a FlFO is synchronized to the port clock that writes data to its array. For both FWFT and IDT Standard modes, each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls a Full/Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FlFO memory status is full, full-1, or full- 2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/Input Ready flag HIGH. A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t SKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 19, 20, 21, and 22). ALMOST-EMPTY FLAGS (AEA, AEB) The Almost-Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost-Empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost- Empty flag and Almost-Full flag offset programming section). An Almost- Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock are required after a FIFO write for its Almost-Empty flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins the first synchro- nization cycle if it occurs at time t SKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. (See Figure 23 and 24). ALMOST-FULL FLAGS ( AFA, AFB) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FlFO reset, programmed from Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Full flag is LOW when the number of words in its FIFO is greater than or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for the IDT72V3654, IDT72V3664, or IDT72V3674 respectively. An Almost- Full flag is HIGH when the number of words in its FIFO is less than or equal IDT72V3664, or IDT72V3674 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [2,048/4,096/8,192- (Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second

Figure 2. Bus Sizing

  1. t SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
  2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.

Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)

  1. t SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

  1. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.

Figure 16. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)

  1. t SKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
  2. If Port B size is word or byte, t SKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode )

  1. t SKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

  1. If Port B size is word or byte, t SKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

Figure 18. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)

  1. t SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.

  1. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.

Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)

Figure 22. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)

  1. t SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.

  1. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.

Figure 28. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)

  1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don’t care input s). In this first case A0-A17 will have valid data

case, A0-A8 will have valid data (A9-A35 will be indeterminate).

Figure 33. Output Load and AC Test Conditions

  1. Includes probe and jig capacitance.

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ORDERING INFORMATION

L 72V3654 72V3664 72V3674 4664 drw36 Commercial (0°C to +70°C) Thin Quad Flat Pack (TQFP, PK128-1) Low Power 2,048 x 36 x 2  3.3V SyncBiFIFO with Bus-Matching 4,096 x 36 x 2  3.3V SyncBiFIFO with Bus-Matching 8,192 x 36 x 2  3.3V SyncBiFIFO with Bus-Matching XXXXXXIDT Device Type XX X X X Power Speed Package Process/ Temperature Range Clock Cycle Time (tCLK) Speed in NanosecondsCommercial Only NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 09/25/2000 pgs. 7, 9, 10 and 37. 12/22/2000 pgs. 4, 5 and 13. 02/08/2001 pgs. 5 and 12. 03/21/2001 pgs. 7 and 8. 11/03/2003 pg. 1.