DT70V27L

IDT70V27S IDT | Alldatasheet

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©2000 Integrated Device Technology, Inc. 6.01 1 /G4A/G41/G4E/G55/G41/G52/G59/G20 /G32/G30/G30/G31 DSC 3603/7 /G46/G65/G61/G74/G75/G72/G65/G73/G3A N True Dual-Ported memory cells which allow simultaneous access of the same memory location N High-speed access – Industrial: 35ns (max.) – Commercial: 15/20/25/35/55ns (max.) N Low-power operation – IDT70V27S Active: 500mW (typ.) Standby: 3.3mW (typ.) – IDT70V27L Active: 500mW (typ.) Standby: 660 µW (typ.) N Separate upper-byte and lower-byte control for bus matching capability N Dual chip enables allow for depth expansion without external logic IDT70V27S/L N IDT70V27 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device N M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave N Busy and Interrupt Flags N On-chip port arbitration logic N Full on-chip hardware support of semaphore signaling between ports N Fully asynchronous operation from either port N LVTTL-compatible, single 3.3V (±0.3V) power supply N Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA (fpBGA) N Industrial temperature range (-40°C to +85°C) is available for selected speeds I/O Control Address Decoder 32Kx16 MEMORY ARRAY 70V27 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0L OEL R/WL A14L A0L A14L A0L SEML INTL (2) BUSYL (1,2) LBL CE0L OEL UBL I/O Control Address Decoder CE0R OER R/WR A14R A0R A14R A0R SEMR INTR(2) BUSYR(1,2) LBR R/WR OER UBR M/S (2) CE 1L CE0R CE 1R 3603 drw 01 I/O0-7L CE 1RCE 1L I/O8-15L I/O0-7R I/O8-15R R/WL NOTES: 1) BUSY is an input as a Slave (M/ S=VIL) and an output as a Master (M/ S=VIH). 2) BUSY and INT are non-tri-state totem-pole outputs (push-pull). HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM /G46/G75/G6E/G63/G74/G69/G6F/G6E/G61/G6C/G20/G42/G6C/G6F/G63/G6B/G20/G44/G69/G61/G67/G72/G61/G6D

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G44/G65/G73/G63/G72/G69/G70/G74/G69/G6F/G6E/G3A The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM, designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32- bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables ( CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 500mW of power. The IDT70V27 is packaged in a 100-pin Thin Quad Flatpack (TQFP), a 108-pin ceramic Pin Grid Array (PGA), and a 144-pin Fine Pitch BGA (fp BGA). /G50/G69/G6E/G20/G43/G6F/G6E/G66/G69/G67/G75/G72/G61/G74/G69/G6F/G6E/G73/G28/G31/G2C/G32/G2C/G33/G29 NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. INDEX 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 0 09 99 8 9 79 69 5 9 49 39 2 9 19 0 8 98 8 8 78 6 8 58 4 8 38 28 1 8 07 9 7 87 7 7 6 IDT70V27PF PN100-1(4) 100-PIN TQFP TOP VIEW (5) GND OER R/WR SEMR CE 1R CE0R NC NC GND A12R A13R A11R A10R A9R A14R NC I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND UBR LBR 3603 drw 02 I/O15L GND OEL R/WL SEML CE 1L CE0L Vcc NC A14L A13L NC NC A12L A11L A10L A9L I/O10L I/O11L I/O12L I/O13L I/O14L UBL LBL GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O A A8L A7L A6R A5R A4R A3R A2R A1R A0R INTR BUSYR M BUSYL INTL NCA0L A2L A3L A5L A6L A1L A4L A8R GND Vcc I/O1L Vcc GND

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G50/G69/G6E/G20/G43/G6F/G6E/G66/G69/G67/G75/G72/G61/G74/G69/G6F/G6E/G73/G28/G31/G2C/G32/G2C/G33/G29/G20/G28/G63/G6F/G6E/G27/G74/G2E/G29 NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 12mm x 12mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 3603 drw 02a IDT70V27BF BF144-1(4) 144-Pin fpBGA Top View(5) M/S BUSYL A2L A4L A7L NCNC A11L I/O3R VCC I/O2R GND I/O0R GND I/O0L I/O3L NC I/O6L I/O5L VCCNC NC NC NC LBR CE0R SEMR GND I/O14R GNDNC GNDR/WROER I/O15R I/O12RNC GND CE 1R NC I/O10R NC NCNC A12LA13L NCNC UBLCE0L VCC VCC NC R/WL CE 1L I/O15L NC NC NC OEL I/O14L NCA9L I/O10L I/013L A6L NCNC I/O11R NC I/O8R NC I/O6R NC I/O2L I/O4L I/O5R NC NC NC I/O4R I/O7R NC UBR NC NC I/O13R NC NC A8L A5L A1L INTL GND BUSYR A1R NC A10L A14L A10 A5R A11 NC A12 NC A13 NC LBL SEML VCC NC GND I/O12L I/O11L I/O9L NC NC I/O8L I/O7L NC I/O 1L VCC I/O1R NC V CC NC NC NC B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 E1 E2 E3 E4 E10 E11 E12 E13 F1 F2 F3 F4 F10 F11 F12 F13 G1 G2 G3 G4 G10 G11 G12 G13 H1 H2 H3 H4 H10 H11 H12 H13 J1 J2 J3 J4 J10 J11 J12 J13 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 INTR A2R A6R A3L NCNCNC A3R A7R A9R A10R A11R A4R A8R A12R A13R A14RA0RA0L I/O9R

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G50/G69/G6E/G20/G43/G6F/G6E/G66/G69/G67/G75/G72/G61/G74/G69/G6F/G6E/G73/G28/G31/G2C/G32/G2C/G33/G29/G20/G28/G63/G6F/G6E/G27/G74/G2E/G29 3603 drw 03 80 77 74 72 69 68 65 63 60 83 78 76 73 70 67 64 61 5984 56 8687 8890 9192 9495 9796 10099 103101 105104 31 34 35 37 39 40 44 43 48 46 52 49 55 51 IDT70V27G G108-1(4) 108-PIN PGA TOP VIEW (5) ABCDEFGHJ K L M 81 57 54 82 79 75 71 66 62 58 50 3691 1 1 4 1 5 1 8 2 0 2 3 29 30 26 27 102 106 107 108 INDEX GND OER R/WR SEM R CE 1R CE0RNC NC GND A12R A13R A11RA10R A9R GND OEL R/WL SEML CE 1L CE0L Vcc NC A14L A13L NC NCA12L A11L A10L A9L I/O6R I/O5R I/O4R I/O3R I/O2R I/O0R GND Vcc I/O0LI/O1L GNDI/O2LI/O4L I/O5L I/O6LI/O7L I/O3L I/O1R I/O7R NC I/O8R I/O9R I/O8L I/O9L VccA6R A5RA4R A3R A2R A1R A0RINTR BUSYRM/S BUSYL INTL NC A0L GND A2L A3L A5L A6L A1L A4L A8RA7R A8L A7L A14R NC I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R I/O10L I/O11L I/O12L I/O13L I/O14L GNDUB R LBR UBL LBL GND NC NC NC NC NCNC NC NC I/O15L Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A 14L A0R - A 14R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select LBL LBR Lower Byte Select INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 3603 tbl 0 1 /G50/G69/G6E/G20/G4E/G61/G6D/G65/G73NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G54/G72/G75/G74/G68/G20/G54/G61/G62/G6C/G65/G20/G49/G49/G20/G96/G20/G20/G4E/G6F/G6E/G2D/G43/G6F/G6E/G74/G65/G6E/G74/G69/G6F/G6E/G20/G52/G65/G61/G64/G2F/G57/G72/G69/G74/G65/G20/G43/G6F/G6E/G74/G72/G6F/G6C NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only. 2. Port "A" and "B" references are located where CE is used. 3. "H" = V IH and "L" = V IL /G54/G72/G75/G74/G68/G20/G54/G61/G62/G6C/G65/G20/G49/G20/G96/G20/G43/G68/G69/G70/G20/G45/G6E/G61/G62/G6C/G65/G28/G31/G2C/G32/G2C/G33/G29 /G54/G72/G75/G74/G68/G20/G54/G61/G62/G6C/G65/G20/G49/G49/G49/G20/G96/G20/G53/G65/G6D/G61/G70/G68/G6F/G72/G65/G20/G52/G65/G61/G64/G2F/G57/G72/G69/G74/G65/G20/G43/G6F/G6E/G74/G72/G6F/G6C NOTES: 1. A 0L — A 14L ≠ A 0R — A14R. 2. Refer to Chip Enable Truth Table. NOTES: 1. There are eight semaphore flags written to I/O 0 and read from all the I/Os (I/O 0-I/O15). These eight semaphore flags are addressed by A 0-A2. 2. Refer to Chip Enable Truth Table. CE CE 0 CE1 Mode L VIL VIH Port Selected (TTL Active) < 0.2V > VCC -0.2V Port Selected (CMOS Active) H VIH X Port Deselected (T T L Inactive) XV IL Port Deselected (TTL Inactive) >VCC -0.2V X Port Deselected (CMOS Inactive) X< 0.2V Port Deselected (CMOS Inactive) 3603 tbl 02 Inputs(1) Outputs ModeCE(2) R/W OE UB LB SEM I/O8-15 I/O0-7 HXXXXH H i g h - Z H i g h - Z D e s e l e c t e d : P o w e r - D o w n X X X H H H High-Z High-Z Both Bytes Deselected LLXLH H D A T A IN High-Z Write to Upper Byte Only L L X H L H High-Z DATA IN Write to Lower Byte Only LLXLLH D A T A IN DATAIN Write to Both Bytes LHLLH H D A T A OUT High-Z Read Upper Byte Only LHLHLH H i g h - Z D A T A OUT Read Lower Byte Only LHLLLH D A T A OUT DATAOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled 3603 tbl 03 Inputs(1) Outputs ModeCE(2) R/W OE UB LB SEM I/O8-15 I/O0-7 HHLXX L D A T A OUT DATAOUT Read Data in Semaphore Flag XHLHHL D A T A OUT DATAOUT Read Data in Semaphore Flag H ↑ XXXL D A T A IN DATAIN Write I/O0 into Semaphore Flag X ↑ XHHL D A T A IN DATAIN Write I/O0 into Semaphore Flag 3603 tbl 04

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G43/G61/G70/G61/G63/G69/G74/G61/G6E/G63/G65/G28/G31/G29 /G28/G54/G41/G20/G3D/G20/G2B/G32/G35/GB0/G43/G2C/G20/G66/G20/G3D/G20/G31/G2E/G30/G6D/G68/G7A/G29/G54/G51/G46/G50/G20/G4F/G4E/G4C/G59 /G44/G43/G20/G45/G6C/G65/G63/G74/G72/G69/G63/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73/G20/G4F/G76/G65/G72/G20/G74/G68/G65/G20/G4F/G70/G65/G72/G61/G74/G69/G6E/G67 /G54/G65/G6D/G70/G65/G72/G61/G74/G75/G72/G65/G20/G61/G6E/G64/G20/G53/G75/G70/G70/G6C/G79/G20/G56/G6F/G6C/G74/G61/G67/G65/G20/G52/G61/G6E/G67/G65/G20/G28/G56/G43/G43/G20/G3D/G20/G33/G2E/G33/G56/G20/GB1/G20/G30/G2E/G33/G56/G29 NOTE: 1. At Vcc < 2.0V, input leakages are undefined. /G4D/G61/G78/G69/G6D/G75/G6D/G20/G4F/G70/G65/G72/G61/G74/G69/G6E/G67/G20/G54/G65/G6D/G70/G65/G72/G61/G74/G75/G72/G65 /G61/G6E/G64/G20/G53/G75/G70/G70/G6C/G79/G20/G56/G6F/G6C/G74/G61/G67/G65/G28/G31/G2C/G32/G29 /G52/G65/G63/G6F/G6D/G6D/G65/G6E/G64/G65/G64/G20/G44/G43/G20/G4F/G70/G65/G72/G61/G74/G69/G6E/G67 /G43/G6F/G6E/G64/G69/G74/G69/G6F/G6E/G73 /G28/G31/G29 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V TERM > Vcc + 0.3V. /G41/G62/G73/G6F/G6C/G75/G74/G65/G20/G4D/G61/G78/G69/G6D/G75/G6D/G20/G52/G61/G74/G69/G6E/G67/G73/G28/G31/G29 NOTES: 1. V IL > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed Vcc + 0.3V. NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. Symbol Rating Commercial & Industrial Unit VTE RM(2) T erminal Voltage with Respect to GND -0.5 to +4.6 V TBI AS T emperature Under Bias -55 to +125 oC TST G Storage T emperature -65 to +150 oC IOUT DC Output Current 50 mA 3603 tbl 05 Grade Ambient Temperature GND Vcc Commercial 0 OC to +70 OC0 V 3 . 3 V + 0.3V Industrial -40 OC to +85 OC0 V 3 . 3 V + 0.3V 3603 tbl 06 Symbol Parameter Conditions (2 ) Max. Unit CIN Input Capacitance V IN = 3dV 9 pF COUT Output Capacitance VOUT = 3dV 10 pF 3603 tbl 08 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 3.0 3.3 3.6 V GND Ground 0 0 0 V VIH Input High Voltage 2.0 ____ VCC+0.3V(2) V VIL Input Low Voltage -0.3 (1) ____ 0.8 V 360 3 tbl 07 Symbol Parameter Test Conditions 70V27S 70V27L UnitMin. Max. Min. Max. |ILI| Input Leakage Current (1) VCC = 3.6V, V IN = 0V to V CC ___ 10 ___ 5µ A |ILO| Output Leakage Current CE = V IH, V OUT = 0V to V CC ___ 10 ___ 5µ A VOL Output Low Voltage I OL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage I OH = -4mA 2.4 ___ 2.4 ___ V 3603 tbl 09

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G44/G43/G20/G45/G6C/G65/G63/G74/G72/G69/G63/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73/G20/G4F/G76/G65/G72/G20/G74/G68/G65/G20/G4F/G70/G65/G72/G61/G74/G69/G6E/G67 /G54/G65/G6D/G70/G65/G72/G61/G74/G75/G72/G65/G20/G61/G6E/G64/G20/G53/G75/G70/G70/G6C/G79/G20/G56/G6F/G6C/G74/G61/G67/G65/G20/G52/G61/G6E/G67/G65/G28/G31/G2C/G36/G2C/G37/G29/G20/G28/G56/G43/G43/G20/G3D/G20/G33/G2E/G33/G56/G20/GB1/G20/G30/G2E/G33/G56/G29 NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. V CC = 3.3V, T A = +25 °C, and are not production tested. I CCDC = 90mA (Typ.) 3. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions ” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Refer to Chip Enable Truth Table. 7. Industrial temperature: for other speeds, packages and powers contact your sales office. 70V27X15 Com'l Only 70V27X20 Com'l Only 70V27X25 Com'l Only ICC Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Disabled SEM = V IH f = fMAX(3) COM'L S L 170 170 260 225 165 165 255 220 145 145 245 210 mA IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 145 145 280 245 ISB1 Standby Current (Bo th Ports - TTL Level Inputs) CE L = CER = V IH SEMR = SEML = V IH f = fMAX(3) COM'L S L mA IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ ISB2 Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = V IH COM'L S L 115 115 160 145 105 105 155 140 150 135 mA IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 170 150 ISB3 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CE L and CER > VCC - 0.2V VIN > VCC - 0.2V or SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 1.0 0.2 1.0 0.2 mA IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 1.0 0.2 ISB4 Full Standby Current (One Port - All CMOS Level Inputs) CE "A" < 0.2V and CE"B" > VCC - 0.2V (5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 115 115 155 140 105 105 150 135 145 130 mA IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 170 145 3603 tbl 10a

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G41/G43/G20/G45/G6C/G65/G63/G74/G72/G69/G63/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73/G20/G4F/G76/G65/G72/G20/G74/G68/G65/G20/G4F/G70/G65/G72/G61/G74/G69/G6E/G67 /G54/G65/G6D/G70/G65/G72/G61/G74/G75/G72/G65/G20/G61/G6E/G64/G20/G53/G75/G70/G70/G6C/G79/G20/G56/G6F/G6C/G74/G61/G67/G65/G20/G52/G61/G6E/G67/G65/G28/G34/G2C/G20/G36/G29 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = V IL and SEM = V IH. To access semaphore, CE= V IH and SEM = V IL. 4. 'X' in part numbers indicates power rating (S or L). 5. Refer to Chip Enable Truth Table. 6. Industrial temperature: for other speeds, packages and powers contact your sales office. 70V27X15 Com'l Only 70V27X20 Com'l Only 70V27X25 Com'l Only READ CYCLE tPU Chip Enable to Power Up Time (2,5) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2,5) ____ 15 ____ 20 ____ 25 ns tSOP Semaphore Flag Update Pulse ( OE or SEM)1 0 ____ 10 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 15 ____ 20 ____ 35 ns 3603 tbl 12a 70V27X35 Com'l & Ind 70V27X55 Com'l Only UnitSymbol Parameter Min. Max. Min. Max. READ CYCLE tAA Address Access Time ____ 35 ____ 55 ns tACE Chip Enable Access Time (3) ____ 35 ____ 55 ns tABE Byte Enable Access Time (3) ____ 35 ____ 55 ns tAOE Output Enable Access Time ____ 20 ____ 30 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tLZ Output Low-Z Time(1,2) 3 ____ 3 ____ ns tHZ Output High-Z Time(1,2) ____ 20 ____ 25 ns tPU Chip Enable to Power Up Time (2,5) 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2,5) ____ 45 ____ 50 ns tSOP Semaphore Flag Update Pulse ( OE or SEM)1 5 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 45 ____ 65 ns 3603 tbl 12b

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20/G52/G65/G61/G64/G20/G43/G79/G63/G6C/G65/G73/G28/G35/G29 /G54/G69/G6D/G69/G6E/G67/G20/G6F/G66/G20/G50/G6F/G77/G65/G72/G2D/G55/G70/G20/G50/G6F/G77/G65/G72/G2D/G44/G6F/G77/G6E NOTES: 1. Timing depends on which signal is asserted last: CE, OE, LB, or UB. 2. Timing depends on which signal is de-asserted first: CE, OE, LB, or UB. 3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simu ltaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last t AOE, tACE, tAA or t BDD. 5. SEM = V IH. 6. Refer to Chip Enable Truth Table. tRC R/W CE ADDR tAA OE UB,LB 3603 drw 05 (4) tACE (4) tAOE (4) tABE (4) (1)tLZ tOH (2)tHZ (3,4) tBDD DATA OUT BUSYOUT VALID DATA (4) (6) CE 3603 drw 06 tPU ICC ISB tPD 50% 50% (6)

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM CE= V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire t EW time. Refer to Chip Enable Truth Table. 4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage and temperature, the actual t DH will always be smaller than the actual t OW. 5. 'X' in part numbers indicates power rating (S or L). 6. Industrial temperature: for other speeds, packages and powers contact your sales office. /G41/G43/G20/G45/G6C/G65/G63/G74/G72/G69/G63/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73/G20/G4F/G76/G65/G72/G20/G74/G68/G65 /G4F/G70/G65/G72/G61/G74/G69/G6E/G67/G20/G54/G65/G6D/G70/G65/G72/G61/G74/G75/G72/G65/G20/G61/G6E/G64/G20/G53/G75/G70/G70/G6C/G79/G20/G56/G6F/G6C/G74/G61/G67/G65/G28/G35/G2C/G36/G29 Symbol Parameter 70V27X15 Com'l Only 70V27X20 Com'l Only 70V27X25 Com'l Only WRI TE CYCLE tEW Chip Enable to End-of-Write (3) 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ ns tWZ Write Enable to Output in High-Z (1,2) ____ 10 ____ 10 ____ 15 ns tOW Output Active from End-of-Write (1, 2,4) 0 ____ 0 ____ 0 ____ ns 3603 tbl 13a Symbol Parameter 70V27X35 Com'l & Ind 70V27X55 Com'l Only UnitMin. Max. Min. Max. WRI TE CYCLE tEW Chip Enable to End-of-Write (3) 30 ____ 45 ____ ns tAW Address Valid to End-of-Write 30 ____ 45 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ ns tWP Write Pulse Width 25 ____ 40 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 20 ____ 30 ____ ns tHZ Output High-Z Time (1,2) ____ 20 ____ 25 ns tWZ Write Enable to Output in High-Z (1,2) ____ 20 ____ 25 ns tOW Output Active from End-of-Write (1, 2,4) 0 ____ 0 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ ns tSPS SEM Flag Contention Window 5 ____ 5 ____ ns 3603 tbl 13b

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G54/G69/G6D/G69/G6E/G67/G20/G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20/G57/G72/G69/G74/G65/G20/G43/G79/G63/G6C/G65/G20/G4E/G6F/G2E/G20/G31/G2C/G20/G52/G2FW/G20/G43/G6F/G6E/G74/G72/G6F/G6C/G6C/G65/G64/G20/G54/G69/G6D/G69/G6E/G67/G28/G31/G2C/G35/G2C/G38/G29 NOTES: 1. R/ W or CE or UB and LB must be HIGH during all address transitions. 2. A write occurs during the overlap (t EW or t WP) of a LOW CE and a LOW R/ W for memory array writing cycle. 3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/ W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW) to allow the I/O drivers to turn off and data to be placed on the bus for the required t DW. If OE is HIGH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. 9. To access RAM, CE = V IL and SEM = V IH. To access semaphore, CE = V IH and SEM = V IL. t EW must be met for either condition. 10. Refer to Chip Enable Truth Table. /G54/G69/G6D/G69/G6E/G67/G20/G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20/G57/G72/G69/G74/G65/G20/G43/G79/G63/G6C/G65/G20/G4E/G6F/G2E/G20/G32/G2C/G20CE/G2C/G20UB/G2C/G20LB/G20/G43/G6F/G6E/G74/G72/G6F/G6C/G6C/G65/G64/G20/G54/G69/G6D/G69/G6E/G67/G28/G31/G2C/G35/G29 R/W tWC tHZ tAW tWRtAS tWP DATA OUT (2) tWZ tDW tDH tOW OE ADDRESS DATA IN (6) (4) (4) (7) UB orLB 3603 drw 07 (9) CE orSEM (9,10) (7) (3) 3603 drw 08 tWC tAS tWR tDW tDH ADDRESS DATA IN R/W tAW tEW UB orLB (3)(2)(6) CE orSEM (9,10) (9)

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G54/G69/G6D/G69/G6E/G67/G20/G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20/G53/G65/G6D/G61/G70/G68/G6F/G72/G65/G20/G52/G65/G61/G64/G20/G61/G66/G74/G65/G72/G20/G57/G72/G69/G74/G65/G20/G54/G69/G6D/G69/G6E/G67/G2C/G20/G45/G69/G74/G68/G65/G72/G20/G53/G69/G64/G65/G28/G31/G29 NOTES: 1. D OR = D OL = V IL, CER = CEL = V IH, or both UB & LB = V IH (refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/ W"A" or SEM"A" going HIGH to R/W "B" or SEM"B" going HIGH. 4. If t SPS is not satisfied, there is no guarantee which side will be granted the semaphore flag. SEM 3603 drw 09 tAW tEW tSOP I/O VALID ADDRESS tSAA R/W tWR tOH tACE VALID ADDRESS DATA VALIDIN DATA OUT tDW tWP tDHtAS tSWRD tAOE Read CycleWrite Cycle A0-A2 OE VALID(2) NOTES: 1. CE = V IH or UB and LB = V IH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table. 2. "DATA OUT VALID" represents all I/O's (I/O 0-I/O15) equal to the semaphore value. SEM"A" 3603 drw 10 tSPS MATCH R/W"A" MATCH A0"A"-A2"A" SIDE “A” (2) SEM"B" R/W"B" A0"B"-A2"B" SIDE (2) “B” /G54/G69/G6D/G69/G6E/G67/G20/G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20/G53/G65/G6D/G61/G70/G68/G6F/G72/G65/G20/G57/G72/G69/G74/G65/G20/G43/G6F/G6E/G74/G65/G6E/G74/G69/G6F/G6E/G28/G31/G2C/G33/G2C/G34/G29

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/ S = V IH)". 2. To ensure that the earlier of the two ports wins. 3. t BDD is a calculated parameter and is the greater of 0, t WDD – tWP (actual), or t DDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L). 7. Industrial temperature: for other speeds, packages and powers contact your sales office. /G41/G43/G20/G45/G6C/G65/G63/G74/G72/G69/G63/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73/G20/G4F/G76/G65/G72/G20/G74/G68/G65 /G4F/G70/G65/G72/G61/G74/G69/G6E/G67/G20/G54/G65/G6D/G70/G65/G72/G61/G74/G75/G72/G65/G20/G61/G6E/G64/G20/G53/G75/G70/G70/G6C/G79/G20/G56/G6F/G6C/G74/G61/G67/G65/G20/G52/G61/G6E/G67/G65/G28/G36/G2C/G37/G29 70V27X15 Com'l Only 70V27X20 Com'l Only 70V27X25 Com'l Only BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 15 ____ 20 ____ 25 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 25 ns tBAC BUSY Access Time from Chip Enable Low ____ 15 ____ 20 ____ 25 ns tBDC BUSY Disable Time from Chip Enable High ____ 15 ____ 20 ____ 25 ns tAPS Arbitration Priority Set-up Time (2 ) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data (3 ) ____ 17 ____ 35 ____ 35 ns BUSY TIMING (M/S=VIL) PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1 ) ____ 30 ____ 45 ____ 55 ns tDDD Write Data Valid to Read Data Delay(1 ) ____ 25 ____ 30 ____ 50 ns 3603 tbl 14a 70V27X35 Com'l & Ind 70V27X55 Com'l Only UnitSymbol Parameter Min. Max. Min. Max. BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 35 ____ 45 ns tBDA BUSY Disable Time from Address Not Matched ____ 35 ____ 45 ns tBAC BUSY Access Time from Chip Enable Low ____ 35 ____ 45 ns tBDC BUSY Disable Time from Chip Enable High ____ 35 ____ 45 ns tAPS Arbitration Priority Set-up Time (2 ) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data (3 ) ____ 40 ____ 50 ns tWH Write Hold After BUSY(5 ) 25 ____ 25 ____ ns BUSY TIMING (M/S=VIL) tWB BUSY Input to Write (4 ) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5 ) 25 ____ 25 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1 ) ____ 65 ____ 85 ns tDDD Write Data Valid to Read Data Delay(1 ) ____ 60 ____ 80 ns 3603 tbl 14b

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G54/G69/G6D/G69/G6E/G67/G20/G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20/G57/G72/G69/G74/G65/G20/G77/G69/G74/G68/G20/G50/G6F/G72/G74/G2D/G74/G6F/G2D/G50/G6F/G72/G74/G20/G52/G65/G61/G64/G20/G61/G6E/G64/G20BUSY/G28/G32/G2C/G35/G29/G20/G20/G28/G4D/G2FS/G20/G3D/G20/G56/G49/G48/G29/G28/G34/G29 NOTES: 1. t WH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/ W"B", until BUSY"B" goes HIGH. 3. t WB is only for the "Slave" version. /G54/G69/G6D/G69/G6E/G67/G20/G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G57/G72/G69/G74/G65/G20/G77/G69/G74/G68/G20BUSY/G20/G28/G4D/G2FS/G20/G3D/G20/G56/G49/G4C/G29 3603 drw 11 tDW tAPS ADDR "A" tWC DATA OUT "B" MATCH tWP R/W"A" DATA IN "A" ADDR "B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD (3) tWDD tBAA NOTES: 1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (SLAVE). 2. CEL = CER = V IL (refer to Chip Enable Truth Table). 3. OE = V IL for the reading port. 4. If M/ S = V IL (SLAVE), then BUSY is an input. Then for this example BUSY "A"= V IH and BUSY "B"= input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 3603 drw 12 R/W "A" BUSY"B" tWP tWB R/W"B" tWH (2) (3) (1)

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20BUSY/G20/G41/G72/G62/G69/G74/G72/G61/G74/G69/G6F/G6E/G20/G43/G79/G63/G6C/G65/G20/G43/G6F/G6E/G74/G72/G6F/G6C/G6C/G65/G64/G20/G62/G79/G20/G41/G64/G64/G72/G65/G73/G73/G20/G4D/G61/G74/G63/G68 /G54/G69/G6D/G69/G6E/G67/G20/G28/G4D/G2FS/G20/G3D/G20/G56/G49/G48/G29/G28/G31/G29 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If t APS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 3. Refer to Chip Enable Truth Table. /G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20BUSY/G20/G41/G72/G62/G69/G74/G72/G61/G74/G69/G6F/G6E/G20/G43/G6F/G6E/G74/G72/G6F/G6C/G6C/G65/G64/G20/G62/G79/G20CE/G20/G20/G54/G69/G6D/G69/G6E/G67/G20/G28/G4D/G2FS/G20/G3D/G20/G56/G49/G48/G29/G28/G31/G2C/G33/G29 NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. Industrial temperature: for other speeds, packages and powers contact your sales office. /G41/G43/G20/G45/G6C/G65/G63/G74/G72/G69/G63/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73/G20/G4F/G76/G65/G72/G20/G74/G68/G65 /G4F/G70/G65/G72/G61/G74/G69/G6E/G67/G20/G54/G65/G6D/G70/G65/G72/G61/G74/G75/G72/G65/G20/G61/G6E/G64/G20/G53/G75/G70/G70/G6C/G79/G20/G56/G6F/G6C/G74/G61/G67/G65/G20/G52/G61/G6E/G67/G65/G28/G31/G2C/G32/G29 3603 drw 13 ADDR "A" and "B" ADDRESSES MATCH CE"B" BUSY"B" tAPS tBAC tBDC (2) CE"A" 3603 drw 14 ADDR "A" ADDRESS "N" ADDR "B" BUSY"B" tAPS tBAA tBDA (2) MATCHING ADDRESS "N" Symbol Parameter 70V27X15 Com'l Only 70V27X20 Com'l Only 70V27X25 Com'l Only INTERRUPT TIMING 3603 tbl 15a Symbol Parameter 70V27X35 Com'l &Ind 70V27X55 Com'l Only UnitMin. Max. Min. Max. INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 30 ____ 40 ns tINR Interrupt Reset Time ____ 35 ____ 45 ns 3603 tbl 15b

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G57/G61/G76/G65/G66/G6F/G72/G6D/G20/G6F/G66/G20/G49/G6E/G74/G65/G72/G72/G75/G70/G74/G20/G54/G69/G6D/G69/G6E/G67/G28/G31/G2C/G35/G29 /G54/G72/G75/G74/G68/G20/G54/G61/G62/G6C/G65/G20/G49/G56/G20/G97/G20/G49/G6E/G74/G65/G72/G72/G75/G70/G74/G20/G46/G6C/G61/G67/G28/G31/G2C/G34/G29 NOTES: 1. Assumes BUSY L = BUSYR =V IH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = V IL, then no change. 4. Refer to Chip Enable Truth Table. NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal ( CE or R/ W) is asserted last. 4. Timing depends on which enable signal ( CE or R/ W) is de-asserted first. 5. Refer to Chip Enable Truth Table. 3603 drw 15 ADDR "A" INTERRUPT SET ADDRESS CE"A" R/W"A" tAS tWC tWR (3) (4) tINS (3) INT"B" (2) 3603 drw 16 ADDR "B" INTERRUPT CLEAR ADDRESS CE"B" OE"B" tAS tRC (3) tINR (3) INT"B" (2) Left Port Right Port FunctionR/WL CEL OEL A14L-A0L INTL R/WR CER OER A14R-A0R INTR L L X 7FFF X X X X X L(2) Set Right INTR Flag X X XXX X L L 7 F F F H(3) Reset Right INTR Flag XXX X L(3) L L X 7FFE X Set Left INTL Flag X L L 7FFE H(2) X X X X X Reset Left INTL Flag 3603 tbl 16

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G54/G72/G75/G74/G68/G20/G54/G61/G62/G6C/G65/G20/G56/G20/G97/G20/G41/G64/G64/G72/G65/G73/G73/G20BUSY/G20/G41/G72/G62/G72/G69/G74/G72/G61/G74/G69/G6F/G6E/G28/G34/G29 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V27 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If t APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. Refer to Chip Enable Truth Table. /G54/G72/G75/G74/G68/G20/G54/G61/G62/G6C/G65/G20/G56/G49/G20/G97/G20/G45/G78/G61/G6D/G70/G6C/G65/G20/G6F/G66/G20/G53/G65/G6D/G61/G70/G68/G6F/G72/G65/G20/G50/G72/G6F/G63/G75/G72/G65/G6D/G65/G6E/G74/G20/G53/G65/G71/G75/G65/G6E/G63/G65/G28/G31/G2C/G32/G29 NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V27. 2. There are eight semaphore flags written to via I/O 0 and read from all the I/O's (I/O 0-I/O15). These eight semaphores are addressed by A 0 - A 2. /G46/G75/G6E/G63/G74/G69/G6F/G6E/G61/G6C/G20/G44/G65/G73/G63/G72/G69/G70/G74/G69/G6F/G6E The IDT70V27 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V27 has an automatic power down feature controlled by CE 0 and CE1. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. /G49/G6E/G74/G65/G72/G72/G75/G70/G74/G73 If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INT L) is asserted when the right port writes to memory location 7FFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table IV. The left port clears the interrupt through access of address location 7FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFF (HEX) and to clear the interrupt flag ( INTR), the right port must read the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is user-defined since it is an addressable SRAM location. If the interrupt func-tion is not used, address locations 7FFE and 7FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table IV for the interrupt operation. /G42/G75/G73/G79/G20/G4C/G6F/G67/G69/G63 Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on Inputs Outputs FunctionCEL CER A0L-A14L A0R-A14R BUSYL(1) BUSYR(1) X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit (3) 3603 tbl 17 Functions D0 - D15 Left D 0 - D15 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 3603 tbl 1 8

to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. prevented to a port by tying the BUSY pin for that port LOW. resulting array requires the use of an external AND gate. Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V27 RAMs. array and another master indicating BUSY on one other side of the array. inhibit the write operations from the other port for the other part of the word. corrupted data in the slave. an additional 8 address locations dedicated to binary semaphore flags. Dual-Port RAM or any other shared resource. flexibility in system architecture. the left side should succeed in gaining control.

0 D Q

the other address pins has any effect. state in the middle of a read cycle due to a write cycle from the other side. gap between the read and write cycles. Figure 4. IDT70V27 Semaphore Logic semaphores alone do not guarantee that access to a resource is secure. or misinterpreted, a software error can easily happen. to assure that they will be free when needed.

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G4F/G72/G64/G65/G72/G69/G6E/G67/G20/G49/G6E/G66/G6F/G72/G6D/G61/G74/G69/G6F/G6E NOTE: 1. Industrial temperature range is available on selected TQFP packages in low power. For other speeds, packages and powers contact your sales office. A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) Commercial (0°Ct o+ 7 0°C) Industrial (-40°Ct o+ 8 5°C) S L Standard Power Low Power XXXXX Device Type 512K (32K x 16) 3.3V Dual-Port RAM70V27 IDT 3603 drw 19 Speed in nanoseconds Commercial Commercial Commercial Commercial & Industrial Commercial 144-pin fpBGA (BF144-1) 100-pin TQFP (PN100-1) 108-pin PGA (G108-1) BF PF G /G50/G72/G65/G6C/G69/G6D/G69/G6E/G61/G72/G79/G20/G44/G61/G74/G61/G73/G68/G65/G65/G74/G3A "PRELIMINARY' datasheets contain descriptions for products that are in early release.

Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM /G44/G61/G74/G61/G73/G68/G65/G65/G74/G20/G44/G6F/G63/G75/G6D/G65/G6E/G74/G20/G48/G69/G73/G74/G6F/G72/G79 12/3/98: Initiated Document History Converted to new format Typographical and cosmetic changes Added fpBGA information Added 15ns and 20ns speed grades Updated DC Electrical Characteristics Added additional notes to pin configurations 4/2/99: Page 5 Fixed typo in Table III 8/1/99: Page 3 Changed package body height from 1.1mm to 1.4mm 8/30/99: Page 1 Changed 660mW to 660 µW 4/25/00: Replaced IDT logo Page 2 Made pin correction Changed ±200mV to 0mV in notes 1/12/01: Page 1 Fixed page numbering; copywright Page 6 Increated storage temperature parameter Clarified T A Parameter Page 7 and8 DC Electrical parameters–changed wording from "open" to "disabled" Removed Preliminary status CORPORATE HEADQUARTERS for SALES: for Tech Support:

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