DSSHA1 MAXIM | Alldatasheet

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Technical content

Features

♦ SHA-1 Computations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz) ♦ Area Estimate is 102,256µm2 in TSMC CL018G (0.18µm Generic Process) ♦ Dedicated Hardware-Accelerated SHA-1 Engine for Generating MACs ♦ 64-Byte RAM for Message Input ♦ Five 32-Bit Registers to Read MAC Result ♦ Available in Synthesizable Verilog® ♦ Made as a Low-Level Module to be Instantiated by a Top-Level Module ♦ Includes Test Bench DSSHA1 Memory-Mapped SHA-1 Coprocessor DESIGN MODULE MICROPROCESSOR ASIC—TOP-LEVEL MODULE R 3.3V MODULE DSSHA1 MODULE DS1WM DS28E01-100 Typical Operating Circuit 19-5870; Rev 0; 5/11 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Verilog is a registered trademark of Gateway Design Automation Corp.

Description

The DSSHA1 is a synthesizable, memory-mapped SHA-1 coprocessor that includes a 64-byte general- purpose RAM that stores the 64-byte message. The input message is used to compute the SHA-1 MAC. The DSSHA1 input and output port signals are designed to internally connect to a 32-bit bus. Implementation in an ASIC or FPGA provides a SHA-1 hash only to be compared to the SHA-1 hash of Maxim devices. By a positive comparison result, authentication security is achieved between a host system and slave accessories. Maxim has numerous SHA-1 slave devices such as the DS28E01-100 and DS28E10 1-Wire ® devices, the DS1961S and DS1963S i Button® devices, and the DS28CN01 I2C device. Figure 1 shows how the 64-byte SHA-1 message is inserted into the RAM. Triggering the input signal RUN_SHA to logic-high starts the SHA-1 computation. The output BUSY signal indicates an occurring com- putation. Upon completion of the BUSY signal, the result registers contain the 20-byte message digest for reading. Memory-Mapped SHA-1 Coprocessor DSSHA1 SHA-1 RAM

64 BYTES

RESULT_DATAO A, B, C, D, E DATAO[31:0] BUSY RAM_DATAI RAM_ADDR[4] RAM_ADDR RAM_DATAO RSTRSTZ CLK WRZ CSZ DATAI[31:0] ADDR[4:0] RUN_SHA Figure 1. Block Diagram 1-Wire and iButton are registered trademarks of Maxim Integrated Products, Inc.

Detailed Register Description Input Buffer (00h to 0Fh) The SHA-1 engine receives the data to be processed through the 64-byte input buffer. This buffer holds the 512-bit message that the SHA-1 engine processes to generate a MAC. Secret and other message data are contained in the input buffer. Security of the secret is a task left for the designer. The format of the data is defined by each Maxim SHA-1 slave device. MAC Result (10h to 14h) A 20-byte MAC of a SHA-1 computation resides in the MAC result address space. Device Operation The typical use of the DSSHA1 in an application involves writing, reading, and running the SHA-1 engine, and using the MAC result to externally compare this block to the MAC of a 1-Wire SHA-1 device. All these activities are controlled through the 32-bit inter- face with separate data input and output lines to easily connect to the internal bus inside an ASIC or FPGA. The SHA-1 Engine Control section explains the data input and output format and how to instruct the SHA-1 engine to perform a MAC computation. DSSHA1 Memory-Mapped SHA-1 Coprocessor Signal Description NAME TYPE* FUNCTION CLK I Clock. On the positive edge, data on signals DATAI[31:0] and DATAO[31:0] are clocked in and out. RSTZ I Active-Low Reset. The RSTZ signal is evaluated at each interval of the positive edge of the CLK signal. It is necessary to do a reset before every load of a 512-bit message and MAC computation. CSZ I Active-Low Chip Select. This signal must be low for all accesses to registers and memory. WRZ I Active-Low Write Enable. This signal must be low during all write operations. ADDR[4:0] I Address[4:0]. These five signals are the address signals. DATAI[31:0] I Data Bus Input. These 32 signals are the input data bus. DATAO[31:0] O Data Bus Output. These 32 signals are the output data bus. BUSY O Busy. When high, this signal indicates that the SHA-1 coprocessor is busy performing a computation. There should be no data accesses while this signal is high. RUN_SHA I Run SHA-1. This signal must only be one clock period wide and initiates a SHA-1 computation upon the positive edge of the CLK signal. Memory Map ADDRESS (HEX) TYPE ACCESS FUNCTION 0x00 to 0x0F RAM Read/Write 64-Byte Buffer Input. This is the 512-bit input block that usually includes the 64-bit slave device secret and a 448-bit input message consisting of a random challenge and various data. 0x10 to 0x14 Registers Read 20-Byte Result. This is the MAC for comparison to the received MAC of the SHA-1 slave device. *I = Input, O = Output.

2 illustrates data flow into and out of the SHA-1 engine. contain the MAC result for reading.

20 BYTES

Figure 2. Data Flow Diagram Table 1. Input Message Format Mx = Input buffer of SHA-1 engine; 0 ≤ t ≤ 15; 32-bit words with a start address at 00h and ending address at 0Fh.

hold the MAC are mapped to the respective locations. this test message will be the values in Table 3. Table 2. Output Message Format Table 3. SHA-1 Input for “abc” Test Packet Mx = Input buffer of SHA-1 engine; 0 ≤ t ≤ 15; 32-bit words with a start address at 00h and ending address at 0Fh.

  • Gate count 6,423 (NAND 2x1 used for calculation).
  • Area is 85,470µm2 without routing.
  • Area is 102,256µm2 with routing estimate. Library used for estimate: ARM TSMC CL018G (0.18um generic process) 1.8V SAGE-X standard cells library, version 2004q3v1. The ARM part number is A0082. This is a free, foundry- sponsored library that can be obtained at: www.arm.com/products/physicalip/productsservices.html. Verification The industry typically denotes the level of verification of an IP block with the following conventions:
  • Gold IP has been to target silicon.
  • Silver IP has been to target silicon in FPGA.
  • Bronze IP has been verified in silicon models with logical timing closure.
  • In-development IP has not yet been verified. Note: The DSSHA1 has achieved silver status. Deliverables The DSSHA1 package comes complete with:
  • Verilog HDL
  • Verilog Test Bench
  • Readme Information on Setup and Scripts The free DSSHA1 IP is available by request at https://support.maxim-ic.com/1-Wire Memory-Mapped SHA-1 Coprocessor

Memory-Mapped SHA-1 Coprocessor Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 5/11 Initial release —