DSP56724 FREESCALE | Alldatasheet
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Data Sheet: Technical Data Document Number: DSP56724EC Rev. 1, 12/2008 © Freescale Semiconductor, Inc., 2008. All rights reserved. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. DSP56724/DSP56725 DSP56725 80-Pin LQFP 14 mm × 14 mm 0.65 mm pitch DSP56724 144-Pin LQFP 20 mm × 20 mm 0.5 mm pitch See Ta ble 19. The Symphony DSP56724/DSP56725 Multi-Core Audio Processors are part of the DSP5672x family of programmable CMOS DSPs, designed using dual DSP56300 24-bit cores. The DSP56724 is intended for consumer and professional audio applications that require high performance for audio processing. In addition, the DSP56724 is ideally suited for applications that need the capability to expand memory off-chip or to interface to external parallel peripherals. Potential applications include A/V receivers, DVD Receivers, Home Theater in a Box (HTIB), and professional audio equipment including portable recording equipment, musical instruments, guitar amplifiers and pedals. The DSP56724 offers customers flexibility in their designs by providing a more cost-effective alternative to the DSP56720 while maintaining pin compatibility. The DSP56725 is intended for automotive and audio applications that require high performance for audio processing. Potential applications include A/V receivers, DVD Receivers, Home Theater in a Box (HTIB), and automotive amplifiers and entertainment systems. The DSP56725 offers customers flexibility in their designs by providing a more cost-effective alternative to the DSP56721 while maintaining pin compatibility. The DSP56724/DSP56725 devices provide a wealth of on-chip audio processing functions, via a plug and play software architecture system that supports audio decoding algorithms, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, among others. The DSP56724/DSP56725 devices also support various matrix decoders and sound field processing algorithms. With two DSP56300 cores, a single DSP56724/ DSP56725 device can replace dual-DSP designs, saving costs while meeting high MIPs requirements. Legacy peripherals from the previous DSP5636x/37x families are included, as are a variety of new modules available in the DSP5672x family. Modules from the DSP56720 are included, such as an Asynchronous Sample Rate Converter (ASRC), an Inter-Core Communication (ICC) module, an External Memory Controller (EMC) to support SDRAM (DSP56724 only), and a Sony/Philips Digital Interface (S/PDIF) transceiver. The DSP56724/DSP56725 devices offer up to 250 million instructions per second (MIPs) per core using an internal 250 MHz clock. The DSP56724/ DSP56725 products are high density CMOS devices with 3.3 V inputs and outputs. The DSP56724 block diagram is shown in Figure 1; the DSP56725 block diagram is shown in Figure 2. NOTE This document contains information on a new product. Specifications and information herein are subject to change without notice. Finalized specifications may be published after further characterization and device qualifications are completed. Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors
Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor2 Table of Contents 1.1.8 Reset, Stop, Mode Select, and Interrupt Timing . . 10
1.2.2 Serial Host Interface (SHI) I
2C Protocol Timing . . 20
4.1.1 Pinout for DSP56724 144-Pin Plastic
4.1.2 Pinout for DSP56725 80-Pin Plastic
Figure 1. DSP56724 Block Diagram Figure 2. DSP56725 Block Diagram
2 JTAGs
1 Electrical Characteristics
1.1 Chip-Level Conditions
Table 1 provides a quick reference to the subsections in this section.
1.1.1 Maximum Ratings
adding a maximum to a minimum represents a condition that can never exist. Table 1. Chip-Level Conditions should be taken to avoid exceeding maximum voltage ratings. The suggested value for a pull-up or pull-down resistor is 4.7 k Ω.
Table 2 lists the maximum ratings. Table 2. Maximum Ratings
- Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the maximum rating may affect device reliability or cause permanent damage to the device.
1.1.2 Thermal Characteristics
Table 3 lists the thermal characteristics.
1.1.3 Power Requirements
as shown in Figure 3, connected between the DSP56724/DSP56725 IO_VDD and Core_VDD power pins. Figure 3. Prevent High Current Conditions by Using External Schottky Diode of Core_VDD, as shown in Figure 4. Figure 4. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD Table 3. Thermal Characteristics
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
- Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
- Thermal resistance between the die and the case top surface as measured by the cold plate method
Figure 5. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD
1.1.4 DC Electrical Characteristics
Table 4. DC Electrical Characteristics
1.1.5 AC Electrical Characteristics
OL and VOH reference levels set at 0.4 V and 2.4 V , respectively.
1.1.6 Internal Clocks
Table 5 lists the internal clocks.
- The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In
- In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (that is, not allowed
Table 5. Internal Clocks
1 Comparison Frequency Fref 2 — 8 MHz Fref = Fin/NR
2 Input Clock Frequency
Table 4. DC Electrical Characteristics (Continued)
1.1.7 External Clock Operation
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see Figure 6. Figure 6. Using the On-Chip Oscillator (Figure 7). When the external square wave source is connected to EXTAL, the XTAL pin is not used. Figure 7. External Clock Timing
3 PLL VCO Frequency Fvco 200 — 500 MHz Fvco = (Fin * NF)/NR
4 Output Clock Frequency [1] [2]
5 System Clock Frequency
- Maximum frequency of 200 MHz supported at 0.95 V < V
Table 5. Internal Clocks (Continued) Note: The midpoint is 0.5 (V IH + VIL).
Table 6 lists the clock operation.
1.1.8 Reset, Stop, Mode Select, and Interrupt Timing
Table 7 lists the reset, stop, mode select, and interrupt timing. Table 6. Clock Operation
6 EXT AL input high 1
7 EXT AL input low
8 EXT AL cycle time
9 Instruction cycle time
- Measured at 50% of the input transition.
- The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
- Maximum frequency of 200 MHz supported at 0.95 V < V
Table 7. Reset, Stop, Mode Select, and Interrupt Timing
10 Delay from RESET assertion to all pins at reset value 3 —— 1 1 n s
11 Required RESET duration4
13 Syn reset deassert delay time
14 Mode select setup time — 10 — ns
15 Mode select hold time — 12 — ns
16 Minimum edge-triggered interrupt request assertion width — 7 — ns
17 Minimum edge-triggered interrupt request deassertion width — 4 — ns
18 Delay from interrupt trigger to interrupt code execution 10 × T
19 Duration of level sensitive IRQA assertion to ensure interrupt
21 Interrupt Requests Rate 1
22 DMA Requests Rate
- When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
- For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined
to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 us.
- Periodically sampled and not 100% tested.
minimize this state to the shortest possible duration. Table 7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)
Figure 10 shows external interrupt timing (negative edge-triggered). Figure 10. External Interrupt Timing (Negative Edge-Triggered) Figure 11 shows MODE select set-up and hold time diagram. Figure 11. MODE Select Set-Up and Hold Time
1.2 Module-Level Specifications
Table 8 provides a quick reference to the subsections of this section. Table 8. Module-Level Specifications
1.2.1 Serial Host Interface SPI Protocol Timing
Table 9 lists the serial host interface SPI protocol timing. Table 9. Serial Host Interface SPI Protocol Timing
26 Serial clock rise/fall time Master
27 SS assertion to first SCK edge
28 Last SCK edge to SS not asserted Slave Bypassed — 12 — ns
29 Data input valid to SCK edge (data input
30 SCK last sampling edge to data input not
31 SS assertion to data out active Slave — — 5 — ns
32 SS deassertion to data high impedance 2 Slave — — — 9 ns
33 SCK edge to data out valid
34 SCK edge to data out not valid
35 SS assertion to data out valid
Table 9. Serial Host Interface SPI Protocol Timing (Continued)
36 First SCK sampling edge to HREQ output
37 Last SCK sampling edge to HREQ output
38 SS deassertion to HREQ output not
41 HREQ in deassertion to last SCK sampling
42 First SCK edge to HREQ in not asserted
- Periodically sampled, not 100% tested
- All times assume noise free inputs.
- All times assume internal clock frequency of 200 MHz.
- SHI_1 specs match those of SHI
- Slave timings should equal the serial clock high period + the serial clock low period.
Figure 15 shows the SPI slave timing (CPHA = 1). Figure 15. SPI Slave Timing (CPHA = 1)
1.2.2 Serial Host Interface (SHI) I 2C Protocol Timing
Table 10 lists the SHI I2C protocol timing diagram. Table 10. SHI I2C Protocol Timing
44 SCL clock frequency F
50 SCL and SDA rise time 7 TR — 1000 — 300 ns
52 Data set-up time T SU;DA T 250 — 100 — ns
54 DSP clock frequency
55 SCL low to data out valid T
57 HREQ in deassertion to last SCL edge (HREQ in
58 First SCL sampling edge to HREQ output
59 Last SCL edge to HREQ
Table 10. SHI I2C Protocol Timing (Continued)
1.2.3 Programming the SHI I 2C Serial Clock
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
60 HREQ in assertion to first SCL edge
61 First SCL edge to HREQ
- Pull-up resistor: R P (min) = 1.5 kΩ
- Capacitive load: C b (max) = 50 pF
- All times assume noise free inputs
- All times assume internal clock frequency of 200 MHz
- SHI_1 specs match those of SHI
- The numbers listed are based on the module/pad design and its characteristics during output. The module is compliant with
2C standard, so the module should receive I 2C bus compliant signal without any issue.
Figure 16 shows the I2C timing diagram. Figure 16. I2C Timing
1.2.4 Enhanced Serial Audio Interface Timing
Table 11 lists the enhanced serial audio interface timing. Table 11. Enhanced Serial Audio Interface Timing
62 Clock cycle 5 tSSICC 4 × Tc
63 Clock high period
64 Clock low period
65 SCKR rising edge to FSR out (bl) high — — —
66 SCKR rising edge to FSR out (bl) low — — —
67 SCKR rising edge to FSR out (wr) high 6 —— —
68 SCKR rising edge to FSR out (wr) low 6 —— —
69 SCKR rising edge to FSR out (wl) high — — —
70 SCKR rising edge to FSR out (wl) low — — —
71 Data in setup time before SCKR (SCK in synchronous
78 SCKT rising edge to FST out (bl) high — — —
79 SCKT rising edge to FST out (bl) low — — —
80 SCKT rising edge to FST out (wr) high 6 —— —
81 SCKT rising edge to FST out (wr) low 6 —— —
82 SCKT rising edge to FST out (wl) high — — —
83 SCKT rising edge to FST out (wl) low — — —
84 SCKT rising edge to data out enable from high impedance — — —
85 SCKT rising edge to transmitter #0 drive enable assertion — — —
86 SCKT rising edge to data out valid — — —
87 SCKT rising edge to data out high impedance 7 —— —
88 SCKT rising edge to transmitter #0 drive enable
Table 11. Enhanced Serial Audio Interface Timing (Continued)
94 Flag output valid after SCKT rising edge — — —
95 HCKR/HCKT clock cycle — 2 × T
- SCKT(SCKT pin) = transmit clock
- For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
- The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
before last bit clock of the first word in frame.
- Periodically sampled and not 100% tested.
- ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
Figure 20 shows the ESAI HCKR timing diagram. Figure 20. ESAI HCKR Timing
1.2.5 GPIO Timing
Table 12 lists the GPIO timing. Table 12. GPIO Timing
100 Fsys edge to GPIO out valid (GPIO out delay time) 2 —— 7 n s
101 Fsys edge to GPIO out not valid (GPIO out hold time) 2 —— 7 n s
102 Fsys In valid to EXTAL edge (GPIO in set-up time) 2 —2 — n s
103 Fsys edge to GPIO in not valid (GPIO in hold time) 2 —0 — n s
104 Minimum GPIO pulse high width 2 × TC 10 — ns
105 Minimum GPIO pulse low width 2 × TC 10 — ns
- Simulation numbers-subject to change.
Figure 21 shows the GPIO timing diagram. Figure 21. GPIO Timing
1.2.6 JTAG Timing
Table 13 lists the JTAG timing. Table 13. JTAG Timing
- All timings apply to OnCE module data transfers because it uses the JT AG port as an interface.
Figure 24 shows the test access port timing diagram. Figure 24. Test Access Port Timing Diagram
1.2.7 Watchdog Timer Timing
Table 14 lists the watchdog timer timings. Table 14. Watchdog Timer Timing
1.2.8 S/PDIF Timing
Table 15 lists the S/PDIF timing. Figure 25 shows the SRCK timing diagram. Figure 25. SRCK Timing Figure 26 shows the STCLK timing diagram. Figure 26. STCLK Timing Table 15. S/PDIF Timing
1.2.9 EMC Timing Specifications—DSP56724
Table 16 lists the EMC timing parameters with EMC PLL enabled. The DSP56725 device does not have an EMC module. Table 16. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)
Table 17 lists the EMC timing parameters with EMC PLL bypassed. Table 17. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4) Note: Negative hold time means the signal could be invalid before LCLK rising edge.
2 Functional Description and Application Information
functional and applications information.
3 Ordering Information
Table 19 shows the ordering information for the DSP56724/DSP56725 devices. Contact your local Freescale sales representative for ordering information.
4 Package Information
This section provides package and pinout information. Table 20 is a quick reference to the package outline drawings. Table 19. Ordering Information Table 20. Package Outline Drawings DSP56724 144-pin plastic LQFP See Section 4.2, “144-Pin Package Outline Drawing,” on page 41. DSP56725 80-pin plastic LQFP See Section 4.3, “80-Pin Package Outline Drawing,” on page 43.
4.1 Pinout and Package Information
4.1.1 Pinout for DSP56724 144-Pin Plastic LQFP Package
Figure 30. DSP56724 144-Pin Package Pinout
108 IO_GND
107 IO_VDD
106 WDT
105 PINIT/NMI
104 TDO
103 TDI
102 TCK
101 TMS
100 SDO2_1/SDI3_1
99 SDO3_1/SDI2_1
98 SDO4_1/SDI1_1
97 SDO5_1/SDI0_1
96 CORE_GND
95 CORE_VDD
94 FSR
93 SCKR
92 HCKR
91 SCKT
90 FST
89 HCKT
88 SDO2/SDI3
87 SDO3/SDI2
86 SDO4/SDI1
85 SDO5/SDI0
84 SPDIFOUT1
83 SPDIFIN1
82 IO_GND
81 IO_VDD
80 EXTAL
79 XTAL
78 PLLP_GND
77 PLLD_GND
76 PLLD_VDD
75 PLLA_GND
74 PLLA_VDD
73 PLLP_VDD
144 SCAN
143 MODA0/IRQA
142 MODB0/IRQB
141 MODC0/PLOCK
140 MODD0/PG1
139 FSR_3
138 SCKR_3
137 HCKR_3
136 SCKT_3
135 FST_3
134 HCKT_3
133 IO_GND
132 IO_VDD
131 CORE_GND
130 CORE_VDD
129 MODA1/IRQC
128 MODB1/IRQD
127 MODC1/NMI_1
126 MODD1/PG2
125 SDO2_2/SDI3_2
124 SDO3_2/SDI2_2
123 SDO4_2/SDI1_2
122 SDO5_2/SDI0_2
121 SDO2_3/SDI3_3
120 SDO3_3/SDI2_3
119 SDO4_3/SDI1_3
118 SDO5_3/SDI0_3
117 SS/HA2
116 HREQ/PH4
115 SCK/SCL
114 MOSI/HA0
113 MISO/SDA
112 SS_1/HA2_1
111 RESET
110 CORE_GND
109 CORE_VDD
4.1.2 Pinout for DSP56725 80-Pin Plastic LQFP Package
Figure 31. DSP56725 80-Pin Package
4.1.3 Pin Multiplexing
60 WDT
59 PINIT/NMI
58 TDO
57 TDI
56 TCK
55 TMS
54 CORE_GND
53 CORE_VDD
52 SDO4/SDI1
51 SDO5/SDI0
50 IO_GND
49 IO_VDD
48 EXTAL
47 XTAL
46 PLLP_GND
45 PLLD_GND
44 PLLD_VDD
43 PLLA_GND
42 PLLA_VDD
41 PLLP_VDD
80 SCAN
79 MODA0/IRQA
78 MODB0/IRQB
77 MODC0/PLOCK
76 IO_GND
75 IO_VDD
74 CORE_GND
73 CORE_VDD
72 MODA1/IRQC
71 MODB1/IRQD
70 MODC1/NMI_1
69 SS/HA2
68 HREQ/PH4
67 SCK/SCL
66 MOSI/HA0
65 MISO/SDA
64 SS_1/HA2_1
63 RESET
62 CORE_GND
61 CORE_VDD
The 144-pin package outline drawing is shown in Figure 32 and Figure 33. Figure 32. 144-Pin Package Outline Drawing
Figure 33. 144-Pin Package Outline Drawing (continued) 1 All dimensions are in millimeters. 3 Datums B, C and D to be determined at datum plane H. 4 The top package body size may be smaller than the bottom package size by a maximum of 0.1 mm. are maximum body size dimensions including mold mismatch. space between protrusion and an adjacent lead shall be 0.07 mm. 7 These dimensions are determined at the seating plane, datum A.
The 80-pin package outline drawing is shown in Figure 34 and Figure 35. Figure 34. 80-Pin Package Outline Drawing
Figure 35. 80-Pin Package Outline Drawing (continued) 1 Dimensioning and tolerancing per ASME Y .14.5M–1994. 2 Controlling dimension: millimeter. 4 Datum E, F and to be determined at datum plane H. 5 Dimensions to be determined at seating plane C. are determined at datum plane H. space between protrusion and adjacent lead or protrusion is 0.07mm.
5 Product Documentation
for the latest information).
6 Revision History
Table 22 summarizes revisions to this document. Table 21. DSP56724 / DSP56725 Documentation Table 22. Revision History 12, and for No. 16, changed 4 to 7. I n Ta bl e 9, “Serial Host Interface SPI Protocol Timing,” updated values. to 1000 and 300; in addition, updated the values for note 1. No. 83, changed 20 to 15; for No. 86, changed 18 to 25; for No. 87, changed 21 to 25. “LSYNC_IN (except LGTA/LUPWAIT),” changed 2 to 3. “LCLK to output high impedance for LAD [23:0],” changed 9 to 8.1. 0 6/2008 Initial public release.
Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor46 THIS PAGE INTENTIONALL Y BLANK
Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 47 THIS PAGE INTENTIONALL Y BLANK
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