DSP56720 FREESCALE | Alldatasheet
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Data Sheet: Technical Data © Freescale Semiconductor, Inc., 2006, 2007. All rights reserved. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. DSP56720 / DSP56721 DSP56720 144-Pin LQFP 20 mm x 20 mm 0.5 mm pitch DSP56721 80-Pin LQFP 14 mm x 14 mm 0.65 mm pitch 144-Pin LQFP 20 mm x 20 mm 0.5 mm pitch
Ordering Information
DSP56720 DSPA56720AG 20 mm x 20 mm DSPB56720AG 20 mm x 20 mm DSP56720 DSPA56721AG 20 mm x 20 mm DSPB56721AG 20 mm x 20 mm DSPA56721AF 14 mm x 14 mm DSPB56721AF 14 mm x 14 mm Document Number: DSP56720 Rev.1, 12/2007 The Symphony DSP56720/DSP56721 Multi-Core Audio Processors are part of the DSP5672x family of programmable CMOS DSPs, designed using multiple DSP56300 24-bit cores. The DSP56720/DSP56721 devices are intended for automotive, consumer, and professional audio applications that require high performance for audio processing. In addition, the DSP56720 is ideally suited for applications that need the capability to expand memory off-chip or to interface to external parallel peripherals. Potential applications include A/V receivers, HD-DVD and Blu-Ray players, car audio/amplifiers, and professional recording equipment. The DSP56720/DSP56721 devices excel at audio processing for automotive and consumer audio applications requiring high MIPs. Higher MIPs and memory requirements are driven by the new high-definition audio standards (Dolby Digital+, Dolby TrueHD, DTS-HD, for example) and the desire to process multiple audio streams. In addition, DSP56720/DSP56721 devices are optimal for the professional audio market requiring audio recording, signal processing, and digital audio synthesis. The DSP56720/DSP56721 processors provide a wealth of on-chip audio processing functions, via a plug and play software architecture system that supports audio decoding algorithms, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, among others. The DSP56720/DSP56721 devices also support various matrix decoders and sound field processing algorithms. With two DSP56300 cores, a single DSP56720 or DSP56721 device can replace dual-DSP designs, saving costs while meeting high MIPs requirements. Legacy peripherals from the previous DSP5636x/7x families are included, as well as a variety of new modules. Included among the new modules are an Asynchronous Sample Rate Converter (ASRC), Inter-Core Communication (ICC), an External Memory Controller (EMC) to support SDRAM, and a Sony/Philips Digital Interface (S/PDIF). The DSP56720/DSP56721 offer 200 million instructions per second (MIPs) per core using an internal 200 MHz clock. The DSP56720/DSP56721 are high density CMOS devices with 3.3 V inputs and outputs. The DSP56720 device is slightly different than the DSP56721 device—the DSP56720 includes an external memory interface while the DSP56721 device does not. The DSP56720 block diagram is shown in Figure 1; the DSP56721 block diagram is shown in Figure 2. SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor2 Table of Contents 1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package . .4 1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package . . .6 1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package . .7
2.1.8 Reset, Stop, Mode Select, and Interrupt Timing14
2.2.1 Serial Host Interface (SHI) SPI Protocol Timing 18
2.2.2 Serial Host Interface (SHI) I
2C Protocol Timing.24
2.2.4 Enhanced Serial Audio Interface (ESAI) Timing 27
Figure 1. DSP56720 Block Diagram Figure 2. DSP56721 Block Diagram
2 JTAGs
1 Pin Assignments
assignments of a specific device in a specific package, please see sections 1.2–1.1. For more detailed information about signals, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM).
1.1 Pinout for DSP56720 144-Pi n Plastic LQFP Package
For the pinout of the DSP56720 144-pin plastic LQFP package, see Figure 3. Table 1. Pin Assignments by Package
Figure 3. DSP56720 144-Pin Package Pinout
108 IO_GND
107 IO_VDD
106 WDT
105 PINIT/NMI
104 TDO
103 TDI
102 TCK
101 TMS
100 SDO2_1/SDI3_1
99 SDO3_1/SDI2_1
98 SDO4_1/SDI1_1
97 SDO5_1/SDI0_1
96 CORE_GND
95 CORE_VDD
94 FSR
93 SCKR
92 HCKR
91 SCKT
90 FST
89 HCKT
88 SDO2/SDI3
87 SDO3/SDI2
86 SDO4/SDI1
85 SDO5/SDI0
84 SPDIFOUT1
83 SPDIFIN1
82 IO_GND
81 IO_VDD
80 EXTAL
79 XTAL
78 PLLP_GND
77 PLLD_GND
76 PLLD_VDD
75 PLLA_GND
74 PLLA_VDD
73 PLLP_VDD
144 SCAN
143 MODA0/IRQA
142 MODB0/IRQB
141 MODC0/PLOCK
140 MODD0/PG1
139 FSR_3
138 SCKR_3
137 HCKR_3
136 SCKT_3
135 FST_3
134 HCKT_3
133 IO_GND
132 IO_VDD
131 CORE_GND
130 CORE_VDD
129 MODA1/IRQC
128 MODB1/IRQD
127 MODC1/NMI_1
126 MODD1/PG2
125 SDO2_2/SDI3_2
124 SDO3_2/SDI2_2
123 SDO4_2/SDI1_2
122 SDO5_2/SDI0_2
121 SDO2_3/SDI3_3
120 SDO3_3/SDI2_3
119 SDO4_3/SDI1_3
118 SDO5_3/SDI0_3
117 SS/HA2
116 HREQ/PH4
115 SCK/SCL
114 MOSI/HA0
113 MISO/SDA
112 SS_1/HA2_1
111 RESET
110 CORE_GND
109 CORE_VDD
1.2 Pinout for DSP56721 80-Pi n Plastic LQFP Package
For the pinout of the DSP56721 80-pin plastic LQFP package, see Figure 4. Figure 4. DSP56721 80-Pin Package
60 WDT
59 PINIT/NMI
58 TDO
57 TDI
56 TCK
55 TMS
54 CORE_GND
53 CORE_VDD
52 SDO4/SDI1
51 SDO5/SDI0
50 IO_GND
49 IO_VDD
48 EXTAL
47 XTAL
46 PLLP_GND
45 PLLD_GND
44 PLLD_VDD
43 PLLA_GND
42 PLLA_VDD
41 PLLP_VDD
80 SCAN
79 MODA0/IRQA
78 MODB0/IRQB
77 MODC0/PLOCK
76 IO_GND
75 IO_VDD
74 CORE_GND
73 CORE_VDD
72 MODA1/IRQC
71 MODB1/IRQD
70 MODC1/NMI_1
69 SS/HA2
68 HREQ/PH4
67 SCK/SCL
66 MOSI/HA0
65 MISO/SDA
64 SS_1/HA2_1
63 RESET
62 CORE_GND
61 CORE_VDD
1.3 Pinout for DSP56721 144-Pi n Plastic LQFP Package
For the pinout of the DSP56721 144-pin plastic LQFP package, see Figure 5. Figure 5. DSP56721 144-Pin Package Pinout
1.4 Pin Multiplexing
105 PIINT/NMI
100 SCKR_1
99 FSR_1
98 SCKT_1
97 FST_1
96 SDO0_1
95 SDO1_1
94 IO_GND
93 IO_VDD
92 CORE_GND
91 CORE_VDD
90 SDO0
89 SDO1
88 SDO4/SDI1
87 SDO5/SDI0
86 SPDIFOUT1/H12/HAD12
85 SPDIFIN1/H8/HAD8
84 HACK/HRRQ
83 HOREQ/HTRQ
139 IO_GND
138 IO_VDD
137 CORE_GND
136 CORE_VDD
135 MODA1/IRQC
134 MODB1/IRQD
133 MODC1/NMI_1
132 MODD1/PG2
131 FSR_2
130 SCKR_2
129 SCKT_2
128 FST_2
127 SDO0_2
126 SDO1_2
125 IO_GND
124 IO_VDD
123 SDO0_3
122 SDO1_3
120 HREQ/PH4
119 SCK/SCL
118 MOSI/HA0
117 MISO/SDA
116 SS_1/HA2_1
115 HREQ_1/PH4_1
114 SCK_1/SCL_1
113 MOSI_1/HA0_1
112 MISO_1/SDA_1
2 Electrical Characteristics
For electrical characteristics, see Table 2.
2.1 Chip-Level Conditions
For a summary of chip-level conditions in this section, see Table 3.
2.1.1 Maximum Ratings
For maximum ratings, see Table 4. value for a pull-up or pull-down resistor is 4.7 kΩ. adding a maximum to a minimum represents a condition that can never exist. Table 2. Electrical Characteristics Table 3. Chip-Level Conditions
Table 4. Maximum Ratings
- Absolute maximum ratings are stress rati ngs only, and functional operation at the maximum is not guaranteed. Stress beyond the
maximum rating may affect device reliability or cause permanent damage to the device.
- Operating temperature qualifi ed for consumer applications. TJ = TA + qJA x Power. Variables used were
Core Current = 900mA, I/O Current = 200mA, Core Voltage = 1.1 V, I/O Voltage = 3.6 V, TA = 105°C.
- If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneous
2.1.2 Thermal Characteristics
For thermal characteristics, see Table 5.
2.1.3 Power Requirements
as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins. Figure 6. Prevent High Current Conditions by Using External Schottky Diode of Core_VDD, as shown in Figure 7. Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD Table 5. Thermal Characteristics
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
- Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
- Thermal resistance between the die and the case top surface as measured by the cold plate method
Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD
2.1.4 DC Electrical Characteristics
For DC electrical characteristics, see Table 6. Table 6. DC Electrical Characteristics
2.1.5 AC Electrical Characteristics
measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V , respectively.
2.1.6 Internal Clocks
Internal clock characteristics are listed in Table 7.
200 MHz
- The Current Consumption section provides a formula to comput e the estimated current requirements in Normal mode. In order
reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.0V, VDD_IO = 3.3V at TJ = 25°C. Maximum internal supply current is measured with VCORE_VDD = 1.10V, VIO_VDD) = 3.6V at TJ = 125°C.
- In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float).
Table 7. Internal Clocks
1 Comparison Frequency Fref 2 – 8 MHz Fref = Fin/NR
2 Input Clock Frequency Fin Max = 200 MHz
3 PLL VCO Frequency Fvco 200 – 400 MHz Fvco = (Fin * NF)/NR
4 Output Clock Frequency [1]
5 Duty Cycle – 40 50 60 % Fvco=
200 MHz – 400 MHz
Table 6. DC Electrical Characteristics (Continued)
2.1.7 External Clock Operation
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in Figure 9. Figure 9. Using the On-Chip Oscillator (Figure 10). When the external square wave source is connected to EXTAL, the XTAL pin is not used. Figure 10. External Clock Timing Table 8. Clock Operation
1 EXTAL input high 1
Note: The midpoint is 0.5 (V IH + VIL).
2.1.8 Reset, Stop, Mode Se lect, and Interrupt Timing
For reset, stop, mode select, and interrupt timing, see Table 9.
2 EXTAL input low 1
3 EXTAL cycle time
4 Instruction cycle time
- Measured at 50% of the input transition.
- The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock
as long as the minimum high time and low time requirements are met.
- A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56720/DSP56721 being
Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters
10 Delay from RESET assertion to all pins at reset value3 – – 11 ns
11 Required RESET duration4
13 Syn reset deassert delay time
16 Minimum edge-triggered interrupt request assertion width – 4 – ns
17 Minimum edge-triggered interrupt request deassertion width – 4 – ns
18 Delay from interrupt trigger to interrupt code execution 10 × T
Table 8. Clock Operation (Continued)
19 Duration of level sensitive IRQA assertion to ensure interrupt service
21 Interrupt Requests Rate 1
22 DMA Requests Rate
- When using fast interrupts and when IRQA , IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
interrupts. Long interrupts are recommended when using Level-sensitive mode.
- For PLL disable, if using an external clock (PCTL Bit 13 = 1) , no stabilization delay is required and recovery time will be defined by
locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 μs.
- Periodically sampled and not 100% tested.
- RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When
Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered) Figure 14. MODE Select Set-Up and Hold Timing Diagram
2.2 Module-Level Specifications
For a summary of the module-level specifications in this section, see Table 10. Table 10. Module-Level Specifications
2.2.1 Serial Host Interface (SHI) SPI Protocol Timing
See Table 11 for SHI SPI protocol timing parameters and Figure 15, Figure 16, Figure 17, and Figure 18 for timing diagrams. Table 11. Serial Host Interface SPI Protocol Timing Parameters
26 Serial clock rise/fall time Master
27 SS assertion to first SCK edge
28 Last SCK edge to SS not asserted Slave Bypassed – 12 – ns
29 Data input valid to SCK edge (data input
30 SCK last sampling edge to data input not
31 SS assertion to data out active Slave – – 5 – ns
32 SS deassertion to data high impedance2 Slave – – – 9 ns
33 SCK edge to data out valid
34 SCK edge to data out not valid
35 SS assertion to data out valid
Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)
36 First SCK sampling edge to HREQ output
37 Last SCK sampling edge to HREQ output
38 SS deassertion to HREQ output not
41 HREQ in deassertion to last SCK sampling
42 First SCK edge to HREQ in not asserted
- Periodically sampled, not 100% tested.
- All times assume noise free inputs.
- All times assume internal clock frequency of 200 MHz.
- SHI_1 specs match those of SHI.
Figure 15. SPI Master Timing Diagram (CPHA = 0)
Figure 16. SPI Master Timing Diagram (CPHA = 1)
Figure 17. SPI Slave Timing Diagram (CPHA = 0)
Figure 18. SPI Slave Timing Diagram (CPHA = 1)
2.2.2 Serial Host Interface (SHI) I 2C Protocol Timing
See Table 12 for SHI I2C protocol timing parameters and Figure 19 for the timing diagram. Table 12. SHI I2C Protocol Timing Parameters
44 SCL clock frequency F
52 Data set-up time T SU;DAT 250 – 100 – ns
54 DSP clock frequency
57 HREQ in deassertion to last SCL edge
58 First SCL sampling edge to HREQ output
59 Last SCL edge to HREQ
60 HREQ
61 First SCL edge to HREQ is not asserted
- Pull-up resistor: R P (min) = 1.5K Ohms.
- Capacitive load: C b (max) = 50 pF .
- All times assume noise free inputs.
- All times assume internal clock frequency of 200 MHz.
- SHI_1 specs match those of SHI.
Table 12. SHI I2C Protocol Timing Parameters (Continued)
2.2.3 Programming the SHI I 2C Serial Clock
divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed. Figure 19. I2C Timing Diagram
2.2.4 Enhanced Serial Audio Interface (ESAI) Timing
See Table 13 For ESAI timing parameters and Figure 20, Figure 21, Figure 22, and Figure 23 for timing diagrams. Table 13. Enhanced Serial Audio Interface Timing Parameters
62 Clock cycle 5 tSSICC 4 × Tc
63 Clock high period
64 Clock low period
65 SCKR rising edge to FSR out (bl) high – – –
66 SCKR rising edge to FSR out (bl) low – – –
67 SCKR rising edge to FSR out (wr) high 6 –– –
68 SCKR rising edge to FSR out (wr) low 6 –– –
69 SCKR rising edge to FSR out (wl) high – – –
70 SCKR rising edge to FSR out (wl) low – – –
71 Data in setup time before SCKR (SCK in synchronous
78 SCKT rising edge to FST out (bl) high – – –
79 SCKT rising edge to FST out (bl) low – – –
80 SCKT rising edge to FST out (wr) high 6 –– –
81 SCKT rising edge to FST out (wr) low 6 –– –
82 SCKT rising edge to FST out (wl) high – – –
83 SCKT rising edge to FST out (wl) low – – –
84 SCKT rising edge to data out enable from high
85 SCKT rising edge to transmitter #0 drive enable
86 SCKT rising edge to data out valid – – –
87 SCKT rising edge to data out high impedance 7 –– –
88 SCKT rising edge to transmitter #0 drive enable
94 Flag output valid after SCKT rising edge – – –
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
95 HCKR/HCKT clock cycle – 2 x T C 10 – – ns
- SCKT(SCKT pin) = transmit clock
- For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
- The word-relative frame sync signal waveform relative to the cl ock operates in the same manner as the bit-length frame sync signal
clock of the first word in frame.
- Periodically sampled and not 100% tested.
- ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
Figure 20. ESAI Transmitter Timing Diagram frame. In normal mode, the output flag state is asserted for the entire frame period.
Figure 23. ESAI HCKR Timing
2.2.5 Timer Timing
See Table 14 for timer timing parameters and Figure 24 for the timing diagram. Figure 24. TIO Timer Event Input Restrictions Diagram
2.2.6 GPIO Timing
See Table 15 for general purpose input and output (GPIO) timing and Figure 25 for the timing diagram. Table 14. Timer Timing Parameters
- TIMER_1 specs match those of TIMER
Table 15. GPIO Timing Parameters
100 Fsys edge to GPIO out valid (GPIO out delay time)2 –– 7 n s
101 Fsys edge to GPIO out not valid (GPIO out hold time) 2 –– 7 n s
102 Fsys In valid to EXTAL edge (GPIO in set-up time) 2 –2 – n s
103 Fsys edge to GPIO in not valid (GPIO in hold time) 2 –0 – n s
104 Minimum GPIO pulse high width 2 x TC 10 – ns
Figure 25. GPIO Timing Diagram
2.2.7 JTAG Timing
See Table 16 for joint test action group (JTAG) timing parameters, and Figure 26, Figure 27, and Figure 28 for timing diagrams.
105 Minimum GPIO pulse low width 2 x TC 10 – ns
Table 16. JTAG Timing Parameters Table 15. GPIO Timing (Continued)Parameters
Figure 28. Test Access Port Timing Diagram
2.2.8 Watchdog Timer Timing
For watchdog timer timing, see Table 17.
2.2.9 Host Data Interface (HDI24) Timing
Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, and Figure 35 for timing diagrams. Table 17. Watchdog Timer Timing Parameters Table 18. HDI24 Timing Parameters
317 Read data strobe assertion width 3
318 Read data strobe deassertion width 3
319 Read data strobe deassertion width 3 after “Last Data Register” reads4,5,
320 Write data strobe assertion width 7
321 Write data strobe deassertion width 7
324 Host data input setup time before write data strobe deassertion 7
325 Host data input hold time after write data strobe deassertion 7
326 Read data strobe assertion to output data active from high impedance 3
327 Read data strobe assertion to output data valid 3
328 Read data strobe deassertion to output data high impedance 3
329 Output data hold time after read data strobe deassertion 3
336 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data
337 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe
338 Delay from read data strobe deassertion to
Table 18. HDI24 Timing Parameters (Continued)
339 Delay from write data strobe deassertion to
340 Delay from data strobe assertion to
341 Delay from data strobe assertion to
342 Delay from DMA HACK deassertion to HOREQ assertion ns
343 Delay from DMA HACK assertion to HOREQ deassertion
344 Delay from DMA HACK assertion to HOREQ deassertion for “Last Data
- In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable.
- The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
- The “last data register” is t he register at address $7, which is the last location to be read or written in data transfers.
- This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without
first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
- This timing is applicable only if two consecutive reads from one of these registers are executed.
- The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
- The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data
- The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.
- In this calculation, the host request signal is pull ed up by a 4.7 kW resistor in the open-drain mode.
- HDI24_1 specs match those of HDI24.
Figure 31. HDI24 Write Timing Diagram, Non-Multiplexed Bus
Figure 32. HDI24 Read Timing Diagram, Multiplexed Bus
Figure 35. HDI24 Host DMA Read Timing Diagram
2.2.10 S/PDIF Timing
Table 19. S/PDIF Timing Parameters
Figure 36. S/PDIF SRCK Timing Diagram Figure 37. S/PIDF STCLK Timing Diagram
2.2.11 EMC Timing (DSP56720 only)
Table 21, and Table 22; for timing diagrams, see Figure 38, Figure 39, and Figure 40. Table 20. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)
Figure 38. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV] = 2)
Table 21. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
- A negative hold time means that the signal could be invalid before the LCLK rising edge.
Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4) Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
- A negative hold time means that the signal could be invalid before the LCLK rising edge.
Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) (Continued)
3 Functional Description and Application Information
See the DSP56720 Reference Manual (DSP56720RM) for detailed functional and applications information.
4 Hardware Design Considerations
5 Ordering Information
Table 23 provides ordering information for both the DSP56720 and DSP56721.
6 Package Information
For the outline drawings of available device packages, see Table 24 and sections 6.1–6.2. For the 80-pin package outline drawings, see Figure 41 and Figure 42. Table 23. Ordering Information Table 24. Package Outline Drawings
Figure 41. 80-Pin Package Outline Drawing (1 of 2)
Figure 42. 80-Pin Package Outline Drawing (2 of 2)
For the 144-pin package drawings, see figures Figure 43 and Figure 44. Figure 43. 144-Pin Package Outline Drawing (1 of 2)
Figure 44. 144-Pin Package Outline Drawing (2 of 2)
7 Product Documentation
types are available at: http://www.freescale.com. Documentation is available from a local Freescale Semiconductor, Inc. (the source for the latest information). 24-bit core processor and instruction set. DSP56720 Product Brief (DSP56720PB). Brief description of the DSP56720 device. DSP56721 Product Brief (DSP56721PB). Brief description of the DSP56721 device.
8 Revision History
Table 25 summarizes revisions to this document. Table 25. Revision History 1 December 2007 Initial public release.
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