DSP56307UM/D

DSP56307 MOTOROLA | Alldatasheet

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SEMICONDUCTOR TECHNICAL DATA DSP56307 Order this document by: DSP56307DS/D Rev. 0, 8/10/98 ©1998 MOTOROLA, INC. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notification. Product Preview 24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56307, a member of the DSP56300 family of programmable digital signal processors (DSPs), supports wireless infrastructure applications with general filtering operations. The on-chip enhanced filter coprocessor (EFCOP) processes filter algorithms in parallel with core operation, thus increasing overall DSP performance and efficiency. Like the other family members, the DSP56307 uses a high-performance, single-clock-cycle-per-instruction engine (code-compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access controller, as in Figure 1 . The DSP56307 offers performance at 100 million instructions (MIPS) per second using an internal 100 MHz clock with a 2.5 volt core and independent 3.3 volt input/output power. Figure 1 DSP56307 Block Diagram PLL OnCE™ Clock Generator Internal Data Bus Switch YAB XAB PAB YDB XDB PDB GDB MODB/ IRQB MODC/ IRQC External Data Bus Switch MODD/ IRQD DSP56300 616 24-Bit DDB DAB Peripheral Core YM_EB XM_EB PM_EB PIO_EB Expansion Area JTAG RESET MODA/ IRQA PINIT/NMI 2EXTAL XTAL Address Control Data Address Generation Unit Six Channel DMA Unit Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 · 24+56fi 56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter Power Mngmnt. External Bus Interface and I - Cache Control AA1367 Memory Expansion Area DE Program RAM

16 K · 24 or

24 K · 24

Timer (Program RAM

15 K · 24 and

1024 · 24) Bootstrap ROM

ii DSP56307 Technical Data MOTOROLA TABLE OF CONTENTS Data Sheet Conventions OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) ÒassertedÓ Means that a high true (active high) signal is high or that a low true (active low) signal is low ÒdeassertedÓ Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage* PIN True Asserted V IL/VOL PIN False Deasserted V IH/VOH PIN True Asserted V IH/VOH PIN False Deasserted V IL/VOL Note: *Values for V IL, VOL, VIH, and VOH are defined by individual product specifications. FOR TECHNICAL ASSISTANCE: Telephone: 1-800-521-6274 Email: dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com

Features

MOTOROLA DSP56307 Technical Data iii High-Performance DSP56300 Core ¥ 100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and

3.3 V I/O

¥ Object code compatible with the DSP56000 core ¥ Highly parallel instruction set ¥ Data arithmetic logic unit (ALU) Ð Fully pipelined 24 x 24-bit parallel multiplier-accumulator Ð 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) Ð Conditional ALU instructions Ð 24-bit or 16-bit arithmetic support under software control ¥ Program control unit (PCU) Ð Position independent code (PIC) support Ð Addressing modes optimized for DSP applications (including immediate offsets) Ð On-chip instruction cache controller Ð On-chip memory-expandable hardware stack Ð Nested hardware DO loops Ð Fast auto-return interrupts ¥ Direct memory access (DMA) Ð Six DMA channels supporting internal and external accesses Ð One-, two-, and three- dimensional transfers (including circular buffering) Ð End-of-block-transfer interrupts Ð Triggering from interrupt lines and all peripherals ¥ Phase-locked loop (PLL) Ð Allows change of low power divide factor (DF) without loss of lock Ð Output clock with skew elimination ¥ Hardware debugging support Ð On-Chip Emulation (OnCE Ô ) module Ð Joint test action group (JTAG) test access port (TAP) Ð Address trace mode reflects internal Program RAM accesses at the external port

iv DSP56307 Technical Data MOTOROLA DSP56307 Enhanced Filtering Coprocessor (EFCOP) The on-chip filtering and echo-cancellation coprocessor runs in parallel to the DSP core. On-Chip Memories ¥ 64 K on-chip RAM total ¥ Program RAM, Instruction Cache, X data RAM, and Y data RAM size is programmable: ¥ 192 x 24-bit bootstrap ROM Off-Chip Memory Expansion ¥ Data memory expansion to two 256K 24-bit word memory spaces (or up to two 4 M 24-bit word memory spaces by using the address attribute AA0ÐAA3 signals) ¥ Program memory expansion to one 256K 24-bit words memory space (or up to one 4 M 24-bit word memory space by using the address attribute AA0ÐAA3 signals) ¥ External memory expansion port ¥ Chip Select Logic for glueless interface to static random access memory (SRAMs) ¥ On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs) Program RAM Size Instruction Cache Size X Data RAM Size* Y Data RAM Size* Instruction Cache Switch Mode MSW1 MSW0 16K 24-bit 0 24K 24-bit 24K 24-bit disabled disabled 0/1 0/1 1 K 24-bit 1024 24-bit 24K 24-bit 24K 24-bit enabled disabled 0/1 0/1 48K 24-bit 0 8K 24-bit 8K 24-bit disabled enabled 0 0 47K 24-bit 1024 24-bit 8K 24-bit 8K 24-bit enabled enabled 0 0 40K 24-bit 0 12K 24-bit 12K 24-bit disabled enabled 0 1 39K 24-bit 1024 24-bit 12K 24-bit 12K 24-bit enabled enabled 0 1 32K 24-bit 0 16K 24-bit 16K 24-bit disabled enabled 1 0 31K 24-bit 1024 24-bit 16K 24-bit 16K 24-bit enabled enabled 1 0 24K 24-bit 0 20K 24-bit 20K 24-bit disabled enabled 1 1 23K 24-bit 1024 24-bit 20K 24-bit 20K 24-bit enabled enabled 1 1 *Includes 4K 24-bit shared memory (i.e., memory shared by the core and the EFCOP)

MOTOROLA DSP56307 Technical Data v On-Chip Peripherals ¥ Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (e.g., ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs ¥ Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) ¥ Serial communications interface (SCI) with baud rate generator ¥ Triple timer module ¥ Up to 34 programmable general purpose input/output (GPIO) pins, depending on which peripherals are enabled Reduced Power Dissipation ¥ Very low power CMOS design ¥ Wait and Stop low-power standby modes ¥ Fully static logic, operation frequency down to 0 Hz (dc) ¥ Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) TARGET APPLICATIONS The DSP56307 is intended for applications requiring a large amount of on-chip memory, such as wireless infrastructure applications. The EFCOP may be used to accelerate general filtering applications, such as echo-cancellation applications, correlation, and general purpose convolution-based algorithms.

vi DSP56307 Technical Data MOTOROLA DSP56307 Product Documentation PRODUCT DOCUMENTATION The three documents listed in the following table are required for a complete description of the DSP56307 and are necessary to design properly with the part. Documentation is available from one of the following locations. (See the back cover for detailed information.) ¥ A local Motorola distributor ¥ A Motorola semiconductor sales office ¥ A Motorola Literature Distribution Center ¥ The World Wide Web (WWW) See Additional Support in the DSP56300 Family Manual for detailed information on the multiple support options available to you. DSP56307 Documentation Name Description Order Number DSP56300 Family Manual Detailed description of the DSP56300 family processor core and instruction set DSP56300FM/AD DSP56307 User’s Manual Detailed functional description of the DSP56307 memory configuration, operation, and register programming DSP56307UM/D DSP56307 Technical Data DSP56307 features list and physical, electrical, timing, and package specifications DSP56307/D

MOTOROLA DSP56307 Technical Data 1-1 SECTION 1 SIGNALS/CONNECTIONS SIGNAL GROUPINGS The input and output signals of the DSP56307 are organized into functional groups as shown in Table 1-1 Figure 1-1 diagrams the DSP56307 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Table 1-1 DSP56307 Functional Signal Groupings Functional Group Number of Signals Power (V CC )2 0 Ground (GND) 19 Clock 2 PLL 3 Address bus Port A Data bus 24 Bus control 13 Interrupt and mode control 5 Host interface (HI08) Port B Enhanced synchronous serial interface (ESSI) Ports C and D Serial communication interface (SCI) Port E Timer 3 OnCE/JTAG Port 6 Note: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. 2. Port B signals are the HI08 port signals multiplexed with the GPIO signals. 3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. 4. Port E signals are the SCI port signals multiplexed with the GPIO signals.

1-2 DSP56307 Technical Data MOTOROLA Signals/Connections Signal Groupings Figure 1-1 Signals Identified by Functional Group DSP56307

18 External

(ESSI0) Timers3 PLL OnCE/JTA G Port Power Inputs: PLL Core Logic I/O Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer A0–A17 D0–D23 AA0–AA3/ RAS0 –RAS3 RD WR TA BR BG BB CAS BCLK BCLK TCK TDI TDO TMS TRST DE CLKOUT PCAP After Reset NMI VCCP VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS Serial Communications Interface (SCI) Port2 Grounds: PLL PLL Internal Logic Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer GND P GND P1 GND Q GND A GND D GND C GND H GND S Interrupt/M ode Control MODA MODB MODC MODD RESET Host Interface (HI08) Port1 Non-Multiplexe d Bus H0–H7 HA0 HA1 HA2 HCS/ HCS Single DS HRW HDS /HDS Single HR HREQ /HREQ HACK /HACK RXD TXD SCLK SC00–SC02 SCK0 SRD0 STD0 TIO0 TIO1 TIO2 EXTAL XTAL Clock Enhanced Synchronous Serial Interface Port 1 (ESSI1)2 SC10–SC12 SCK1 SRD1 STD1 Multiplexed Bus HAD0–HAD7 HAS /HAS HA8 HA9 HA10 Double DS HRD/HRD HWR /HWR Double HR HTRQ /HTRQ HRRQ /HRRQ Port B GPIO PB0–PB7 PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 Port E GPIO PE0 PE1 PE2 Port C GPIO PC0–PC2 PC3 PC4 PC5 Port D GPIO PD0–PD2 PD3 PD4 PD5 Timer GPIO TIO0 TIO1 TIO2 Port A AA0601 Note: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or double Host Request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0–PB15). Signals with dual designations (e.g., HAS /HAS) have configurable polarity. 2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0–PC5), Port D GPIO signals (PD0–PD5), and Port E GPIO signals (PE0–PE2), respectively. 3. TIO0–TIO2 can be configured as GPIO signals. IRQA IRQB IRQC IRQD PINIT

3 RESET

MOTOROLA DSP56307 Technical Data 1-3 POWER Table 1-2 Power Inputs Power Name Description V CCP PLL Power ÑV CCP is V CC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the V CC power rail. V CCQL Quiet Core (Low) Power ÑV CCQL is an isolated power for the core processing logic. This input must be isolated externally from all other chip power inputs. The user must provide adequate external decoupling capacitors. V CCQH Quiet External (High) Power ÑV CCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs, except V CCQL . The user must provide adequate decoupling capacitors. V CCA Address Bus Power ÑV CCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs, except V CCQL . The user must provide adequate external decoupling capacitors. V CCD Data Bus Power ÑV CCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs, except V CCQL . The user must provide adequate external decoupling capacitors. V CCC Bus Control Power ÑV CCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs except V CCQL . The user must provide adequate external decoupling capacitors. V CCH Host Power ÑV CCH is an isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs except V CCQL The user must provide adequate external decoupling capacitors. V CCS ESSI, SCI, and Timer Power ÑV CCS is an isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs, except V CCQL . The user must provide adequate external decoupling capacitors.

1-4 DSP56307 Technical Data MOTOROLA Signals/Connections Ground GROUND Table 1-3 Grounds Ground Name Description GND P PLL Ground ÑGND P is ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. V CCP should be bypassed to GND P by a 0.47 m F capacitor located as close as possible to the chip package. GND PLL Ground 1 ÑGND is ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. GND Q Quiet Ground ÑGND Q is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GND A Address Bus Ground ÑGND A is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND A connections. GND D Data Bus Ground ÑGND D is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GND C Bus Control Ground ÑGND C is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GNDH Host GroundÑGNDH is an isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GNDS ESSI, SCI, and Timer GroundÑGNDS is an isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

MOTOROLA DSP56307 Technical Data 1-5 CLOCK PLL Table 1-4 Clock Signals Signal Name Type State During Reset Signal Description EXTAL Input Input External Clock/Crystal InputÑEXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock. XTAL Output Chip-driven Crystal OutputÑXTAL connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. Table 1-5 Phase-Locked Loop Signals Signal Name Type State During Reset Signal Description PCAP Input Input PLL CapacitorÑPCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to V CCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. CLKOUT Output Chip-driven Clock OutputÑCLKOUT provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.

1-6 DSP56307 Technical Data MOTOROLA Signals/Connections External Memory Expansion Port (Port A) EXTERNAL MEMORY EXPANSION PORT (PORT A) Note: When the DSP56307 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A0ÐA17, D0ÐD23, AA0/RAS0 ÐAA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK. External Address Bus PINIT NMI Input Input Input PLL InitialÑDuring assertion of RESET , the value of PINIT is written into the PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether the PLL is enabled or disabled. Nonmaskable InterruptÑAfter RESET deassertion and during normal instruction processing, this Schmitt-trigger input is the negative-edge-triggered NMI request internally synchronized to CLKOUT. Table 1-6 External Address Bus Signals Signal Name Type State During Reset Signal Description A0ÐA17 Output Tri-stated Address BusÑWhen the DSP is the bus master, A0ÐA17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0ÐA17 do not change state when external memory spaces are not being accessed. Table 1-5 Phase-Locked Loop Signals (Continued) Signal Name Type State During Reset Signal Description

External Memory Expansion Port (Port A) MOTOROLA DSP56307 Technical Data 1-7 External Data Bus External Bus Control Table 1-7 External Data Bus Signals Signal Name Type State During Reset Signal Description D0ÐD23 Input/ Output Tri-stated Data BusÑWhen the DSP is the bus master, D0ÐD23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0ÐD23 are tri-stated. These lines have weak keepers to maintain the last state even if all drivers are tri-stated. Table 1-8 External Bus Control Signals Signal Name Type State During Reset Signal Description AA0ÐAA3 RAS0 ÐRAS3 Output Output Tri-stated Address AttributeÑWhen defined as AA, these signals can be used as chip selects or additional address lines. The default use defines a priority scheme under which only one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit 14) of the OMR, the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals. Row Address StrobeÑWhen defined as RAS , these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. RD Output Tri-stated Read EnableÑWhen the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0ÐD23). Otherwise, RD is tri-stated. WR Output Tri-stated Write EnableÑWhen the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0ÐD23). Otherwise, the signals are tri-stated.

1-8 DSP56307 Technical Data MOTOROLA Signals/Connections External Memory Expansion Port (Port A) TA Input Ignored Input Transfer AcknowledgeÑIf the DSP56307 is the bus master and there is no external bus activity, or the DSP56307 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the bus control register (BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the BCR, whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion; otherwise, improper operation may result. TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the OMR. TA functionality may not be used while performing DRAM type accesses; otherwise, improper operation may result. Table 1-8 External Bus Control Signals (Continued) Signal Name Type State During Reset Signal Description

External Memory Expansion Port (Port A) MOTOROLA DSP56307 Technical Data 1-9 BR Output Output (deasserted) Bus RequestÑBR is an active-low output, never tri-stated. BR is asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independently of whether the DSP56307 is a bus master or a bus slave. Bus ÒparkingÓ allows BR to be deasserted even though the DSP56307 is the bus master. (See the description of bus ÒparkingÓ in the BB signal description.) The bus request hole (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. BG Input Ignored Input Bus GrantÑBG is an active-low input. BG must be asserted/deasserted synchronous to CLKOUT for proper operation. BG is asserted by an external bus arbitration circuit when the DSP56307 becomes the next bus master. When BG is asserted, the DSP56307 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. The default operation of this bit requires a setup and hold time as specified in DSP56307 Technical Data (the data sheet). An alternate mode can be invoked: set the asynchronous bus arbitration enable (ABE) bit (Bit 13) in the OMR. When this bit is set, BG and BB are synchronized internally. This eliminates the respective setup and hold time requirements but adds a required delay between the deassertion of an initial BG input and the assertion of a subsequent BG input. Table 1-8 External Bus Control Signals (Continued) Signal Name Type State During Reset Signal Description

1-10 DSP56307 Technical Data MOTOROLA Signals/Connections External Memory Expansion Port (Port A) BB Input/ Output Input Bus BusyÑBB is a bidirectional active-low input/output and must be asserted and deasserted synchronous to CLKOUT. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. Called Òbus parking,Ó this allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB is done by an Òactive pull-upÓ method (i.e., BB is driven high and then released and held high by an external pull-up resistor). The default operation of this bit requires a setup and hold time as specified in the DSP56307 Technical Data sheet. An alternate mode can be invoked: set the ABE bit (Bit 13) in the OMR. When this bit is set, BG and BB are synchronized internally. See BG for additional information. BB requires an external pull-up resistor. CAS Output Tri-stated Column Address StrobeÑWhen the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the bus mastership enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. BCLK Output Tri-stated Bus ClockÑWhen the DSP is the bus master, BCLK is an active-high output. BCLK is active as a sampling signal when the program address tracing mode is enabled (i.e., the ATE bit in the OMR is set). When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. The BCLK rising edge may be used to sample the internal program memory access on the A0ÐA23 address lines. BCLK Output Tri-stated Bus Clock NotÑWhen the DSP is the bus master, BCLK is an active-low output and is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. Table 1-8 External Bus Control Signals (Continued) Signal Name Type State During Reset Signal Description

Interrupt and Mode Control MOTOROLA DSP56307 Technical Data 1-11 INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the chipÕs operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 1-9 Interrupt and Mode Control Signal Name Type State During Reset Signal Description RESET Input Input ResetÑRESET is an active-low, Schmitt-trigger input. Deassertion of RESET is internally synchronized to CLKOUT. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in Òlock-step.Ó When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power up. MODA IRQA Input Input Input Mode Select AÑMODA is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request AÑAfter reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQA is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQA to exit the wait state. If the processor is in the stop standby state and IRQA is asserted, the processor will exit the stop state.

1-12 DSP56307 Technical Data MOTOROLA Signals/Connections Interrupt and Mode Control MODB IRQB Input Input Input Mode Select BÑMODB is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request BÑAfter reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQB is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQB to exit the wait state. If the processor is in the stop standby state and IRQB is asserted, the processor will exit the stop state. MODC IRQC Input Input Input Mode Select CÑMODC is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request CÑAfter reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state. If the processor is in the stop standby state and IRQC is asserted, the processor will exit the stop state. Table 1-9 Interrupt and Mode Control (Continued) Signal Name Type State During Reset Signal Description

MOTOROLA DSP56307 Technical Data 1-13 HI08 The HI08 provides a fast parallel-data-to-8-bit port that may be connected directly to the host bus. The HI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware. MODD IRQD Input Input Input Mode Select DÑMODD is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request DÑAfter reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQD is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQD to exit the wait state. If the processor is in the stop standby state and IRQD is asserted, the processor will exit the stop state. Table 1-9 Interrupt and Mode Control (Continued) Signal Name Type State During Reset Signal Description

1-14 DSP56307 Technical Data MOTOROLA Signals/Connections HI08 Table 1-10 Host Interface Signal Name Type State During Reset Signal Description H0ÐH7 HAD0ÐHAD7 PB0ÐPB7 Input/ Output Input/ Output Input or Output Tri-stated Host DataÑWhen the HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, these signals are lines 0Ð7 of the data bidirectional, tri-state bus. Host AddressÑWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0Ð7 of the address/data bidirectional, multiplexed, tri-state bus. Port B 0Ð7ÑWhen the HI08 is configured as GPIO through the host port control register (HPCR), these signals are individually programmed as inputs or outputs through the HI08 data direction register (HDDR). Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. HA0 HAS/HAS PB8 Input Input Input or Output Input Host Address Input 0ÑWhen the HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address StrobeÑWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable but is configured active-low (HAS ) following reset. Port B 8ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.

MOTOROLA DSP56307 Technical Data 1-15 HA1 HA8 PB9 Input Input Input or Output Input Host Address Input 1ÑWhen the HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address 8ÑWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus. Port B 9ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. HA2 HA9 PB10 Input Input Input or Output Input Host Address Input 2ÑWhen the HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. Host Address 9ÑWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. Port B 10ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-10 Host Interface (Continued) Signal Name Type State During Reset Signal Description

1-16 DSP56307 Technical Data MOTOROLA Signals/Connections HI08 HRW HRD/HRD PB11 Input Input Input or Output Input Host Read/WriteÑWhen HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. Host Read DataÑWhen HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the HRD strobe Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD ) after reset. Port B 11ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. HDS/HDS HWR/HWR PB12 Input Input Input or Output Input Host Data StrobeÑWhen HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS ) following reset. Host Write DataÑWhen HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR ) following reset. Port B 12ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-10 Host Interface (Continued) Signal Name Type State During Reset Signal Description

MOTOROLA DSP56307 Technical Data 1-17 HCS HA10 PB13 Input Input Input or Output Input Host Chip SelectÑWhen HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS after reset. Host Address 10ÑWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. Port B 13ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-10 Host Interface (Continued) Signal Name Type State During Reset Signal Description

1-18 DSP56307 Technical Data MOTOROLA Signals/Connections HI08 HREQ/HREQ HTRQ/HTRQ PB14 Output Output Input or Output Input Host RequestÑWhen HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host request (HREQ) output. The polarity of the host request is programmable, but is configured as active-low (HREQ ) following reset. The host request may be programmed as a driven or open-drain output. Transmit Host RequestÑWhen HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ ) following reset. The host request may be programmed as a driven or open-drain output. Port B 14ÑWhen the HI08 is programmed to interface a multiplexed host bus and the signal is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-10 Host Interface (Continued) Signal Name Type State During Reset Signal Description

Enhanced Synchronous Serial Interface 0 MOTOROLA DSP56307 Technical Data 1-19 ENHANCED SYNCHRONOUS SERIAL INTERFACE 0 There are two synchronous serial interfaces (ESSI0 and ESSI1) that provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola serial peripheral interface (SPI). HACK/ HACK HRRQ/ HRRQ PB15 Input Output Input or Output Input Host AcknowledgeÑWhen HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK ) after reset. Receive Host RequestÑWhen HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ ) after reset. The host request may be programmed as a driven or open-drain output. Port B 15ÑWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-10 Host Interface (Continued) Signal Name Type State During Reset Signal Description

1-20 DSP56307 Technical Data MOTOROLA Signals/Connections Enhanced Synchronous Serial Interface 0 Table 1-11 Enhanced Synchronous Serial Interface 0 Signal Name Type State During Reset Signal Description SC00 PC0 Input or Output Input Serial Control 0ÑThe function of SC00 is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal will be used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port C 0ÑThe default configuration following reset is GPIO input PC0. When configured as PC0, signal direction is controlled through the port directions register (PRR0). The signal can be configured as ESSI signal SC00 through the port control register (PCR0). Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. SC01 PC1 Input/ Output Input or Output Input Serial Control 1ÑThe function of this signal is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for transmitter 2 output or for serial I/O flag 1. Port C 1ÑThe default configuration following reset is GPIO input PC1. When configured as PC1, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC01 through PCR0. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.

Enhanced Synchronous Serial Interface 0 MOTOROLA DSP56307 Technical Data 1-21 SC02 PC2 Input/ Output Input or Output Input Serial Control Signal 2ÑSC02 is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C 2ÑThe default configuration following reset is GPIO input PC2. When configured as PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. SCK0 PC3 Input/ Output Input or Output Input Serial ClockÑSCK0 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the ESSI. The SCK0 is a clock input or output, used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. Port C 3ÑThe default configuration following reset is GPIO input PC3. When configured as PC3, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SCK0 through PCR0. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-11 Enhanced Synchronous Serial Interface 0 (Continued) Signal Name Type State During Reset Signal Description

1-22 DSP56307 Technical Data MOTOROLA Signals/Connections Enhanced Synchronous Serial Interface 0 SRD0 PC4 Input/ Output Input or Output Input Serial Receive DataÑSRD0 receives serial data and transfers the data to the ESSI receive shift register. SRD0 is an input when data is being received. Port C 4ÑThe default configuration following reset is GPIO input PC4. When configured as PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. STD0 PC5 Input/ Output Input or Output Input Serial Transmit DataÑSTD0 is used for transmitting data from the serial transmit shift register. STD0 is an output when data is being transmitted. Port C 5ÑThe default configuration following reset is GPIO input PC5. When configured as PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-11 Enhanced Synchronous Serial Interface 0 (Continued) Signal Name Type State During Reset Signal Description

Enhanced Synchronous Serial Interface 1 MOTOROLA DSP56307 Technical Data 1-23 ENHANCED SYNCHRONOUS SERIAL INTERFACE 1 Table 1-12 Enhanced Serial Synchronous Interface 1 Signal Name Type State During Reset Signal Description SC10 PD0 Input or Output Input or Output Input Serial Control 0ÑThe function of SC10 is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal will be used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port D 0ÑThe default configuration following reset is GPIO input PD0. When configured as PD0, signal direction is controlled through the port directions register (PRR1). The signal can be configured as an ESSI signal SC10 through the port control register (PCR1). Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. SC11 PD1 Input/ Output Input or Output Input Serial Control 1ÑThe function of this signal is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1. Port D 1ÑThe default configuration following reset is GPIO input PD1. When configured as PD1, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC11 through PCR1. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.

1-24 DSP56307 Technical Data MOTOROLA Signals/Connections Enhanced Synchronous Serial Interface 1 SC12 PD2 Input/ Output Input or Output Input Serial Control Signal 2ÑSC12 is used for frame sync I/O. SC12 is the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port D 2ÑThe default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. SCK1 PD3 Input/ Output Input or Output Input Serial ClockÑSCK1 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the ESSI. The SCK1 is a clock input or output used by both the transmitter and receiver in synchronous modes, or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. Port D 3ÑThe default configuration following reset is GPIO input PD3. When configured as PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-12 Enhanced Serial Synchronous Interface 1 (Continued) Signal Name Type State During Reset Signal Description

MOTOROLA DSP56307 Technical Data 1-25 SCI The SCI provides a full duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. SRD1 PD4 Input/ Output Input or Output Input Serial Receive DataÑSRD1 receives serial data and transfers the data to the ESSI receive shift register. SRD1 is an input when data is being received. Port D 4ÑThe default configuration following reset is GPIO input PD4. When configured as PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. STD1 PD5 Input/ Output Input or Output Input Serial Transmit DataÑSTD1 is used for transmitting data from the serial transmit shift register. STD1 is an output when data is being transmitted. Port D 5ÑThe default configuration following reset is GPIO input PD5. When configured as PD5, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal STD1 through PCR1. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-12 Enhanced Serial Synchronous Interface 1 (Continued) Signal Name Type State During Reset Signal Description

1-26 DSP56307 Technical Data MOTOROLA Signals/Connections SCI Table 1-13 Serial Communication Interface Signal Name Type State During Reset Signal Description RXD PE0 Input Input or Output Input Serial Receive DataÑThis input receives byte oriented serial data and transfers it to the SCI receive shift register. Port E 0ÑThe default configuration following reset is GPIO input PE0. When configured as PE0, signal direction is controlled through the SCI port directions register (PRR). The signal can be configured as an SCI signal RXD through the SCI port control register (PCR). Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. TXD PE1 Output Input or Output Input Serial Transmit DataÑThis signal transmits data from SCI transmit data register. Port E 1ÑThe default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. SCLK PE2 Input/ Output Input or Output Input Serial ClockÑThis is the bidirectional Schmitt-trigger input signal providing the input or output clock used by the transmitter and/or the receiver. Port E 2ÑThe default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal SCLK through the SCI PCR. Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.

MOTOROLA DSP56307 Technical Data 1-27 TIMERS Three identical and independent timers are implemented in the DSP56307. Each timer can use internal or external clocking and can either interrupt the DSP56307 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events. Table 1-14 Triple Timer Signals Signal Name Type State During Reset Signal Description TIO0 Input or Output Input Timer 0 Schmitt-Trigger Input/OutputÑ When Timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer I/O through the timer 0 control/status register (TCSR0). Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. TIO1 Input or Output Input Timer 1 Schmitt-Trigger Input/OutputÑ When Timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer I/O through the timer 1 control/status register (TCSR1). Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.

1-28 DSP56307 Technical Data MOTOROLA Signals/Connections JTAG and OnCE Interface JTAG AND OnCE INTERFACE The DSP56300 family and in particular the DSP56307 support circuit-board test strategies based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming models, see Section 12 Joint Test Action Group Port and Section 11 On-Chip Emulation Module . TIO2 Input or Output Input Timer 2 Schmitt-Trigger Input/OutputÑ When timer 2 functions as an external event counter or in measurement mode, TIO2 is used as input. When timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer I/O through the timer 2 control/status register (TCSR2). Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated. Table 1-14 Triple Timer Signals (Continued) Signal Name Type State During Reset Signal Description

MOTOROLA DSP56307 Technical Data 1-29 Table 1-15 OnCE/JTAG Interface Signal Name Type State During Reset Signal Description TCK Input Input Test ClockÑTCK is a test clock input signal used to synchronize the JTAG test logic. TDI Input Input Test Data InputÑTDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. TDO Output Tri-stated Test Data OutputÑTDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. TMS Input Input Test Mode SelectÑTMS is an input signal used to sequence the test controllerÕs state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. TRST Input Input Test ResetÑTRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted after power up.

1-30 DSP56307 Technical Data MOTOROLA Signals/Connections JTAG and OnCE Interface DE Input/ Output Input Debug EventÑDE is an open-drain, bidirectional, active-low signal that provides, as an input, a means of entering the debug mode of operation from an external command controller, and, as an output, a means of acknowledging that the chip has entered the debug mode. This signal, when asserted as an input, causes the DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters the debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor. This is not a standard part of the JTAG TAP controller. The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered the debug mode. All other interface with the OnCE module must occur through the JTAG port. Table 1-15 OnCE/JTAG Interface (Continued) Signal Name Type State During Reset Signal Description

MOTOROLA DSP56307 Technical Data 2-1 SECTION 2 SPECIFICATIONS INTRODUCTION The DSP56307 is fabricated in high-density CMOS with transistor-transistor Logic (TTL) compatible inputs and outputs. The DSP56307 specifications are preliminary from design simulations and may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after full characterization and device qualifications are complete. MAXIMUM RATINGS Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst-case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a ÒmaximumÓ value for a specification will never occur in the same device that has a ÒminimumÓ value for another specification, adding a maximum to a minimum represents a condition that can never exist. CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V CC

2-2 DSP56307 Technical Data MOTOROLA Specifications Thermal Characteristics THERMAL CHARACTERISTICS Table 2-1 Maximum Ratings Rating Symbol Value 1, 2 Unit Supply Voltage: ¥ PLL (V CCP ) and Core (V CCQL ¥ All other (I/O) V CCx 0.3 to +3.3 Ð0.3 to +4.0 V V All input signal voltages V IN GND 0.3 to V CCQH + 0.3 V Current drain per pin excluding V CC and GND I 10 mA Operating temperature range T J 40 to +100 û C Storage temperature T STG 55 to +150 û C Notes: 1. GND = 0 V, V CCQL CCP = 2.5 V

0.2 V, I/O V

= 3.3

0.3 V, T

J = Ð40 C to +100 C, CL = 50 pF 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. Table 2-2 Thermal Characteristics Characteristic Symbol PBGA Value PBGA Value Unit Junction-to-ambient thermal resistance R q JA or q JA 51.9 29.0 û C/W Junction-to-case thermal resistance R q JC or q JC 13.1 Ñ û C/W Thermal characterization parameter Y JT 2.45 1.68 û C/W Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 in natural convection. (SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. 2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. 3. The test board has two, 2-ounce signal layers and two 1-ounce solid ground planes internal to the test board.

MOTOROLA DSP56307 Technical Data 2-3 DC ELECTRICAL CHARACTERISTICS Table 2-3 Characteristics Symbol Min Typ Max Unit Supply voltage: ¥ Core (V CCQL and PLL (V CCP 4. I/O (V CCQH , V CCA , V CCD , V CCC V CCH , and V CCS V CC 2.3 3.0 2.5 3.3 2.7 3.6 V Input high voltage ¥ D0ÐD23, BG , BB, TA ¥ MOD /IRQ , RESET, PINIT/NMI and all JTAG/ESSI/SCI/Timer/HI08 pins ¥ EXTAL V IH V IHP V IHX 2.0 2.0 0.8 V CCQH Ñ Ñ Ñ V CCQH V CCQH + 0.3 V CCQH V V V Input low voltage ¥ D0ÐD23, BG , BB, TA, MOD /IRQ RESET, PINIT ¥ All JTAG/ESSI/SCI/Timer/HI08 pins ¥ EXTAL V IL V ILP V ILX Ð0.3 Ð0.3 Ð0.3 Ñ Ñ Ñ 0.8 0.8 0.2 V CCQH V V V Input leakage current (@ maximum V CCQH / 0.0 V) I IN Ð10 Ñ 10 m A High impedance (off-state) input current (@ maximum V CCQH / 0.0 V) I TSI Ð10 Ñ 10 m A Output high voltage ¥ TTL (I OH = Ð0.4 mA) 4,5 ¥ CMOS (I OH = Ð10 m V OH 2.4 V CCQH Ð 0.01 Ñ Ñ Ñ Ñ V V Output low voltage ¥ TTL (Port A I OL = 1.6 mA, non-Port A I OL = 3.2 mA, open-drain pins I OL = 6.7 mA) 4,5 ¥ CMOS (I OL = 10 m V OL Ñ Ñ Ñ Ñ 0.4 0.01 V V Internal supply current ¥ In Normal mode ¥ In Wait mode ¥ In Stop mode I CCI I CCW I CCS Ñ Ñ Ñ 120 100 Ñ Ñ Ñ mA mA m A PLL supply current in Stop mode ÑÑ 1 Ñ m A Input capacitance C IN Ñ Ñ 10 pF

2-4 DSP56307 Technical Data MOTOROLA Specifications AC ELECTRICAL CHARACTERISTICS The timing waveforms shown in the ac electrical characteristics section are tested with a V IL maximum of 0.3 V and a V IH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of Table 2-3 . AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signalÕs transition. DSP56307 output levels are measured with the production test machine V OL and V OH reference levels set at 0.8 V and 2.0 V, respectively. INTERNAL CLOCKS 2. Refers to MODA/IRQA , MODB/IRQB, MODC/IRQC, and MODD/IRQD pins 3. Driving EXTAL to the low V IHX or the high VILX value may cause additional power consumption (dc current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 · VCC and the maximum VILX should be no higher than 0.1 · VCC. 4. Periodically sampled and not 100% tested 5. This characteristic does not apply to XTAL and PCAP. 6. Power Consumption Considerations on page SECTION 4-4 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. (For an example, see Appendix A, Power Consumption Benchmark on page APPENDIX A-1.) The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V CCQL = 2.5 V at TJ = 100ûC. Maximum internal supply current may vary widely and is application dependent. 7. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL and XTAL signals are disabled during Stop state. 8. In order to obtain these results, all inputs not disconnected in Stop mode must be terminated (i.e., not allowed to float). 9. See DSP56307 Errata ES 74. for appropriate operating voltages for appropriate mask sets. 10. See DSP56307 Errata ES93 for appropriate workarounds to data bus drift problem. Table 2-4 Internal Clocks, CLKOUT Characteristics Symbol Expression1, 2 Min Typ Max Internal operation frequency and CLKOUT with PLL enabled f Ñ (Ef · MF)/ (PDF · DF) Ñ Table 2-3 DC Electrical Characteristics1 (Continued) Characteristics Symbol Min Typ Max Unit

MOTOROLA DSP56307 Technical Data 2-5 Internal operation frequency and CLKOUT with PLL disabled f Ñ Ef/2 Ñ Internal clock and CLKOUT high period ¥ With PLL disabled ¥ With PLL enabled and MF £ 4 ¥ With PLL enabled and MF > 4 T H Ñ 0.49 · ETC · PDF · DF/MF 0.47 · ETC · PDF · DF/MF ETC Ñ Ñ Ñ 0.51 · ETC · PDF · DF/MF 0.53 · ETC · PDF · DF/MF Internal clock and CLKOUT low period ¥ With PLL disabled ¥ With PLL enabled and MF £ 4 ¥ With PLL enabled and MF > 4 T L Ñ 0.49 · ETC · PDF · DF/MF 0.47 · ETC · PDF · DF/MF ETC Ñ Ñ Ñ 0.51 · ETC · PDF · DF/MF 0.53 · ETC · PDF · DF/MF Internal clock and CLKOUT cycle time with PLL enabled TC ÑE T C · PDF · DF/MF Ñ Internal clock and CLKOUT cycle time with PLL disabled TC Ñ2 · ETC Ñ Instruction cycle time I CYC ÑT C Ñ Notes: 1. DF = Division Factor Ef = External frequency ET C = External clock cycle MF = Multiplication Factor PDF = Predivision Factor T C = internal clock cycle 2. See PLL and Clock Generation in the DSP56300 Family Manual for a detailed discussion of the phase-locked loop. Table 2-4 Internal Clocks, CLKOUT Characteristics Symbol Expression1, 2 Min Typ Max

MOTOROLA DSP56307 Technical Data 2-7 Figure 2-2 External Clock Timing Table 2-5 Clock Operation No. Characteristics Symbol

100 MHz

1 Frequency of EXTAL (EXTAL pin frequency)

The rise and fall time of this external clock should be 3 ns maximum. Ef 0 100.0

2 EXTAL input high

1, 2 ¥ With PLL disabled (46.7%Ð53.3% duty cycle3) ¥ With PLL enabled (42.5%Ð57.5% duty cycle3) ETH 4.67 ns 4.25 ns 157.0 ms

3 EXTAL input low 1, 2

¥ With PLL disabled (46.7%Ð53.3% duty cycle3) ¥ With PLL enabled (42.5%Ð57.5% duty cycle3) ETL 4.67 ns 4.25 ns 157.0 ms

4 EXTAL cycle time 2

¥ With PLL disabled ¥ With PLL enabled ETC 10.00 ns 10.00 ns 273.1 ms

5 CLKOUT change from EXTAL fall with PLL

Ñ 4.3 ns 11.0 ns EXTAL VILC VIHC Midpoint Note: The midpoint is 0.5 (VIHC + VILC). ET H ET L ET C CLKOUT With PLL Disabled CLKOUT With PLL Enabled AA0459

2-8 DSP56307 Technical Data MOTOROLA Specifications External Clock Operation

6 CLKOUT rising edge from EXTAL rising edge

with PLL enabled (MF = 1, PDF = 1, Ef > 15 MHz) 4,5 CLKOUT falling edge from EXTAL rising edge with PLL enabled (MF = 2 or 4, PDF = 1, Ef > 15 MHz) 4,5 CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF £ 4, PDF „ 1, Ef / PDF > 15 MHz) 4,5 0.0 ns 0.0 ns 0.0 ns 1.8 ns 1.8 ns 1.8 ns

7 Instruction cycle time = I

CYC = TC (See Table 2-4.) (46.7%Ð53.3% duty cycle) ¥ With PLL disabled ¥ With PLL enabled I CYC 20.0 ns 10.00 ns 8.53 ms Notes: 1. Measured at 50% of the input transition 2. The maximum value for PLL enabled is given for minimum V CO and maximum MF. 3. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 4. Periodically sampled and not 100% tested 5. The skew is not guaranteed for any other MF value. 6. The maximum value for PLL enabled is given for minimum V CO and maximum DF. Table 2-5 Clock Operation (Continued) No. Characteristics Symbol

MOTOROLA DSP56307 Technical Data 2-9 PLL CHARACTERISTICS Table 2-6 PLL Characteristics Characteristics enabled (MF · Ef · 2/PDF) 30 200 MHz PLL external capacitor (PCAP pin to VCCP) (CPCAP ¥ @ MF £ 4 ¥ @ MF > 4 (MF · 680) - 120 MF · 1100 (MF · 580) - 100 MF · 830 (MF · 780) - 140 MF · 1470 pF pF Note: C PCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (500 · MF) Ð 150, for MF £ 4, or 690 · MF, for MF > 4.

2-10 DSP56307 Technical Data MOTOROLA Specifications Reset, Stop, Mode Select, and Interrupt Timing RESET, STOP, MODE SELECT, AND INTERRUPT TIMING Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing1 No. Characteristics Expression

8 Delay from RESET assertion to all pins

Ñ Ñ 26.0 ns

9 Required RESET duration3

¥ Power on, external clock generator, PLL disabled ¥ Power on, external clock generator, PLL enabled ¥ Power on, internal oscillator ¥ During STOP, XTAL disabled (PCTL Bit 16 = 0) ¥ During STOP, XTAL enabled (PCTL Bit 16 = 1) ¥ During normal operation 50 · ET C 1000 · ETC 75000 · ETC 75000 · ETC 2.5 · TC 2.5 · TC 500.0 10.0 0.75 0.75 25.0 25.0 Ñ Ñ Ñ Ñ Ñ Ñ ns ms ms ms ns ns

10 Delay from asynchronous RESET

deassertion to first external address output (internal reset deassertion) ¥ Minimum ¥ Maximum 3.25 · T C + 2.0 20.25 TC + 7.50 34.5 Ñ Ñ 211.5 ns ns

11 Synchronous reset set-up time from

RESET deassertion to CLKOUT Transition 1 ¥ Minimum ¥ Maximum T C 5.9 Ñ Ñ 10.0 ns ns

12 Synchronous reset deasserted, delay

time from the CLKOUT Transition 1 to the first external address output ¥ Minimum ¥ Maximum 3.25 · T C + 1.0 20.25 TC + 5.0 33.5 Ñ Ñ 207.5 ns ns 13 Mode select setup time Ñ 30.0 Ñ ns 14 Mode select hold time Ñ 0.0 Ñ ns

15 Minimum edge-triggered interrupt

Ñ 6.6 Ñ ns

16 Minimum edge-triggered interrupt

Ñ 6.6 Ñ ns

Reset, Stop, Mode Select, and Interrupt Timing MOTOROLA DSP56307 Technical Data 2-11

17 Delay from IRQA , IRQB, IRQC, IRQD,

NMI assertion to external memory access address out valid ¥ Caused by first interrupt instruction fetch ¥ Caused by first interrupt instruction execution 4.25 · TC + 2.0 7.25 · TC + 2.0 44.5 74.5 Ñ Ñ ns ns

18 Delay from IRQA , IRQB, IRQC, IRQD,

NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution 10 · T C + 5.0 105.0 Ñ ns

19 Delay from address output valid caused

by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts 5,6,7 (WS + 3.75) · TC Ð 10.94 Ñ see note 8 ns

20 Delay from RD assertion to interrupt

request deassertion for level sensitive fast interrupts 5,6,7 (WS + 3.25) · TC Ð 10.94 Ñ see note 8 ns

21 Delay from WR assertion to interrupt

request deassertion for level sensitive fast interrupts 5,6,7 ¥ DRAM for all WS ¥ SRAM WS = 1 ¥ SRAM WS = 2, 3 ¥ SRAM WS ‡ 4 (WS + 3.5) · T C Ð 10.94 (WS + 3) · TC Ð 10.94 Ñ Ñ Ñ Ñ see note 8 ns ns ns ns

22 Synchronous interrupt setup time from

, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 Ñ 5.9 T C ns

23 Synchronous interrupt delay time from

the CLKOUT Transition 2 to the first external address output valid caused by the first instruction fetch after coming out of Wait Processing state ¥ Minimum ¥ Maximum 9.25 · T C + 1.0 24.75 · TC + 5.0 93.5 Ñ Ñ 252.5 ns ns

24 Duration for IRQA assertion to recover

Ñ 5.9 Ñ ns Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing1 (Continued) No. Characteristics Expression

2-12 DSP56307 Technical Data MOTOROLA Specifications Reset, Stop, Mode Select, and Interrupt Timing

25 Delay from IRQA assertion to fetch of

first instruction (when exiting Stop)2, 8 ¥ PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) ¥ PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) ¥ PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) PLC · ET C · PDF + (128 K - PLC/2) · TC PLC · ETC · PDF + (23.75 – 0.5) · TC (8.25 – 0.5) · TC 1.3 232.5 ns 77.5 13.6 12.3 ms 87.5 ms ns

26 Duration of level sensitive IRQA

assertion to insure interrupt service (when exiting Stop) 2, 8 ¥ PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) ¥ PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) ¥ PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) PLC · ET C · PDF + (128K - PLC/2) · TC PLC · ETC · PDF + (20.5 – 0.5) · TC 5.5 · TC 13.6 12.3 55.0 Ñ Ñ Ñ ms ms ns

27 Interrupt Requests Rate

¥ HI08, ESSI, SCI, Timer ¥ DMA ¥ IRQ , NMI (edge trigger) ¥ IRQ , NMI (level trigger) 12TC 8TC 8TC 12TC Ñ Ñ Ñ Ñ 120.0 80.0 80.0 120.0 ns ns ns ns

28 DMA Requests Rate

¥ Data read from HI08, ESSI, SCI ¥ Data write to HI08, ESSI, SCI ¥ Timer ¥ IRQ , NMI (edge trigger) 6TC 7TC 2TC 3TC Ñ Ñ Ñ Ñ 60.0 70.0 20.0 30.0 ns ns ns ns

29 Delay from IRQA

, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid 4.25 · TC + 2.0 44.0 Ñ ns Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing1 (Continued) No. Characteristics Expression

Reset, Stop, Mode Select, and Interrupt Timing MOTOROLA DSP56307 Technical Data 2-13 Notes: 1. V CCQL = 2.5 V – 0.25 V; TJ = Ð40ûC to +100ûC, CL = 50 pF 2. Periodically sampled and not 100% tested 3. For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the V CC is valid, but the other Òrequired RESET durationÓ conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. 4. If PLL does not lose lock 5. When fast interrupts and IRQA are being used, then IRQB, IRQC, and IRQD are defined as level-sensitive; timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, we recommend the deasserted edge-triggered mode when fast interrupts are being used. Long interrupts are recommended when any level-sensitive mode is being used. 6. WS = number of wait states (measured in clock cycles, number of T 7. Use expression to compute maximum value. 8. This timing depends on several settings: For PLL disable, if the internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) is being used and the oscillator is disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to insure the oscillator is stable before programs are executed. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. For PLL disable, if the internal oscillator (PCTL Bit 16 = 0) is being used and the oscillator is enabled during Stop (PCTL Bit 17=1), then no stabilization delay is required, and recovery time will be minimal (i.e., OMR Bit 6 setting is ignored). For PLL disable, if the external clock (PCTL Bit 16 = 1) is being used, no stabilization delay is required, and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovery from Stop requires the PLL to be locked. The duration of the PLL lock procedure (i.e., the PLL Lock Cycles (PLC)) may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ET C is 4096 (maximum MF) divided by the desired internal frequency. During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well. Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing1 (Continued) No. Characteristics Expression

2-18 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) EXTERNAL MEMORY INTERFACE (PORT A) SRAM Timing Table 2-8 SRAM Read and Write Accesses No. Characteristics Symbol Expression1, 2

100 Address valid and

t RC, tWC (WS + 1) · TC - 4.0 [1 £ WS £ 3] [4 £ WS £ 7] [WS ‡ 8] 16.0 56.0 106.0 Ñ Ñ Ñ ns ns ns

101 Address and AA

tAS 100 MHz: All frequencies: 0.75 · T 0.1 3.5 8.5 Ñ Ñ Ñ ns ns ns

102 WR assertion pulse

tWP 1.5 · TC - 4.5 [WS = 1] 10.5 16.0 31.0 Ñ Ñ Ñ ns ns ns 103 WR deassertion to address not valid tWR 100 MHz: All frequencies: 1.25 · T 0.1 8.5 18.5 Ñ Ñ Ñ ns ns ns

104 Address and AA

t AA, tAC 100 MHz: [WS ‡ 1] Ñ 9.5 ns

105 RD assertion to

tOE 100 MHz: [WS ‡ 1] Ñ 4.5 ns

106 RD deassertion to

data not valid (data hold time) t OHZ 0.0 Ñ ns

107 Address valid to

tAW (WS + 0.75) · TC - 4.0 [WS ‡ 1] 13.5 Ñ ns

108 Data valid to WR

deassertion (data setup time) t DS (tDW) 100 MHz: [WS ‡ 1] 4.8 Ñ ns

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-19

109 Data hold time from

tDH 100 MHz: All frequencies: 1.25 · T 0.1 8.7 18.7 Ñ Ñ Ñ ns ns ns

110 WR assertion to data

3.8 Ð1.2 Ð6.2 Ñ Ñ Ñ ns ns ns 111 WR deassertion to data high impedance Ñ 0.25 · T Ñ Ñ Ñ 2.7 12.7 22.7 ns ns ns

112 Previous RD

active (write) Ñ 1.25 · T 8.5 18.5 28.5 Ñ Ñ Ñ ns ns ns 113 RD deassertion time Ñ 0.75 · TC - 4.0 [1 £ WS £ 3] 3.5 13.5 23.5 Ñ Ñ Ñ ns ns ns 114 WR deassertion time 1.5 6.5 21.5 31.5 Ñ Ñ Ñ Ñ ns ns ns ns

115 Address valid to RD

Ñ 0.5 · TC - 4 1.0 Ñ ns

116 RD assertion pulse

Ñ (WS + 0.25) · TC - 3.8 8.7 Ñ ns

117 RD deassertion to

0.0 9.5 19.5 Ñ Ñ Ñ ns ns ns Notes: 1. WS is the number of wait states specified in the BCR. 2. V CCQL = 2.5 V – 0.25 V; TJ = Ð40ûC to +100 ûC, CL = 50 pF Table 2-8 SRAM Read and Write Accesses (Continued) No. Characteristics Symbol Expression1, 2

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-21 DRAM Timing The selection guides provided in Figure 2-14 and in Figure 2-17 on page SECTION 2-32 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when page mode DRAM is being used. However, a designer may use the information in the appropriate table to evaluate whether fewer wait states might be used; a designer may determine which timing prevents operation at 100 MHz, run the chip at a slightly lower frequency (e.g., 95 MHz), use faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance. Figure 2-14 DRAM Page Mode Wait States Selection Guide Chip Frequency (MHz) DRAM Type (tRAC ns) 100 40 66 80 100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

Note: This figure should be used for primary selection. For exact and detailed timings, see the following tables. AA0472 120

2-22 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 No. Characteristics Symbol Expression

20 MHz6 30 MHz6

131 Page mode cycle time t PC 1.25 · TC 62.5 Ñ 41.7 Ñ ns

132 CAS assertion to data valid

(read) tCAC TC - 7.5 Ñ 42.5 Ñ 25.8 ns

133 Column address valid to

data valid (read) tAA 1.5 · TC - 7.5 Ñ 67.5 Ñ 42.5 ns

134 CAS deassertion to data not

valid (read hold time) tOFF Ñ 0.0 Ñ 0.0 Ñ ns

135 Last CAS assertion to RAS

tRSH 0.75 · TC - 4.0 33.5 Ñ 21.0 Ñ ns

136 Previous CAS deassertion to

tRHCP 2 · TC - 4.0 96.0 Ñ 62.7 Ñ ns 137 CAS assertion pulse width t CAS 0.75 · TC - 4.0 33.5 Ñ 21.0 Ñ ns

138 Last CAS deassertion to

¥ BRW[1:0] = 00 ¥ BRW[1:0] = 01 ¥ BRW[1:0] = 10 ¥ BRW[1:0] = 11 t CRP 1.75 · TC - 6.0 3.25 · TC - 6.0 4.25 · TC - 6.0 6.25 · TC Ð 6.0 81.5 156.5 206.5 306.5 Ñ Ñ Ñ Ñ 52.3 102.2 135.5 202.1 Ñ Ñ Ñ Ñ ns ns ns ns

139 CAS

tCP 0.5 · TC - 4.0 21.0 Ñ 12.7 Ñ ns

140 Column address valid to

tASC 0.5 · TC - 4.0 21.0 Ñ 12.7 Ñ ns

141 CAS assertion to column

tCAH 0.75 · TC - 4.0 33.5 Ñ 21.0 Ñ ns

142 Last column address valid

tRAL 2 · TC - 4.0 96.0 Ñ 62.7 Ñ ns

143 WR deassertion to CAS

tRCS 0.75 · TC - 3.8 33.7 Ñ 21.2 Ñ ns

144 CAS deassertion to WR

tRCH 0.25 · TC - 3.7 8.8 Ñ 4.6 Ñ ns

145 CAS assertion to WR

tWCH 0.5 · TC - 4.2 20.8 Ñ 12.5 Ñ ns 146 WR assertion pulse width tWP 1.5 · TC - 4.5 70.5 Ñ 45.5 Ñ ns

147 Last WR assertion to RAS

tRWL 1.75 · TC - 4.3 83.2 Ñ 54.0 Ñ ns

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-23

148 WR assertion to CAS

tCWL 1.75 · TC - 4.3 83.2 Ñ 54.0 Ñ ns

149 Data valid to CAS assertion

(Write) tDS 0.25 · TC - 4.0 8.5 Ñ 4.3 Ñ ns

150 CAS assertion to data not

valid (write) tDH 0.75 · TC - 4.0 33.5 Ñ 21.0 Ñ ns

151 WR assertion to CAS

tWCS TC - 4.3 45.7 Ñ 29.0 Ñ ns

152 Last RD assertion to RAS

tROH 1.5 · TC - 4.0 71.0 Ñ 46.0 Ñ ns 153 RD assertion to data valid t GA T C - 7.5 Ñ 42.5 Ñ 25.8 ns

154 RD deassertion to data not

tGZ Ñ 0.0 Ñ 0.0 Ñ ns 155 WR assertion to data active Ñ 0.75 · TC - 0.3 37.2 Ñ 24.7 Ñ ns

156 WR deassertion to data high

Ñ 0.25 · TC Ñ 12.5 Ñ 8.3 ns Notes: 1. The number of wait states for page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t PC equals 2 · TC for read-after-read or write-after-write sequences). 4. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 5. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 6. Reduced DSP clock speed allows use of page mode DRAM with one wait state (see Figure 2-14). Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 No. Characteristics Symbol Expression

2-24 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Table 2-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4, 5 No. Characteristics Symbol Expression

66 MHz 80 MHz

131 Page mode cycle time t PC 2.75 · TC 41.7 Ñ 34.4 Ñ ns (read) tCAC 66 MHz: 1.5 · TC - 7.5

80 MHz:

1.5 · TC - 6.5 Ñ Ñ 15.2 Ñ Ñ Ñ Ñ 12.3 ns ns data valid (read) tAA 66 MHz: 2.5 · TC - 7.5 2.5 · TC - 6.5 Ñ Ñ 30.4 Ñ Ñ Ñ Ñ 24.8 ns ns valid (read hold time) tOFF Ñ 0.0 Ñ 0.0 Ñ ns tRSH 1.75 · TC - 4.0 22.5 Ñ 17.9 Ñ ns

136 Previous CAS deassertion

tRHCP 3.25 · TC - 4.0 45.2 Ñ 36.6 Ñ ns 137 CAS assertion pulse width t CAS 1.5 · TC - 4.0 18.7 Ñ 14.8 Ñ ns ¥ BRW[1:0] = 00 ¥ BRW[1:0] = 01 ¥ BRW[1:0] = 10 ¥ BRW[1:0] = 11 t CRP 2.0 · TC - 6.0 3.5 · TC - 6.0 4.5 · TC - 6.0 6.5 · TC - 6.0 24.4 47.2 62.4 92.8 Ñ Ñ Ñ Ñ 19.0 37.8 50.3 75.3 Ñ Ñ Ñ Ñ ns ns ns ns tCP 1.25 · TC - 4.0 14.9 Ñ 11.6 Ñ ns tASC TC - 4.0 11.2 Ñ 8.5 Ñ ns tCAH 1.75 · TC - 4.0 22.5 Ñ 17.9 Ñ ns tRAL 3 · TC - 4.0 41.5 Ñ 33.5 Ñ ns tRCS 1.25 · TC - 3.8 15.1 Ñ 11.8 Ñ ns tRCH 0.5 · TC - 3.7 3.9 Ñ 2.6 Ñ ns tWCH 1.5 · TC - 4.2 18.5 Ñ 14.6 Ñ ns 146 WR assertion pulse width t WP 2.5 · TC - 4.5 33.4 Ñ 26.8 Ñ ns

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-25 tRWL 2.75 · TC - 4.3 37.4 Ñ 30.1 Ñ ns tCWL 2.5 · TC - 4.3 33.6 Ñ 27.0 Ñ ns (write) tDS 66 MHz: 0.25 · TC - 3.7 0.25 · TC - 3.0 0.1 Ñ Ñ Ñ Ñ 0.1 Ñ Ñ ns ns valid (write) tDH 1.75 · TC - 4.0 22.5 Ñ 17.9 Ñ ns tWCS TC - 4.3 10.9 Ñ 8.2 Ñ ns tROH 2.5 · TC - 4.0 33.9 Ñ 27.3 Ñ ns

153 RD assertion to data valid t GA 66 MHz:

1.75 · TC - 7.5 1.75 · TC - 6.5 Ñ Ñ 19.0 Ñ Ñ Ñ Ñ 15.4 ns ns tGZ Ñ 0.0 Ñ 0.0 Ñ ns 155 WR assertion to data active Ñ 0.75 · TC - 0.3 11.1 Ñ 9.1 Ñ ns

156 WR deassertion to data

Ñ 0.25 · TC Ñ 3.8 Ñ 3.1 ns Notes: 1. The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56307. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t PC equals 3 · TC for read-after-read or write-after-write sequences). 5. There are not any DRAMs fast enough to fit two wait states in Page mode at 100MHz (see Figure 2-14). 6. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 7. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Table 2-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4, 5 (Continued) No. Characteristics Symbol Expression

2-26 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Table 2-11 DRAM Page Mode Timings, Three Wait States1, 2, 3, 4 No. Characteristics Symbol Expression

66 MHz 80 MHz 100 MHz

131 Page mode cycle time t PC 3.5 · TC 53.0 Ñ 43.8 Ñ 35.0 Ñ ns (read) tCAC 66 MHz: 2 · TC - 7.5 2 · TC - 6.5

100 MHz:

2 · TC - 5.7 Ñ Ñ Ñ 22.8 Ñ Ñ Ñ Ñ Ñ Ñ 18.5 Ñ Ñ Ñ Ñ Ñ Ñ 14.3 ns ns ns

133 Column address valid to data

valid (read) t AA 66 MHz: 3 · TC - 7.5 3 · TC - 6.5 3 · TC - 5.7 Ñ Ñ Ñ 37.9 Ñ Ñ Ñ Ñ Ñ Ñ 31.0 Ñ Ñ Ñ Ñ Ñ Ñ 24.3 ns ns ns

134 CAS

valid (read hold time) tOFF Ñ 0.0 Ñ 0.0 Ñ 0.0 Ñ ns 137 CAS assertion pulse width t CAS 2 · TC - 4.0 26.3 Ñ 21.0 Ñ 16.0 Ñ ns

138 Last CAS deassertion to RAS

¥ BRW[1:0] = 00 ¥ BRW[1:0] = 01 ¥ BRW[1:0] = 10 ¥ BRW[1:0] = 11 t CRP 2.25 · TC - 6.0 3.75 · TC - 6.0 4.75 · TC - 6.0 6.75 · TC - 6.0 28.2 51.0 66.2 96.6 Ñ Ñ Ñ Ñ 22.2 40.9 53.4 78.4 Ñ Ñ Ñ Ñ 16.5 31.5 41.5 61.5 Ñ Ñ Ñ Ñ ns ns ns ns

140 Column address valid to CAS

tASC TC - 4.0 11.2 Ñ 8.5 Ñ 6.0 Ñ ns

142 Last column address valid to

tRAL 4 · TC - 4.0 56.6 Ñ 46.0 Ñ 36.0 Ñ ns

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-27 (write) valid (write) 2.5 · TC - 7.5 2.5 · TC - 6.5 2.5 · TC - 5.7 Ñ Ñ Ñ 30.4 Ñ Ñ Ñ Ñ Ñ Ñ 24.8 Ñ Ñ Ñ Ñ Ñ Ñ 19.3 ns ns ns 154 RD deassertion to data not valid6 tGZ Ñ 0.0 Ñ 0.0 Ñ 0.0 Ñ ns Ñ 0.25 · TC Ñ 3.8 Ñ 3.1 Ñ 2.5 ns Notes: 1. The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56307 . 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t PC equals 4 · TC for read-after-read or write-after-write sequences). 5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. 6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Table 2-11 DRAM Page Mode Timings, Three Wait States1, 2, 3, 4 No. Characteristics Symbol Expression

2-28 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Table 2-12 DRAM Page Mode Timings, Four Wait States1, 2, 3, 4 No. Characteristics Symbol Expression 131 Page mode cycle time t PC 4.5 · TC 68.2 Ñ 56.3 Ñ 45.0 Ñ ns (read) tCAC 66 MHz: 2.75 · TC - 7.5 2.75 · TC - 6.5 2.75 · TC - 5.7 Ñ Ñ Ñ 34.2 Ñ Ñ Ñ Ñ Ñ Ñ 27.9 Ñ Ñ Ñ Ñ Ñ Ñ 21.8 ns ns ns data valid (read) t AA 66 MHz: 3.75 · TC - 7.5 3.75 · TC - 6.5 3.75 · TC - 5.7 Ñ Ñ Ñ 49.3 Ñ Ñ Ñ Ñ Ñ Ñ 40.4 Ñ Ñ Ñ Ñ Ñ Ñ 31.8 ns ns ns valid (read hold time) tOFF Ñ 0.0 Ñ 0.0 Ñ 0.0 Ñ ns tRHCP 6 · TC - 4.0 86.9 Ñ 71.0 Ñ 56.0 Ñ ns ¥ BRW[1:0] = 00 ¥ BRW[1:0] = 01 ¥ BRW[1:0] = 10 ¥ BRW[1:0] = 11 t CRP 2.75 · TC - 6.0 4.25 · TC - 6.0 5.25 · TC - 6.0 6.25 · TC - 6.0 35.8 58.6 73.8 89.0 Ñ Ñ Ñ Ñ 28.4 47.2 59.7 72.2 Ñ Ñ Ñ Ñ 21.5 36.5 46.5 56.5 Ñ Ñ Ñ Ñ ns ns ns ns tCP 2 · TC - 4.0 26.3 Ñ 21.0 Ñ 16.0 Ñ ns tASC TC - 4.0 11.2 Ñ 8.5 Ñ 6.0 Ñ ns tRAL 5 · TC - 4.0 71.8 Ñ 58.5 Ñ 46.0 Ñ ns

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-29 (write) valid (write) 3.25 · TC - 7.5 3.25 · TC - 6.5 3.25 · TC - 5.7 Ñ Ñ Ñ 41.7 Ñ Ñ Ñ Ñ Ñ Ñ 34.1 Ñ Ñ Ñ Ñ Ñ Ñ 26.8 ns ns ns 154 RD deassertion to data not valid6 tGZ Ñ 0.0 Ñ 0.0 Ñ 0.0 Ñ ns Ñ 0.25 · TC Ñ 3.8 Ñ 3.1 Ñ 2.5 ns Notes: 1. The number of wait states for page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56307. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t PC equals 3 · TC for read-after-read or write-after-write sequences). 5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Table 2-12 DRAM Page Mode Timings, Four Wait States1, 2, 3, 4 (Continued) No. Characteristics Symbol Expression

2-30 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Figure 2-15 DRAM Page Mode Write Accesses RAS CAS A0–A17 WR RD D0–D23 ColumnRow Data Out Data Out Data Out Last ColumnColumn Add Address Address Address 136 135131 139 141 137 140 142 147 144151 148146 155 156 150 138 145 143 149 AA0473

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-31 Figure 2-16 DRAM Page Mode Read Accesses RAS CAS A0–A17 WR RD D0–D23 Column Last ColumnColumnRow Data In Data InData In Add Address Address Address 136 135131 137 140 141 142 143 152133 153 132 138139 134 154 AA0474

2-32 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Figure 2-17 DRAM Out-of-Page Wait States Selection Guide Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 No. Characteristics3 Symbol Expression

20 MHz4 30 MHz4

157 Random read or write

tRC 5 · TC 250.0 Ñ 166.7 Ñ ns

158 RAS assertion to data

valid (read) tRAC 2.75 · TC - 7.5 Ñ 130.0 Ñ 84.2 ns

159 CAS assertion to data

valid (read) tCAC 1.25 · TC - 7.5 Ñ 55.0 Ñ 34.2 ns

160 Column address valid to

data valid (read) tAA 1.5 · TC - 7.5 Ñ 67.5 Ñ 42.5 ns

161 CAS deassertion to data

not valid (read hold time) t OFF Ñ 0.0 Ñ 0.0 Ñ ns Chip Frequency (MHz) DRAM Type (tRAC ns) 100 66 80 100

8 Wait States

11 Wait States

15 Wait States

Note: This figure should be used for primary selection. For exact and detailed timings, see the following tables. 40 120 AA0475

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-33

162 RAS deassertion to RAS

tRP 1.75 · TC - 4.0 83.5 Ñ 54.3 Ñ ns

163 RAS assertion pulse

tRAS 3.25 · TC - 4.0 158.5 Ñ 104.3 Ñ ns

164 CAS assertion to RAS

tRSH 1.75 · TC - 4.0 83.5 Ñ 54.3 Ñ ns

165 RAS assertion to CAS

tCSH 2.75 · TC - 4.0 133.5 Ñ 87.7 Ñ ns

166 CAS assertion pulse

tCAS 1.25 · TC - 4.0 58.5 Ñ 37.7 Ñ ns

167 RAS assertion to CAS

168 RAS assertion to column

169 CAS deassertion to RAS

tCRP 2.25 · TC - 4.0 108.5 Ñ 71.0 Ñ ns

170 CAS deassertion pulse

tCP 1.75 · TC - 4.0 83.5 Ñ 54.3 Ñ ns

171 Row address valid to

tASR 1.75 · TC - 4.0 83.5 Ñ 54.3 Ñ ns

172 RAS assertion to row

tRAH 1.25 · TC - 4.0 58.5 Ñ 37.7 Ñ ns

173 Column address valid to

tASC 0.25 · TC - 4.0 8.5 Ñ 4.3 Ñ ns

174 CAS assertion to column

tCAH 1.75 · TC - 4.0 83.5 Ñ 54.3 Ñ ns

175 RAS assertion to column

tAR 3.25 · TC - 4.0 158.5 Ñ 104.3 Ñ ns

176 Column address valid to

tRAL 2 · TC - 4.0 96.0 Ñ 62.7 Ñ ns

177 WR deassertion to CAS

tRCS 1.5 · TC - 3.8 71.2 Ñ 46.2 Ñ ns

178 CAS deassertion to WR

tRCH 0.75 · TC - 3.7 33.8 Ñ 21.3 Ñ ns

179 RAS deassertion to WR

tRRH 0.25 · TC - 3.7 8.8 Ñ 4.6 Ñ ns Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression

2-34 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A)

180 CAS assertion to WR

tWCH 1.5 · TC - 4.2 70.8 Ñ 45.8 Ñ ns

181 RAS assertion to WR

tWCR 3 · TC - 4.2 145.8 Ñ 95.8 Ñ ns

182 WR assertion pulse

tWP 4.5 · TC - 4.5 220.5 Ñ 145.5 Ñ ns

183 WR assertion to RAS

tRWL 4.75 · TC - 4.3 233.2 Ñ 154.0 Ñ ns

184 WR assertion to CAS

tCWL 4.25 · TC - 4.3 208.2 Ñ 137.4 Ñ ns

185 Data valid to CAS

assertion (write) tDS 2.25 · TC - 4.0 108.5 Ñ 71.0 Ñ ns

186 CAS assertion to data

not valid (write) tDH 1.75 · TC - 4.0 83.5 Ñ 54.3 Ñ ns

187 RAS assertion to data

not valid (write) tDHR 3.25 · TC - 4.0 158.5 Ñ 104.3 Ñ ns

188 WR assertion to CAS

tWCS 3 · TC - 4.3 145.7 Ñ 95.7 Ñ ns

189 CAS assertion to RAS

assertion (refresh) tCSR 0.5 · TC - 4.0 21.0 Ñ 12.7 Ñ ns

190 RAS deassertion to CAS

assertion (refresh) tRPC 1.25 · TC - 4.0 58.5 Ñ 37.7 Ñ ns

191 RD assertion to RAS

tROH 4.5 · TC - 4.0 221.0 Ñ 146.0 Ñ ns

192 RD assertion to data

tGA 4 · TC - 7.5 Ñ 192.5 Ñ 125.8 ns

193 RD deassertion to data

tGZ Ñ 0.0 Ñ 0.0 Ñ ns

194 WR assertion to data

Ñ 0.75 · TC - 0.3 37.2 Ñ 24.7 Ñ ns

195 WR deassertion to data

Ñ 0.25 · TC Ñ 12.5 Ñ 8.3 ns Notes: 1. The number of wait states for out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (see Figure 2-17). Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-35 Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 No. Characteristics3 Symbol Expression4

157 Random read or write cycle

tRC 9 · TC 136.4 Ñ 112.5 Ñ 90.0 Ñ ns

158 RAS assertion to data valid

(read) tRAC 66 MHz: 4.75 · TC - 7.5 4.75 · TC - 6.5 4.75 · TC - 5.7 Ñ Ñ Ñ 64.5 Ñ Ñ Ñ Ñ Ñ Ñ 52.9 Ñ Ñ Ñ Ñ Ñ Ñ 41.8 ns ns ns

159 CAS

(read) tCAC 66 MHz: 2.25 · TC - 7.5 2.25 · TC - 6.5 2.25 · TC - 5.7 Ñ Ñ Ñ 26.6 Ñ Ñ Ñ Ñ Ñ Ñ 21.6 Ñ Ñ Ñ Ñ Ñ Ñ 16.8 ns ns ns data valid (read) t AA 66 MHz: 3 · TC - 7.5 3 · TC - 6.5 3 · TC - 5.7 Ñ Ñ Ñ 40.0 Ñ Ñ Ñ Ñ Ñ Ñ 31.0 Ñ Ñ Ñ Ñ Ñ Ñ 24.3 ns ns ns

161 CAS

valid (read hold time) tOFF 0.0 Ñ 0.0 Ñ 0.0 Ñ ns

2-36 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A)

171 Row address valid to RAS

tRAL 4 · TC - 4.0 56.6 Ñ 46.0 Ñ 36.0 Ñ ns tRCS 2 · TC - 3.8 26.5 Ñ 21.2 Ñ 16.2 Ñ ns

178 CAS deassertion to WR5

179 RAS deassertion to WR5

tRRH 66 MHz: 0.25 · TC - 3.7 0.25 · TC - 3.0 0.25 · TC - 2.4 0.1 Ñ Ñ Ñ Ñ Ñ Ñ 0.1 Ñ Ñ Ñ Ñ Ñ Ñ 0.1 Ñ Ñ Ñ ns ns ns

180 CAS

tWCH 3 · TC - 4.2 41.3 Ñ 33.3 Ñ 25.8 Ñ ns

185 Data valid to CAS assertion

(write)

186 CAS assertion to data not

valid (write)

187 RAS assertion to data not

valid (write) Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression4

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-37 assertion (refresh) assertion (refresh)

192 RD assertion to data valid t GA 66 MHz:

7.5 · TC - 7.5 7.5 · TC - 6.5 7.5 · TC - 5.7 Ñ Ñ Ñ 106.1 Ñ Ñ Ñ Ñ Ñ Ñ 87.3 Ñ Ñ Ñ Ñ Ñ Ñ 69.3 ns ns ns 193 RD deassertion to data not valid3 tGZ 0.0 0.0 Ñ 0.0 Ñ 0.0 Ñ ns Ñ 0.25 · TC Ñ 3.8 Ñ 3.1 Ñ 2.5 ns Notes: 1. The number of wait states for out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4. The asynchronous delays specified in the expressions are valid for DSP56307. 5. Either t RCH or tRRH must be satisfied for read cycles. Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression4

2-38 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 No. Characteristics3 Symbol Expression4 tRC 12 · TC 181.8 Ñ 150.0 Ñ 120.0 Ñ ns (read) tRAC 66 MHz: 6.25 · TC - 7.5 6.25 · TC - 6.5 6.25 · TC - 5.7 Ñ Ñ Ñ 87.2 Ñ Ñ Ñ Ñ Ñ Ñ 71.6 Ñ Ñ Ñ Ñ Ñ Ñ 56.8 ns ns ns (read) tCAC 66 MHz: 3.75 · TC - 7.5 3.75 · TC - 6.5 3.75 · TC - 5.7 Ñ Ñ Ñ 49.3 Ñ Ñ Ñ Ñ Ñ Ñ 40.4 Ñ Ñ Ñ Ñ Ñ Ñ 31.8 ns ns ns data valid (read) t AA 66 MHz: 4.5 · TC - 7.5 4.5 · TC - 6.5 4.5 · TC - 5.7 Ñ Ñ Ñ 60.7 Ñ Ñ Ñ Ñ Ñ Ñ 49.8 Ñ Ñ Ñ Ñ Ñ Ñ 39.3 ns ns ns valid (read hold time) tOFF 0.0 Ñ 0.0 Ñ 0.0 Ñ ns

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-39 tRAL 6 · TC - 4.0 86.9 Ñ 71.0 Ñ 56.0 Ñ ns tRRH 66 MHz: 0.25 · TC - 3.7 0.25 · TC - 3.0 0.25 · TC - 2.4 0.1 Ñ Ñ Ñ Ñ Ñ Ñ 0.1 Ñ Ñ Ñ Ñ Ñ Ñ 0.1 Ñ Ñ Ñ ns ns ns tWCH 5 · TC - 4.2 71.6 Ñ 58.3 Ñ 45.8 Ñ ns (write) valid (write) valid (write) Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression4

2-40 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) assertion (refresh) assertion (refresh) 10 · TC - 7.5 10 · TC - 6.5 10 · TC - 5.7 Ñ Ñ Ñ 144.0 Ñ Ñ Ñ Ñ Ñ Ñ 118.5 Ñ Ñ Ñ Ñ Ñ Ñ 94.3 ns ns ns 193 RD deassertion to data not valid3 tGZ Ñ 0.0 Ñ 0.0 Ñ 0.0 Ñ ns Ñ 0.25 · TC Ñ 3.8 Ñ 3.1 Ñ 2.5 ns Notes: 1. The number of wait states for out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4. The asynchronous delays specified in the expressions are valid for DSP56307. 5. Either t RCH or tRRH must be satisfied for read cycles. Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression4

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-41 Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 No. Characteristics3 Symbol Expression tRC 16 · TC 242.4 Ñ 200.0 Ñ 160.0 Ñ ns (read) tRAC 66 MHz: 8.25 · TC - 7.5 8.25 · TC - 6.5 8.25 · TC - 5.7 Ñ Ñ Ñ 117.5 Ñ Ñ Ñ Ñ Ñ Ñ 96.6 Ñ Ñ Ñ Ñ Ñ Ñ 76.8 ns ns ns (read) tCAC 66 MHz: 4.75 · TC - 7.5 4.75 · TC - 6.5 4.75 · TC - 5.7 Ñ Ñ Ñ 64.5 Ñ Ñ Ñ Ñ Ñ Ñ 52.9 Ñ Ñ Ñ Ñ Ñ Ñ 41.8 ns ns ns

160 Column address valid to data

valid (read) t AA 66 MHz: 5.5 · TC - 7.5 5.5 · TC - 6.5 5.5 · TC - 5.7 Ñ Ñ Ñ 75.8 Ñ Ñ Ñ Ñ Ñ Ñ 62.3 Ñ Ñ Ñ Ñ Ñ Ñ 49.3 ns ns ns valid (read hold time) tOFF 0.0 0.0 Ñ 0.0 Ñ 0.0 Ñ ns

2-42 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A)

172 RAS assertion to row address

173 Column address valid to CAS

176 Column address valid to RAS

tRAL 7 · TC - 4.0 102.1 Ñ 83.5 Ñ 66.0 Ñ ns tRCS 5 · TC - 3.8 72.0 Ñ 58.7 Ñ 46.2 Ñ ns tRRH 66 MHz: 0.25 · TC - 3.7 0.25 · TC - 3.0 0.25 · TC - 2.4 0.1 Ñ Ñ Ñ Ñ Ñ Ñ 0.1 Ñ Ñ Ñ Ñ Ñ Ñ 0.1 Ñ Ñ Ñ ns ns ns tWCH 6 · TC - 4.2 86.7 Ñ 70.8 Ñ 55.8 Ñ ns tCWL 66Ð80 MHz: 14.25 · TC - 4.3 14.75 · T C - 4.3 211.6 Ñ Ñ Ñ 180.1 Ñ Ñ Ñ Ñ 143.2 Ñ Ñ ns ns (write) valid (write) Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-43 valid (write) assertion (refresh) assertion (refresh) 14 · TC - 7.5 14 · TC - 6.5 14 · TC - 5.7 Ñ Ñ Ñ 204.6 Ñ Ñ Ñ Ñ Ñ Ñ 168.5 Ñ Ñ Ñ Ñ Ñ Ñ 134.3 ns ns ns 193 RD deassertion to data not valid3 tGZ Ñ 0.0 Ñ 0.0 Ñ 0.0 Ñ ns

195 WR deassertion to data high

Ñ 0.25 · TC Ñ 3.8 Ñ 3.1 Ñ 2.5 ns Notes: 1. The number of wait states for out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4. Either t RCH or tRRH must be satisfied for read cycles. Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression

2-44 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Figure 2-18 DRAM Out-of-Page Read Access RAS CAS A0–A17 WR RD D0–D23 Data Row Address Column Address In 157 163 165 162162 169 170 171 168 167 164 166 173 174 175 172 177 176 191 160 168 159 193 161 192 158 179 AA0476

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-45 Figure 2-19 DRAM Out-of-Page Write Access RAS CAS A0–A17 WR RD D0–D23 Data Out Column AddressRow Address 162 163 165 162 157 169 170 167 168 164 166 171 173 174 176 172 181 175 180188 182 184 183 187 185 194 186 195 AA0477

2-46 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Figure 2-20 DRAM Refresh Access RAS CAS WR 157 163 162162 190 170 165 189 177 AA0478

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-47 Synchronous Timings Table 2-17 External Bus Synchronous Timings1 No. Characteristics Expression2,3

100 MHz4

198 CLKOUT high to address, and AA valid 5 0.25 · TC + 4.0 Ñ 6.5 ns 199 CLKOUT high to address, and AA invalid 5 0.25 · TC 2.5 Ñ ns 200 TA valid to CLKOUT high (setup time) Ñ 4.0 Ñ ns 201 CLKOUT high to TA invalid (hold time) Ñ 0.0 Ñ ns 202 CLKOUT high to data out active 0.25 · TC 2.5 Ñ ns 203 CLKOUT high to data out valid 0.25 · TC + 4.0 3.3 6.5 ns 204 CLKOUT high to data out invalid 0.25 · TC 2.5 Ñ ns 205 CLKOUT high to data out high impedance 0.25 · TC Ñ 2.5 ns 206 Data in valid to CLKOUT high (setup) Ñ 4.0 Ñ ns 207 CLKOUT high to data in invalid (hold) Ñ 0.0 Ñ ns

208 CLKOUT high to RD

assertion 0.75 · TC + 4.0 8.2 11.5 ns 209 CLKOUT high to RD deassertion Ñ 0.0 4.0 ns

210 CLKOUT high to WR assertion6

¥ 100 MHz ¥ All frequencies For WS = 1 or WS ‡ 4 0.5 · T C + 4.3 For 2 £ WS £ 3 6.3 1.3 9.3 4.3 ns ns 211 CLKOUT high to WR deassertion Ñ 0.0 3.8 ns Notes: 1. External bus synchronous timings should be used only for reference to the clock and not for relative timings. 2. WS is the number of wait states specified in the BCR. 3. The asynchronous delays specified in the expressions are valid for DSP56307. 4. For operation at greater than 80MHz, we recommend that you set the asynchronous bus enable bit (ABE) in the OMR to activate asynchronous bus arbitration. 5. T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to determine whether the access referenced by A0ÐA23 is internal or external, when this mode is enabled 6. If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

2-48 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Figure 2-21 Synchronous Bus Timings 1 WS (BCR Controlled) WR RD Data OutD0–D23 CLKOUT TA Data InD0–D23 A0–A17 AA0–AA3 199 201 200 211 210 208 209 207 198 205 204203 202 206 AA0479

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-49 Figure 2-22 Synchronous Bus Timings, SRAM, 2 or More WS, TA Controlled A0–A17 WR RD Data OutD0–D23 AA0–AA3 CLKOUT TA Data InD0–D23 198 199 201 200 201 211 209 207 208 210 200 203 202 205 204 206 AA1615

2-50 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Arbitration Timings Table 2-18 Arbitration Bus Timings1 No. Characteristics Expression 212 CLKOUT high to BR assertion/deassertion2 Ñ 1.0 4.0 ns 213 BG asserted/deasserted to CLKOUT high (setup)3 Ñ 4.0 Ñ ns 214 CLKOUT high to BG deasserted/asserted (hold)3 Ñ 0.0 Ñ ns 215 BB deassertion to CLKOUT high (input setup)3 Ñ 4.0 Ñ ns 216 CLKOUT high to BB assertion (input hold)3 Ñ 0.0 Ñ ns 217 CLKOUT high to BB assertion (output) Ñ 1.0 4.0 ns 218 CLKOUT high to BB deassertion (output) Ñ 1.0 4.0 ns 219 BB high to BB high impedance (output) Ñ Ñ 4.5 ns 220 CLKOUT high to address and controls active 0.25 · TC 2.5 Ñ ns 221 CLKOUT high to address and controls high impedance 0.25 · TC Ñ 2.5 ns 222 CLKOUT high to AA active 0.25 · TC 2.5 Ñ ns 223 CLKOUT high to AA deassertion 4 0.25 · TC + 4.0 3.2 6.5 ns 224 CLKOUT high to AA high impedance 0.75 · TC Ñ 7.5 ns 225 BG deassertion to BB assertion (output)5 2.5 · TC + 5 Ñ 30 ns

226 BB (input) assertion to BG assertion5 2 · TC + 5 25 Ñ ns

Notes: 1. The asynchronous delays specified in the expressions are valid for DSP56307. 2. T212 is valid for address trace mode when the ATE bit (Bit 15) in the OMR is set. BR is deasserted for internal accesses and asserted for external accesses. 3. T213, T214, T215, and T216 are valid only when the ABE bit (Bit 13) in the OMR is cleared. 4. When an expression appears with both a minimum and maximum value, use the expression to calculate worst case. 5. Asynchronous bus arbitration mode inserts a delay between changes in BG and BB until the change is actually ÒseenÓ by the chip internally (i.e., this delay is required because internal chip operation is synchronous). T225 and T226 are valid for asynchronous bus arbitration mode only (i.e., when the ABE bit in the OMR is set). If ABE is set, T213, T214, T215, and T216 are not required for proper operation, and BG and BB do not have setup and input hold requirements with respect to CLKOUT. The delay between the deassertion of BG for a DSP56307 and the assertion of a second BG to another DSP56307 must be greater than the sum of T225 (for the first chip) and T226 (for the second chip) to prevent bus access by more than one DSP at a time.

External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-51 Figure 2-23 Bus Acquisition Timings A0–A17 BB AA0–AA3 CLKOUT BR BG RD , WR 212 214 216 215 220 217 213 222 AA0481

2-52 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) Figure 2-24 Bus Release Timings Case 1 (BRT Bit in OMR Cleared) A0–A17 BB AA0–AA3 CLKOUT BR BG RD , WR 212 214 218 221 224 223 213 219 AA0482

2-54 DSP56307 Technical Data MOTOROLA Specifications Host Interface Timing HOST INTERFACE TIMING Figure 2-27 Bus Arbitration Mode Timing for Issuing a New BG Signal (ABE Bit in OMR Set) Table 2-19 Host Interface Timing1, 2 No. Characteristic3 Expression

317 Read data strobe assertion width 4 HACK assertion

TC + 9.9 19.9 Ñ ns

318 Read data strobe deassertion width 4 HACK

Ñ 9.9 Ñ ns

319 Read data strobe deassertion width 4 after ÒLast Data

RegisterÓ reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK deassertion width after ÒLast Data RegisterÓ reads5,6 2.5 · TC + 6.6 31.6 Ñ ns 320 Write data strobe assertion width 8 Ñ 13.2 Ñ ns

321 Write data strobe deassertion width 8

HACK write deassertion width: ¥ after HcTR, HCVR, and ÒLast Data Register Writes ¥ after TXH:TXM writes (with HBE=0), TXM:TXL writes (with HBE=1) 2.5 · TC + 6.6 2.5 · TC + 8.3 2.5 x TC + 6.6 31.6 39.5 31.6 Ñ @80 MHz @100 MHz @80 MHz @100 MHz 322 HAS assertion width Ñ 9.9 Ñ ns 323 HAS deassertion to data strobe assertion9 Ñ 0.0 Ñ ns

324 Host data input setup time before write data strobe

Ñ 9.9 Ñ ns

325 Host data input hold time after write data strobe

Ñ 3.3 Ñ ns BB BG 226 (input) AA1426

MOTOROLA DSP56307 Technical Data 2-55

326 Read data strobe assertion to output data active from

high impedance4 HACK assertion to output data active from high impedance Ñ 3.3 Ñ ns

327 Read data strobe assertion to output data valid 4

HACK assertion to output data valid Ñ Ñ 23.54 ns

328 Read data strobe deassertion to output data high

HACK deassertion to output data high impedance Ñ Ñ 9.9 ns

329 Output data hold time after read data strobe

Output data hold time after HACK deassertion Ñ 4.1 Ñ ns 330 HCS assertion to read data strobe deassertion4 TC + 9.9 19.9 Ñ ns 331 HCS assertion to write data strobe deassertion8 Ñ 9.9 Ñ ns 332 HCS assertion to output data valid Ñ Ñ 16.5 ns 333 HCS hold time after data strobe deassertion9 Ñ 0.0 Ñ ns

334 Address (HAD0ÐHAD7) setup time before HAS

deassertion (HMUX=1) Ñ 4.7 Ñ ns

335 Address (HAD0ÐHAD7) hold time after HAS

deassertion (HMUX=1) Ñ 3.3 Ñ ns

336 HA8ÐHA10 (HMUX=1), HA0ÐHA2 (HMUX=0),

HR/W setup time before data strobe assertion9 ¥ Read ¥ Write Ñ 4.7 Ñ Ñ ns ns

337 HA8ÐHA10 (HMUX=1), HA0ÐHA2 (HMUX=0),

hold time after data strobe deassertion9 Ñ 3.3 Ñ ns

338 Delay from read data strobe deassertion to host

request assertion for ÒLast Data RegisterÓ read4, 5, 10 2 · TC + 20.6 36.5 Ñ ns

339 Delay from write data strobe deassertion to host

request assertion for ÒLast Data RegisterÓ write5, 8, 10 1.5 · TC + 16.5 31.5 Ñ ns

340 Delay from data strobe assertion to host request

deassertion for ÒLast Data RegisterÓ read or write (HROD=0) 5, 9, 10 Ñ Ñ 20.24 ns

341 Delay from data strobe assertion to host request

deassertion for ÒLast Data RegisterÓ read or write (HROD=1, open drain host request) 5, 9, 10, 11 Ñ Ñ 300.0 ns Table 2-19 Host Interface Timing1, 2 (Continued) No. Characteristic3 Expression

2-56 DSP56307 Technical Data MOTOROLA Specifications Host Interface Timing Notes: 1. See Host Port Usage Considerations in the DSP56307 User’s Manual. 2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. 3. V CCQL = 2.5 V – 0.25 V; TJ = -40ûC to +100 ûC, CL = 50 pF 4. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. 5. The Òlast data registerÓ is the register at address $7, which is the last location to be read or written in data transfers. This is RXL/TXL in the little endian mode (HBE = 0), or RXH/TXH in the big endian mode (HBE = 1). 6. This timing is applicable only if a read from the Òlast data registerÓ is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode 10. The host request is HREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 11. In this calculation, the host request signal is pulled up by a 4.7 k W resistor in the open-drain mode. Figure 2-28 Host Interrupt Vector Register (IVR) Read Timing Diagram Table 2-19 Host Interface Timing1, 2 (Continued) No. Characteristic3 Expression H0–H7 HREQ 329 317 318 328 326 327 AA1105

MOTOROLA DSP56307 Technical Data 2-57 Figure 2-29 Read Timing Diagram, Non-Multiplexed Bus HRD , HDS HA0–HA2 HCS H0–H7 HREQ , 327 332 319 318 317 330 329 337336 328 326 338 341 340 333 AA0484G HRRQ , HTRQ

2-58 DSP56307 Technical Data MOTOROLA Specifications Host Interface Timing Figure 2-30 Write Timing Diagram, Non-Multiplexed Bus HWR , HDS HA0–HA2 HCS H0–H7 HREQ , HRRQ , HTRQ 336 331 337 321 320 324 325 339340 341 333 AA0485G

MOTOROLA DSP56307 Technical Data 2-59 Figure 2-31 Read Timing Diagram, Multiplexed Bus HRD , HDS HA8–HA10 HAS HAD0–HAD7 HREQ , HRRQ , HTRQ Address Data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 AA0486G 322

2-60 DSP56307 Technical Data MOTOROLA Specifications Host Interface Timing Figure 2-32 Write Timing Diagram, Multiplexed Bus HWR , HDS HA8–HA10 HREQ , HRRQ , HTRQ HAS HAD0–HAD7 Address Data 320 321 325 324 335 341 339 336 334 340 322 323 AA0487G

MOTOROLA DSP56307 Technical Data 2-61 SCI TIMING Table 2-20 SCI Timing No. Characteristics1 Symbol Expression

400 Synchronous clock cycle t SCC

2 8 · TC 80.0 Ñ ns 401 Clock low period Ñ t SCC/2 - 10.0 30.0 Ñ ns 402 Clock high period Ñ t SCC/2 - 10.0 30.0 Ñ ns

403 Output data setup to clock falling

edge (internal clock) Ñt SCC/4 + 0.5 · TC -17.0 8.0 Ñ ns

404 Output data hold after clock

rising edge (internal clock) Ñt SCC/4 - 0.5 · TC 15.0 Ñ ns

405 Input data setup time before

clock rising edge (internal clock) Ñt SCC/4 + 0.5 · TC + 25.0 50.0 Ñ ns

406 Input data not valid before clock

rising edge (internal clock) Ñt SCC/4 + 0.5 · TC - 5.5 Ñ 19.5 ns

407 Clock falling edge to output data

valid (external clock) Ñ Ñ Ñ 32.0 ns

408 Output data hold after clock

rising edge (external clock) ÑT C + 8.0 18.0 Ñ ns

409 Input data setup time before

clock rising edge (external clock) Ñ Ñ 0.0 Ñ ns

410 Input data hold time after clock

rising edge (external clock) Ñ Ñ 9.0 Ñ ns

411 Asynchronous clock cycle t ACC

3 64 · TC 640.0 Ñ ns 412 Clock low period Ñ t ACC/2 - 10.0 310.0 Ñ ns 413 Clock high period Ñ t ACC/2 - 10.0 310.0 Ñ ns

414 Output data setup to clock rising

edge (internal clock) Ñt ACC/2 - 30.0 290.0 Ñ ns

415 Output data hold after clock

rising edge (internal clock) Ñt ACC/2 - 30.0 290.0 Ñ ns Notes: 1. V CCQL = 2.5 V – 0.25 V; TJ = -40ûC to +100 ûC, CL = 50 pF 2. t SCC = synchronous clock cycle time (For internal clock, tSCC is determined by the SCI clock control register and TC.) 3. t ACC = asynchronous clock cycle time; value given for 1x Clock mode (For internal clock, tACC is determined by the SCI clock control register and TC.)

MOTOROLA DSP56307 Technical Data 2-63 ESSI0/ESSI1 TIMING Table 2-21 ESSI Timings No. Characteristics1, 2, 3 Symbol Expression

100 MHz Cond-

430 Clock cycle 5 tSSICC 3 · TC

4 · TC 30.0 40.0 Ñ Ñ x ck i ck ns

431 Clock high period

¥ For internal clock ¥ For external clock Ñ 2 · T C - 10.0 1.5 · TC 10.0 15.0 Ñ Ñ ns ns

432 Clock low period

¥ For internal clock ¥ For external clock Ñ 2 · T C - 10.0 1.5 · TC 10.0 15.0 Ñ Ñ ns ns

433 RXC rising edge to FSR out (bl) high Ñ Ñ Ñ

Ñ 37.0 22.0 x ck i ck a ns

434 RXC rising edge to FSR out (bl) low Ñ Ñ Ñ

Ñ 37.0 22.0 x ck i ck a ns

435 RXC rising edge to FSR out (wr)

ÑÑ Ñ Ñ 39.0 24.0 x ck i ck a ns

436 RXC rising edge to FSR out (wr)

ÑÑ Ñ Ñ 39.0 24.0 x ck i ck a ns

437 RXC rising edge to FSR out (wl)

ÑÑ Ñ Ñ 36.0 21.0 x ck i ck a ns

438 RXC rising edge to FSR out (wl) low Ñ Ñ Ñ

Ñ 37.0 22.0 x ck i ck a ns

439 Data in setup time before RXC (SCK

in Synchronous mode) falling edge Ñ Ñ 0.0 19.0 Ñ Ñ x ck i ck ns

440 Data in hold time after RXC falling

Ñ Ñ 5.0 3.0 Ñ Ñ x ck i ck ns

441 FSR input (bl, wr) high before RXC

Ñ Ñ 23.0 1.0 Ñ Ñ x ck i ck a ns

442 FSR input (wl) high before RXC

Ñ Ñ 23.0 1.0 Ñ Ñ x ck i ck a ns

443 FSR input hold time after RXC

Ñ Ñ 3.0 0.0 Ñ Ñ x ck i ck a ns

444 Flags input setup before RXC

Ñ Ñ 0.0 19.0 Ñ Ñ x ck i ck s ns

445 Flags input hold time after RXC

Ñ Ñ 6.0 0.0 Ñ Ñ x ck i ck s ns

2-64 DSP56307 Technical Data MOTOROLA Specifications ESSI0/ESSI1 Timing

446 TXC rising edge to FST out (bl) high Ñ Ñ Ñ

Ñ 29.0 15.0 x ck i ck ns

447 TXC rising edge to FST out (bl) low Ñ Ñ Ñ

Ñ 31.0 17.0 x ck i ck ns

448 TXC rising edge to FST out (wr)

ÑÑ Ñ Ñ 31.0 17.0 x ck i ck ns

449 TXC rising edge to FST out (wr)

ÑÑ Ñ Ñ 33.0 19.0 x ck i ck ns

450 TXC rising edge to FST out (wl)

ÑÑ Ñ Ñ 30.0 16.0 x ck i ck ns

451 TXC rising edge to FST out (wl) low Ñ Ñ Ñ

Ñ 31.0 17.0 x ck i ck ns

452 TXC rising edge to data out enable

ÑÑ Ñ Ñ 31.0 17.0 x ck i ck ns

453 TXC rising edge to Transmitter #0

ÑÑ Ñ Ñ 34.0 20.0 x ck i ck ns 454 TXC rising edge to data out valid Ñ 35 + 0.5 · TC 21.0 Ñ Ñ 40.0 21.0 x ck i ck ns

455 TXC rising edge to data out high

ÑÑ Ñ Ñ 31.0 16.0 x ck i ck ns

456 TXC rising edge to Transmitter #0

ÑÑ Ñ Ñ 34.0 20.0 x ck i ck ns

457 FST input (bl, wr) setup time before

Ñ Ñ 2.0 21.0 Ñ Ñ x ck i ck ns

458 FST input (wl) to data out enable

Ñ Ñ Ñ 27.0 —n s

459 FST input (wl) to Transmitter #0

Ñ Ñ Ñ 31.0 Ñ ns

460 FST input (wl) setup time before

Ñ Ñ 2.0 21.0 Ñ Ñ x ck i ck ns

461 FST input hold time after TXC

Ñ Ñ 4.0 0.0 Ñ Ñ x ck i ck ns

462 Flag output valid after TXC rising

ÑÑ Ñ Ñ 32.0 18.0 x ck i ck ns Table 2-21 ESSI Timings (Continued) No. Characteristics1, 2, 3 Symbol Expression

MOTOROLA DSP56307 Technical Data 2-65 Notes: 1. V CCQL = 2.5 V – 0.25 V; TJ = -40ûC to +100 ûC, CL = 50 pF 2. i ck = Internal Clock x ck = External Clock i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous Mode (Synchronous implies that TXC and RXC are the same clock) 3. bl = bit length wl = word length wr = word length relative 4. TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) Receive Frame Sync 5. For the internal clock, the external clock cycle is defined by Icyc and the ESSI control register. 6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as Bit Length Frame Sync signal), until the one before last bit clock of the first word in frame. 7. Periodically sampled and not 100% tested Table 2-21 ESSI Timings (Continued) No. Characteristics1, 2, 3 Symbol Expression

2-66 DSP56307 Technical Data MOTOROLA Specifications ESSI0/ESSI1 Timing Figure 2-35 ESSI Transmitter Timing Last Bit See Note Note: In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period. First Bit 430 432 446 447 450 451 455 454454 452 459 456453 461 457 458 460 461 462 431 AA0490 TXC (Input/ Output) FST (Bit) Out FST (Word) Out Data Out Transmitter #0 Drive Enable FST (Bit) In FST (Word) In Flags Out

MOTOROLA DSP56307 Technical Data 2-67 Figure 2-36 ESSI Receiver Timing Last BitFirst Bit 430 432 433 437 438 440 439 443441 442 443 445444 431 434 RXC (Input/ Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In AA0491

2-68 DSP56307 Technical Data MOTOROLA Specifications Timer Timing TIMER TIMING Table 2-22 Timer Timing No. Characteristics Expression 480 TIO Low 2 · TC + 2.0 22.0 Ñ ns 481 TIO High 2 · TC + 2.0 22.0 Ñ ns

482 Timer setup time from TIO (Input) assertion to

Ñ 9.0 10.0 ns

483 Synchronous timer delay time from CLKOUT

rising edge to the external memory access address out valid caused by first interrupt instruction execution 10.25 · T C + 1.0 103.5 Ñ ns

484 CLKOUT rising edge to TIO (Output) assertion

¥ Minimum ¥ Maximum 0.5 · T C + 3.5 0.5 · TC + 19.8 8.5 Ñ Ñ 24.8 ns ns

485 CLKOUT rising edge to TIO (Output) deassertion

¥ Minimum ¥ Maximum 0.5 · T C + 3.5 0.5 · TC + 19.0 8.5 Ñ Ñ 24.8 ns ns Note: V CCQL = 2.5 V – 0.25 V; TJ = Ð40ûC to +100 ûC, CL = 50 pF Figure 2-37 TIO Timer Event Input Restrictions Figure 2-38 Timer Interrupt Generation TIO 481480 AA0492 CLKOUT TIO (Input) First Interrupt Instruction Execution Address 482 483 AA0493

MOTOROLA DSP56307 Technical Data 2-69 Figure 2-39 External Pulse Generation CLKOUT TIO (Output) 484 485 AA0494

2-70 DSP56307 Technical Data MOTOROLA Specifications GPIO Timing GPIO TIMING Table 2-23 GPIO Timing No. Characteristics Expression

490 CLKOUT edge to GPIO out valid (GPIO

out delay time) Ñ Ñ 31.0 ns

491 CLKOUT edge to GPIO out not valid

(GPIO out hold time) Ñ 3.0 Ñ ns

492 GPIO In valid to CLKOUT edge (GPIO in

set-up time) Ñ 12.0 Ñ ns

493 CLKOUT edge to GPIO in not valid (GPIO

in hold time) Ñ 0.0 Ñ ns

494 Fetch to CLKOUT edge before GPIO

6.75 · TC 67.5 Ñ ns Note: V CCQL = 2.5 V – 0.25 V; TJ = -40ûC to +100 ûC, CL = 50 pF Figure 2-40 GPIO Timing ValidGPIO (Input) GPIO (Output) CLKOUT (Output) Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. A0–A17 490 491 492 494 493 AA0495

MOTOROLA DSP56307 Technical Data 2-71 JTAG TIMING Table 2-24 JTAG Timing No. Characteristics All frequencies Unit Min Max 500 TCK frequency of operation (1/(T C · 3); maximum 22 MHz) 0.0 22.0 MHz 501 TCK cycle time in Crystal mode 45.0 Ñ ns 502 TCK clock pulse width measured at 1.5 V 20.0 Ñ ns 503 TCK rise and fall times 0.0 3.0 ns 504 Boundary scan input data setup time 5.0 Ñ ns 505 Boundary scan input data hold time 24.0 Ñ ns 506 TCK low to output data valid 0.0 40.0 ns 507 TCK low to output high impedance 0.0 40.0 ns 508 TMS, TDI data setup time 5.0 Ñ ns 509 TMS, TDI data hold time 25.0 Ñ ns 510 TCK low to TDO data valid 0.0 44.0 ns 511 TCK low to TDO high impedance 0.0 44.0 ns

512 TRST

assert time 100.0 Ñ ns 513 TRST setup time to TCK low 40.0 Ñ ns Notes: 1. V CCQL = 2.5 V – 0.25 V; TJ = -40ûC to +100 ûC, CL = 50 pF 2. All timings apply to OnCE module data transfers, because it uses the JTAG port as an interface. Figure 2-41 Test Clock Input Timing Diagram TCK (Input) VM VMVIH VIL 501 502 502 503503 AA0496

MOTOROLA DSP56307 Technical Data 2-73 O nCE MODULE TIMING Figure 2-44 TRST Timing Diagram Table 2-25 OnCE Module Timing No. Characteristics Expression

500 TCK frequency of operation 1/(TC · 3),

max 22.0 MHz 0.0 22.0 MHz 514 DE assertion time in order to enter Debug mode 1.5 · TC + 10.0 25.0 Ñ ns

515 Response time when DSP56307 is executing NOP

instructions from internal memory 5.5 · TC + 30.0 Ñ 85.0 ns 516 Debug acknowledge assertion time 3 · TC + 10.0 40.0 Ñ ns Note: V CCQL = 2.5 V – 0.25 V; TJ = -40ûC to +100 ûC, CL = 50 pF Figure 2-45 OnCEÑDebug Request TCK (Input) TRST (Input) 513 512 AA0499 DE 516515 514 AA0500

2-74 DSP56307 Technical Data MOTOROLA Specifications OnCE Module TimIng

MOTOROLA DSP56307 Technical Data 3-1 SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The DSP56307 is available in a 196-pin Plastic Ball Grid Array (PBGA) package.

Pin-out and Package Information MOTOROLA DSP56307 Technical Data 3-3 Figure 3-2 DSP56307 Plastic Ball Grid Array (PBGA), Bottom View Bottom View 134256781014 13 12 11 9 VCCQH HACK HREQ B C D E F G H N M L J K HA0 HRW HDS HCS IRQD H5NC HA1HA2 VCCD VCCQL IRQA D19 D18VCCD VCCD VCCQL VCCS VCCQH GNDGNDGNDGNDGND GND GND GND GND GND GND GND GND GNDGND GND GND GND GND GND GND GNDGND GND GND GND GND GNDGNDGND V CCA VCCC VCCA VCCA VCCP VCCH VCCS VCCQL GND GND GND GND GND GND V CCD VCCQH IRQC H4 H6VCCQL D12 D11 D15 A17A16 A1A2 PB0 TIO1 RXD TIO2 TIO0 SCK1TXD SC12 SC11 STD1 SCK0 SRD0 SRD1 STD0 SC02 SC01 TDO TMS DE TA TDI TCK A15 A12 BG GND P PINIT AA0 TRST SCLK VCCC P AIRQBD23 D22 D21D20D17 D16D14 D13D10D8 D6D4 D2 D1 A14 A13 A11 A10 A9 A8 A4 A3 AA1 RD WR BB BR BCLK BCLK CLK OUT XTAL CAS AA3 AA2 GND P1 PCAP RESET SC00 SC10 NC NC NC NC GNDGND GND GNDGND GNDGND GNDGND GNDGND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDGND GND GND EXTAL

3-4 DSP56307 Technical Data MOTOROLA Packaging Pin-out and Package Information Table 3-1 DSP56307 PBGA Signal Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name A1 Not Connected (NC), reserved B12 D8 D9 GND A2 SC11 or PD1 B13 D5 D10 GND A3 TMS B14 NC D11 GND A4 TDO C1 SC02 or PC2 D12 D1 A5 MODB/IRQB C2 STD1 or PD5 D13 D2 A6 D23 C3 TCK D14 V CCD A7 V CCD C4 MODA/IRQA E1 STD0 or PC5 A8 D19 C5 MODC/IRQC E2 V CCS A9 D16 C6 D22 E3 SRD0 or PC4 A10 D14 C7 V CCQL E4 GND A11 D11 C8 D18 E5 GND A12 D9 C9 V CCD E6 GND A13 D7 C10 D12 E7 GND A14 NC C11 V CCD E8 GND B1 SRD1 or PD4 C12 D6 E9 GND B2 SC12 or PD2 C13 D3 E10 GND B3 TDI C14 D4 E11 GND B4 TRST D1 PINIT/NMI E12 A17 B5 MODD/IRQD D2 SC01 or PC1 E13 A16 B6 D21 D3 DE E14 D0 B7 D20 D4 GND F1 RXD or PE0 B8 D17 D5 GND F2 SC10 or PD0 B9 D15 D6 GND F3 SC00 or PC0 B10 D13 D7 GND F4 GND B11 D10 D8 GND F5 GND

Pin-out and Package Information MOTOROLA DSP56307 Technical Data 3-5 F6 GND H3 SCK0 or PC3 J14 A9 F7 GND H4 GND K1 V CCS F8 GND H5 GND K2 HREQ /HREQ, HTRQ/HTRQ, or PB14 F9 GND H6 GND K3 TIO2 F10 GND H7 GND K4 GND F11 GND H8 GND K5 GND F12 V CCQH H9 GND K6 GND F13 A14 H10 GND K7 GND F14 A15 H11 GND K8 GND G1 SCK1 or PD3 H12 V CCA K9 GND G2 SCLK or PE2 H13 A10 K10 GND G3 TXD or PE1 H14 A11 K11 GND G4 GND J1 HACK /HACK, HRRQ/HRRQ, or PB15 K12 V CCA G5 GND J2 HRW, HRD /HRD, or PB11 K13 A5 G6 GND J3 HDS /HDS, HWR/HWR, or PB12 K14 A6 G7 GND J4 GND L1 HCS /HCS, HA10, or PB13 G8 GND J5 GND L2 TIO1 G9 GND J6 GND L3 TIO0 G10 GND J7 GND L4 GND G11 GND J8 GND L5 GND G12 A13 J9 GND L6 GND G13 V CCQL J10 GND L7 GND G14 A12 J11 GND L8 GND H1 V CCQH J12 A8 L9 GND H2 V CCQL J13 A7 L10 GND Table 3-1 DSP56307 PBGA Signal Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

3-6 DSP56307 Technical Data MOTOROLA Packaging Pin-out and Package Information L11 GND M13 A1 P1 NC L12 V CCA M14 A2 P2 H5, HAD5, or PB5 L13 A3 N1 H6, HAD6, or PB6 P3 H3, HAD3, or PB3 L14 A4 N2 H7, HAD7, or PB7 P4 H1, HAD1, or PB1 M1 HA1, HA8, or PB9 N3 H4, HAD4, or PB4 P5 PCAP M2 HA2, HA9, or PB10 N4 H2, HAD2, or PB2 P6 GND M3 HA0, HAS /HAS, or PB8 N5 RESET P7 AA2/RAS2 M4 V CCH N6 GND P P8 XTAL M5 H0, HAD0, or PB0 N7 AA3/RAS3 P9 V CCC M6 V CCP N8 CAS P10 TA M7 V CCQH N9 V CCQL P11 BB M8 EXTAL N10 BCLK P12 AA1/RAS1 M9 CLKOUT N11 BR P13 BG M10 BCLK N12 V CCC P14 NC M11 WR N13 AA0/RAS0 M12 RD N14 A0 Note: Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted but act as interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some connections have two or more configurable functions; names assigned to these connections indicate the function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike the TQFP package, most of the GND pins are connected internally in the center of the connection array and act as heat sink for the chip. Therefore, except for GND P and GND that support the PLL, other GND signals do not support individual subsystems in the chip. Table 3-1 DSP56307 PBGA Signal Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

Pin-out and Package Information MOTOROLA DSP56307 Technical Data 3-7 Table 3-2 DSP56307 PBGA Signal Identification by Name Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. A0 N14 BG P13 D7 A13 A1 M13 BR N11 D8 B12 A10 H13 CAS N8 D9 A12 A11 H14 CLKOUT M9 DE D3 A12 G14 D0 E14 EXTAL M8 A13 G12 D1 D12 GND D4 A14 F13 D10 B11 GND D5 A15 F14 D11 A11 GND D6 A16 E13 D12 C10 GND D7 A17 E12 D13 B10 GND D8 A2 M14 D14 A10 GND D9 A3 L13 D15 B9 GND D10 A4 L14 D16 A9 GND D11 A5 K13 D17 B8 GND E4 A6 K14 D18 C8 GND E5 A7 J13 D19 A8 GND E6 A8 J12 D2 D13 GND E7 A9 J14 D20 B7 GND E8 AA0 N13 D21 B6 GND E9 AA1 P12 D22 C6 GND E10 AA2 P7 D23 A6 GND E11 AA3 N7 D3 C13 GND F4 BB P11 D4 C14 GND F5 BCLK M10 D5 B13 GND F6 BCLK N10 D6 C12 GND F7

3-8 DSP56307 Technical Data MOTOROLA Packaging Pin-out and Package Information GND F8 GND J9 H4 N3 GND F9 GND J10 H5 P2 GND F10 GND J11 H6 N1 GND F11 GND K4 H7 N2 GND G4 GND K5 HA0 M3 GND G5 GND K6 HA1 M1 GND G6 GND K7 HA10 L1 GND G7 GND K8 HA2 M2 GND G8 GND K9 HA8 M1 GND G9 GND K10 HA9 M2 GND G10 GND K11 HACK /HACK J1 GND G11 GND L4 HAD0 M5 GND H4 GND L5 HAD1 P4 GND H5 GND L6 HAD2 N4 GND H6 GND L7 HAD3 P3 GND H7 GND L8 HAD4 N3 GND H8 GND L9 HAD5 P2 GND H9 GND L10 HAD6 N1 GND H10 GND L11 HAD7 N2 GND H11 GND P N6 HAS /HAS M3 GND J4 GND P6 HCS /HCS L1 GND J5 H0 M5 HDS /HDS J3 GND J6 H1 P4 HRD /HRD J2 GND J7 H2 N4 HREQ /HREQ K2 GND J8 H3 P3 HRRQ /HRRQ J1 Table 3-2 DSP56307 PBGA Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.

Pin-out and Package Information MOTOROLA DSP56307 Technical Data 3-9 HRW J2 PB2 N4 RAS0 N13 HTRQ/HTRQ K2 PB3 P3 RAS1 P12 HWR/HWR J3 PB4 N3 RAS2 P7 IRQA C4 PB5 P2 RAS3 N7 IRQB A5 PB6 N1 RD M12 IRQC C5 PB7 N2 RESET N5 IRQD B5 PB8 M3 RXD F1 MODA C4 PB9 M1 SC00 F3 MODB A5 PC0 F3 SC01 D2 MODC C5 PC1 D2 SC02 C1 MODD B5 PC2 C1 SC10 F2 NC A1 PC3 H3 SC11 A2 NC A14 PC4 E3 SC12 B2 NC B14 PC5 E1 SCK0 H3 NC P1 PCAP P5 SCK1 G1 NC P14 PD0 F2 SCLK G2 NMI D1 PD1 A2 SRD0 E3 PB0 M5 PD2 B2 SRD1 B1 PB1 P4 PD3 G1 STD0 E1 PB10 M2 PD4 B1 STD1 C2 PB11 J2 PD5 C2 TA P10 PB12 J3 PE0 F1 TCK C3 PB13 L1 PE1 G3 TDI B3 PB14 K2 PE2 G2 TDO A4 PB15 J1 PINIT D1 TIO0 L3 Table 3-2 DSP56307 PBGA Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.

3-10 DSP56307 Technical Data MOTOROLA Packaging Pin-out and Package Information TIO1 L2 V CCC P9 V CCQH TIO2 K3 V CCD A7 V CCQL TMS A3 V CCD C9 V CCQL G13 TRST B4 V CCD C11 V CCQL TXD G3 V CCD D14 V CCQL V CCA H12 V CCH M4 V CCS V CCA K12 V CCP M6 V CCS VCCA L12 V CCQH F12 WR M11 VCCC N12 V CCQH H1 XTAL P8 Table 3-2 DSP56307 PBGA Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.

Pin-out and Package Information MOTOROLA DSP56307 Technical Data 3-11 Figure 3-3 DSP56307 Mechanical Information, 196-pin PBGA Package A BD EE2 4X 0.2 TOP VIEW

0.3 B AC

0.1 C e /2 BOTTOM VIEW 13X 196X b e/ 2 e A B C D E F G H J K L M N P C 0.35C 0.15 C SIDE VIEW A DIM MIN MAX MILLIMETERS A 1.91 A1 0.27 0.47 A2 0.28 0.44 A3 0.70 1.00 b 0.35 0.65 D 15.00 BSC D1 13.00 BSC D2 12.00 15.00 E 15.00 BSC E1 13.00 BSC E2 12.00 15.00 e 1.00 BSC NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE SOLDER BAL DIAMETER MEASURED PARALLEL T DATUM C. ISSUE B 1.25 123456789 1 0 1 1 1 2 1 3 1 4 R1 — 2.50 CASE 1128-01 DATE 11/22/96 4X R R1 2X R R1

3-12 DSP56307 Technical Data MOTOROLA Packaging Ordering Drawings ORDERING DRAWINGS Complete mechanical information on DSP56307 packaging is available by facsimile through Motorola's Mfax system. Call the following number to obtain information by facsimile: The Mfax automated system requests the following information: ¥ The receiving facsimile telephone number including area code or country code ¥ The callerÕs personal identification number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. ¥ The type of information requested: Ð Instructions for using the system Ð A literature order form Ð Specific part technical information or data sheets Ð Other information described by the system messages A total of three documents may be ordered per call. The DSP56307 196-pin PBGA package mechanical drawing is referenced as 1128-01. (602) 244-6609

MOTOROLA DSP56307 Technical Data 4-1 SECTION 4 DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimate of the chip junction temperature, T J , in C can be obtained from this equation: Equation 1: Where: T A = ambient temperature ûC R q JA = package junction-to-ambient thermal resistance ûC/W P D = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance, as in this equation: Equation 2: Where: R q JA = package junction-to-ambient thermal resistance ûC/W R q JC = package junction-to-case thermal resistance ûC/W R q CA = package case-to-ambient thermal resistance ûC/W R q JC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, R q CA . For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimates obtained from R q JA do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. TJ TA PD RqJA·()+= RqJA RqJC RqCA+=

SECTION 4-2 DSP56307 Technical Data MOTOROLA Design Considerations Thermal Design Considerations A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. ¥ To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. ¥ To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. ¥ If the temperature of the package case (T T ) is determined by a thermocouple, the thermal resistance is computed from the value obtained by the equation (T J - T T )/P D As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will yield an estimate of a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or Y JT , has been defined to be (T J - T T )/P D This value gives a better estimate of the junction temperature in natural convection when the surface temperature of the package is used. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

Electrical Design Considerations MOTOROLA DSP56307 Technical Data SECTION 4-3 ELECTRICAL DESIGN CONSIDERATIONS Use the following list of recommendations to insure correct DSP operation. ¥ Provide a low-impedance path from the board power supply to each V CC pin on the DSP and from the board ground to each GND pin. ¥ Use at least six 0.01Ð0.1 m F bypass capacitors positioned as close as possible to the four sides of the package to connect the V CC power source to GND. ¥ Insure that capacitor leads and associated printed circuit traces that connect to the chip V CC and GND pins are less than 0.5 inch per capacitor lead. ¥ Use at least a four-layer PCB with two inner layers for V CC and GND. ¥ Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA , IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended. ¥ Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V CC and GND circuits. ¥ All inputs must be terminated (i.e., not allowed to float) by CMOS levels except for the three pins with internal pull-up resistors (TRST, TMS, DE). ¥ Take special care to minimize noise levels on the V CCP , GND P , and GND pins. ¥ The following pins must be asserted after power-up: RESET and TRST. ¥ If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V CC

SECTION 4-4 DSP56307 Technical Data MOTOROLA Design Considerations Power Consumption Considerations ¥ RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before deassertion of RESET. POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by this formula: Equation 3: Where: C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle The maximum internal current (I CCI max) value reflects the typical possible switching of the internal buses on best-case operation conditionsÑnot necessarily a real application case. The typical internal current (I CCItyp ) value reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for applications that require very low current consumption: ¥ Set the EBD bit when you are not accessing external memory. ¥ Minimize external memory accesses, and use internal memory accesses. ¥ Minimize the number of pins that are switching. ¥ Minimize the capacitive load on the pins. ¥ Connect the unused inputs to pull-up or pull-down resistors. ¥ Disable unused peripherals. ¥ Disable unused pin activity (e.g., CLKOUT, XTAL). Example 1 Current Consumption For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33 MHz), the current consumption is expressed in this equation: Equation 4: I CVf ··= I5 0 1 0 12з 3.3· 33· 106· 5.48 mA==

MOTOROLA DSP56307 Technical Data SECTION 4-5 One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix APPENDIX A Power Consumption Benchmark . Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. Equation 5: Where : I typF2 = current at F2 I typF1 = current at F1 F2 = high frequency (any specified operating frequency) F1 = low frequency (any specified operating frequency lower than F2) Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. PLL PERFORMANCE ISSUES The following explanations should be considered as general observations on expected PLL behavior. There is no test that replicates these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. Phase Skew Performance The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a given capacitive load on CLKOUT over the entire process, temperature, and voltage ranges. As defined in Figure 2-2 on page SECTION 2-7 for input frequencies greater than

15 MHz and the MF

4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than

10 MHz, this skew is between

1.4 ns and +3.2 ns. I MIPS⁄ I MHz⁄ ItypF2 ItypF1Ð() F2 F1Ð()⁄==

SECTION 4-6 DSP56307 Technical Data MOTOROLA Design Considerations PLL Performance Issues Phase Jitter Performance The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than 2 ns. Frequency Jitter Performance The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2Ð3%. Input (EXTAL) Jitter Requirements The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.

MOTOROLA DSP56307 Technical Data 5-1 SECTION 5

ORDERING INFORMATION

Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Voltage Package Type Pin Count Frequency (MHz) Order Number DSP56307 2.5 V core Array (PBGA) 196 100 XC56307GC100C

SECTION 5-2 DSP56307 Technical Data MOTOROLA

MOTOROLA DSP56307 Technical Data A-1 APPENDIX A POWER CONSUMPTION BENCHMARK The following benchmark program evaluates DSP power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation. ;* * ;* CHECKS Typical Power Consumption * ;* * page 200,55,0,0,0 nolist I_VEC EQU $000000 ; Interrupt vectors for program debug only START EQU $8000 ; MAIN (external) program starting address INT_PROG EQU $100 ; INTERNAL program memory starting address INT_XDAT EQU $0 ; INTERNAL X-data memory starting address INT_YDAT EQU $0 ; INTERNAL Y-data memory starting address INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org P:START movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM) ; Default: 1 w.s (SRAM) movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; Load the program move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; Load the X-data

A-2 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark move #INT_XDAT,r0 move #XDAT_START,r1 do #(XDAT_END-XDAT_START),XLOAD_LOOP move p:(r1)+,x0 move x0,x:(r0)+ XLOAD_LOOP ; Load the Y-data move #INT_YDAT,r0 move #YDAT_START,r1 do #(YDAT_END-YDAT_START),YLOAD_LOOP move p:(r1)+,x0 move x0,y:(r0)+ YLOAD_LOOP jmp INT_PROG PROG_START move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 clr a clr b move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 bset #4,omr ; ebd sbr dor #60,_end mac x0,y0,a x:(r0)+,x1 y:(r4)+,y1 mac x1,y1,a x:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,a x:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end bra sbr nop nop nop nop PROG_END nop nop XDAT_START ; org x:0

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-3 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 dc $6C6657 dc $C2A544 dc $A3662D dc $A4E762 dc $84F0F3 dc $E6F1B0 dc $B3829 dc $8BF7AE dc $63A94F dc $EF78DC dc $242DE5 dc $A3E0BA dc $EBAB6B dc $8726C8 dc $CA361 dc $2F6E86 dc $A57347 dc $4BE774 dc $8F349D dc $A1ED12 dc $4BFCE3 dc $EA26E0 dc $CD7D99 dc $4BA85E dc $27A43F dc $A8B10C dc $D3A55 dc $25EC6A dc $2A255B dc $A5F1F8 dc $2426D1 dc $AE6536 dc $CBBC37 dc $6235A4 dc $37F0D dc $63BEC2 dc $A5E4D3 dc $8CE810 dc $3FF09 dc $60E50E dc $CFFB2F dc $40753C dc $8262C5

A-4 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark dc $CA641A dc $EB3B4B dc $2DA928 dc $AB6641 dc $28A7E6 dc $4E2127 dc $482FD4 dc $7257D dc $E53C72 dc $1A8C3 dc $E27540 XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc $24233D dc $802732 dc $2E3C83 dc $A43E00 dc $C2B639 dc $85A47E dc $ABFDDF dc $F3A2C dc $2D7CF5 dc $E16A8A dc $ECB8FB dc $4BED18 dc $43F371 dc $83A556 dc $E1E9D7 dc $ACA2C4 dc $8135AD dc $2CE0E2 dc $8F2C73 dc $432730 dc $A87FA9 dc $4A292E dc $A63CCF dc $6BA65C dc $E06D65 dc $1AA3A dc $A1B6EB dc $48AC48 dc $EF7AE1 dc $6E3006 dc $62F6C7

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-5 dc $6064F4 dc $87E41D dc $CB2692 dc $2C3863 dc $C6BC60 dc $43A519 dc $6139DE dc $ADF7BF dc $4B3E8C dc $6079D5 dc $E0F5EA dc $8230DB dc $A3B778 dc $2BFE51 dc $E0A6B6 dc $68FFB7 dc $28F324 dc $8F2E8D dc $667842 dc $83E053 dc $A1FD90 dc $6B2689 dc $85B68E dc $622EAF dc $6162BC dc $E4A245 YDAT_END ; EQUATES for DSP56307 I/O registers and ports ; Last update: June 11 1995 page 132,55,0,0,0 opt mex ioequ ident 1,0 ; EQUATES for I/O Port Programming ; Register Addresses M_HDR EQU $FFFFC9 ; Host port GPIO data Register M_HDDR EQU $FFFFC8 ; Host port GPIO direction Register M_PCRC EQU $FFFFBF ; Port C Control Register M_PRRC EQU $FFFFBE ; Port C Direction Register

A-6 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark M_PDRC EQU $FFFFBD ; Port C GPIO Data Register M_PCRD EQU $FFFFAF ; Port D Control register M_PRRD EQU $FFFFAE ; Port D Direction Data Register M_PDRD EQU $FFFFAD ; Port D GPIO Data Register M_PCRE EQU $FFFF9F ; Port E Control register M_PRRE EQU $FFFF9E ; Port E Direction Register M_PDRE EQU $FFFF9D ; Port E Data Register M_OGDB EQU $FFFFFC ; OnCE GDB Register ; EQUATES for Host Interface ; Register Addresses M_HCR EQU $FFFFC2 ; Host Control Register M_HSR EQU $FFFFC3 ; Host Status Rgister M_HPCR EQU $FFFFC4 ; Host Polarity Control Register M_HBAR EQU $FFFFC5 ; Host Base Address Register M_HRX EQU $FFFFC6 ; Host Receive Register M_HTX EQU $FFFFC7 ; Host Transmit Register ; HCR bits definition M_HRIE EQU $0 ; Host Receive interrupts Enable M_HTIE EQU $1 ; Host Transmit Interrupt Enable M_HCIE EQU $2 ; Host Command Interrupt Enable M_HF2 EQU $3 ; Host Flag 2 M_HF3 EQU $4 ; Host Flag 3 ; HSR bits definition M_HRDF EQU $0 ; Host Receive Data Full M_HTDE EQU $1 ; Host Receive Data Emptiy M_HCP EQU $2 ; Host Command Pending M_HF0 EQU $3 ; Host Flag 0 M_HF1 EQU $4 ; Host Flag 1 ; HPCR bits definition M_HGEN EQU $0 ; Host Port GPIO Enable M_HA8EN EQU $1 ; Host Address 8 Enable M_HA9EN EQU $2 ; Host Address 9 Enable M_HCSEN EQU $3 ; Host Chip Select Enable M_HREN EQU $4 ; Host Request Enable M_HAEN EQU $5 ; Host Acknowledge Enable M_HEN EQU $6 ; Host Enable M_HOD EQU $8 ; Host Request Open Drain mode M_HDSP EQU $9 ; Host Data Strobe Polarity M_HASP EQU $A ; Host Address Strobe Polarity M_HMUX EQU $B ; Host Multiplexed bus select M_HD_HS EQU $C ; Host Double/Single Strobe select

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-7 M_HCSP EQU $D ; Host Chip Select Polarity M_HRP EQU $E ; Host Request PolarityPolarity M_HAP EQU $F ; Host Acknowledge Polarity ; EQUATES for Serial Communications Interface (SCI) ; Register Addresses M_STXH EQU $FFFF97 ; SCI Transmit Data Register (high) M_STXM EQU $FFFF96 ; SCI Transmit Data Register (middle) M_STXL EQU $FFFF95 ; SCI Transmit Data Register (low) M_SRXH EQU $FFFF9A ; SCI Receive Data Register (high) M_SRXM EQU $FFFF99 ; SCI Receive Data Register (middle) M_SRXL EQU $FFFF98 ; SCI Receive Data Register (low) M_STXA EQU $FFFF94 ; SCI Transmit Address Register M_SCR EQU $FFFF9C ; SCI Control Register M_SSR EQU $FFFF93 ; SCI Status Register M_SCCR EQU $FFFF9B ; SCI Clock Control Register ; SCI Control Register Bit Flags M_WDS EQU $7 ; Word Select Mask (WDS0-WDS3) M_WDS0 EQU 0 ; Word Select 0 M_WDS1 EQU 1 ; Word Select 1 M_WDS2 EQU 2 ; Word Select 2 M_SSFTD EQU 3 ; SCI Shift Direction M_SBK EQU 4 ; Send Break M_WAKE EQU 5 ; Wakeup Mode Select M_RWU EQU 6 ; Receiver Wakeup Enable M_WOMS EQU 7 ; Wired-OR Mode Select M_SCRE EQU 8 ; SCI Receiver Enable M_SCTE EQU 9 ; SCI Transmitter Enable M_ILIE EQU 10 ; Idle Line Interrupt Enable M_SCRIE EQU 11 ; SCI Receive Interrupt Enable M_SCTIE EQU 12 ; SCI Transmit Interrupt Enable M_TMIE EQU 13 ; Timer Interrupt Enable M_TIR EQU 14 ; Timer Interrupt Rate M_SCKP EQU 15 ; SCI Clock Polarity M_REIE EQU 16 ; SCI Error Interrupt Enable (REIE) ; SCI Status Register Bit Flags M_TRNE EQU 0 ; Transmitter Empty M_TDRE EQU 1 ; Transmit Data Register Empty M_RDRF EQU 2 ; Receive Data Register Full M_IDLE EQU 3 ; Idle Line Flag M_OR EQU 4 ; Overrun Error Flag M_PE EQU 5 ; Parity Error

A-8 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark M_FE EQU 6 ; Framing Error Flag M_R8 EQU 7 ; Received Bit 8 (R8) Address ; SCI Clock Control Registe r M_CD EQU $FFF ; Clock Divider Mask (CD0-CD11) M_COD EQU 12 ; Clock Out Divider M_SCP EQU 13 ; Clock Prescaler M_RCM EQU 14 ; Receive Clock Mode Source Bit M_TCM EQU 15 ; Transmit Clock Source Bit ; EQUATES for Synchronous Serial Interface (SSI) ; Register Addresses Of SSI0 M_TX00 EQU $FFFFBC ; SSI0 Transmit Data Register 0 M_TX01 EQU $FFFFBB ; SSIO Transmit Data Register 1 M_TX02 EQU $FFFFBA ; SSIO Transmit Data Register 2 M_TSR0 EQU $FFFFB9 ; SSI0 Time Slot Register M_RX0 EQU $FFFFB8 ; SSI0 Receive Data Register M_SSISR0 EQU $FFFFB7 ; SSI0 Status Register M_CRB0 EQU $FFFFB6 ; SSI0 Control Register B M_CRA0 EQU $FFFFB5 ; SSI0 Control Register A M_TSMA0 EQU $FFFFB4 ; SSI0 Transmit Slot Mask Register A M_TSMB0 EQU $FFFFB3 ; SSI0 Transmit Slot Mask Register B M_RSMA0 EQU $FFFFB2 ; SSI0 Receive Slot Mask Register A M_RSMB0 EQU $FFFFB1 ; SSI0 Receive Slot Mask Register B ; Register Addresses Of SSI1 M_TX10 EQU $FFFFAC ; SSI1 Transmit Data Register 0 M_TX11 EQU $FFFFAB ; SSI1 Transmit Data Register 1 M_TX12 EQU $FFFFAA ; SSI1 Transmit Data Register 2 M_TSR1 EQU $FFFFA9 ; SSI1 Time Slot Register M_RX1 EQU $FFFFA8 ; SSI1 Receive Data Register M_SSISR1 EQU $FFFFA7 ; SSI1 Status Register M_CRB1 EQU $FFFFA6 ; SSI1 Control Register B M_CRA1 EQU $FFFFA5 ; SSI1 Control Register A M_TSMA1 EQU $FFFFA4 ; SSI1 Transmit Slot Mask Register A M_TSMB1 EQU $FFFFA3 ; SSI1 Transmit Slot Mask Register B M_RSMA1 EQU $FFFFA2 ; SSI1 Receive Slot Mask Register A M_RSMB1 EQU $FFFFA1 ; SSI1 Receive Slot Mask Register B ; SSI Control Register A Bit Flags M_PM EQU $FF ; Prescale Modulus Select Mask (PM0-PM7) M_PSR EQU 11 ; Prescaler Range M_DC EQU $1F000 ; Frame Rate Divider Control Mask (DC0-DC7) M_ALC EQU 18 ; Alignment Control (ALC)

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-9 M_WL EQU $380000 ; Word Length Control Mask (WL0-WL7) M_SSC1 EQU 22 ; Select SC1 as TR #0 drive enable (SSC1) ; SSI Control Register B Bit Flags M_OF EQU $3 ; Serial Output Flag Mask M_OF0 EQU 0 ; Serial Output Flag 0 M_OF1 EQU 1 ; Serial Output Flag 1 M_SCD EQU $1C ; Serial Control Direction Mask M_SCD0 EQU 2 ; Serial Control 0 Direction M_SCD1 EQU 3 ; Serial Control 1 Direction M_SCD2 EQU 4 ; Serial Control 2 Direction M_SCKD EQU 5 ; Clock Source Direction M_SHFD EQU 6 ; Shift Direction M_FSL EQU $180 ; Frame Sync Length Mask (FSL0-FSL1) M_FSL0 EQU 7 ; Frame Sync Length 0 M_FSL1 EQU 8 ; Frame Sync Length 1 M_FSR EQU 9 ; Frame Sync Relative Timing M_FSP EQU 10 ; Frame Sync Polarity M_CKP EQU 11 ; Clock Polarity M_SYN EQU 12 ; Sync/Async Control M_MOD EQU 13 ; SSI Mode Select M_SSTE EQU $1C000 ; SSI Transmit enable Mask M_SSTE2 EQU 14 ; SSI Transmit #2 Enable M_SSTE1 EQU 15 ; SSI Transmit #1 Enable M_SSTE0 EQU 16 ; SSI Transmit #0 Enable M_SSRE EQU 17 ; SSI Receive Enable M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable M_SSRIE EQU 19 ; SSI Receive Interrupt Enable M_STLIE EQU 20 ; SSI Transmit Last Slot Interrupt Enable M_SRLIE EQU 21 ; SSI Receive Last Slot Interrupt Enable M_STEIE EQU 22 ; SSI Transmit Error Interrupt Enable M_SREIE EQU 23 ; SI Receive Error Interrupt Enable ; SSI Status Register Bit Flags M_IF EQU $3 ; Serial Input Flag Mask M_IF0 EQU 0 ; Serial Input Flag 0 M_IF1 EQU 1 ; Serial Input Flag 1 M_TFS EQU 2 ; Transmit Frame Sync Flag M_RFS EQU 3 ; Receive Frame Sync Flag M_TUE EQU 4 ; Transmitter Underrun Error FLag M_ROE EQU 5 ; Receiver Overrun Error Flag M_TDE EQU 6 ; Transmit Data Register Empty M_RDF EQU 7 ; Receive Data Register Full ; SSI Transmit Slot Mask Register A M_SSTSA EQU $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15) ; SSI Transmit Slot Mask Register B M_SSTSB EQU $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31)

A-10 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark ; SSI Receive Slot Mask Register A M_SSRSA EQU $FFFF ; SSI Receive Slot Bits Mask A (RS0-RS15) ; SSI Receive Slot Mask Register B M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31) ; EQUATES for Exception Processing ; Register Addresses M_IPRC EQU $FFFFFF ; Interrupt Priority Register Core M_IPRP EQU $FFFFFE ; Interrupt Priority Register Peripheral ; Interrupt Priority Register Core (IPRC) M_IAL EQU $7 ; IRQA Mode Mask M_IAL0 EQU 0 ; IRQA Mode Interrupt Priority Level (low) M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high) M_IAL2 EQU 2 ; IRQA Mode Trigger Mode M_IBL EQU $38 ; IRQB Mode Mask M_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low) M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high) M_IBL2 EQU 5 ; IRQB Mode Trigger Mode M_ICL EQU $1C0 ; IRQC Mode Mask M_ICL0 EQU 6 ; IRQC Mode Interrupt Priority Level (low) M_ICL1 EQU 7 ; IRQC Mode Interrupt Priority Level (high) M_ICL2 EQU 8 ; IRQC Mode Trigger Mode M_IDL EQU $E00 ; IRQD Mode Mask M_IDL0 EQU 9 ; IRQD Mode Interrupt Priority Level (low) M_IDL1 EQU 10 ; IRQD Mode Interrupt Priority Level (high) M_IDL2 EQU 11 ; IRQD Mode Trigger Mode M_D0L EQU $3000 ; DMA0 Interrupt priority Level Mask M_D0L0 EQU 12 ; DMA0 Interrupt Priority Level (low) M_D0L1 EQU 13 ; DMA0 Interrupt Priority Level (high) M_D1L EQU $C000 ; DMA1 Interrupt Priority Level Mask M_D1L0 EQU 14 ; DMA1 Interrupt Priority Level (low) M_D1L1 EQU 15 ; DMA1 Interrupt Priority Level (high) M_D2L EQU $30000 ; DMA2 Interrupt priority Level Mask M_D2L0 EQU 16 ; DMA2 Interrupt Priority Level (low) M_D2L1 EQU 17 ; DMA2 Interrupt Priority Level (high) M_D3L EQU $C0000 ; DMA3 Interrupt Priority Level Mask M_D3L0 EQU 18 ; DMA3 Interrupt Priority Level (low) M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high)

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-11 M_D4L EQU $300000 ; DMA4 Interrupt priority Level Mask M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low) M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high) M_D5L EQU $C00000 ; DMA5 Interrupt priority Level Mask M_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low) M_D5L1 EQU 23 ; DMA5 Interrupt Priority Level (high) ; Interrupt Priority Register Peripheral (IPRP) M_HPL EQU $3 ; Host Interrupt Priority Level Mask M_HPL0 EQU 0 ; Host Interrupt Priority Level (low) M_HPL1 EQU 1 ; Host Interrupt Priority Level (high) M_S0L EQU $C ; SSI0 Interrupt Priority Level Mask M_S0L0 EQU 2 ; SSI0 Interrupt Priority Level (low) M_S0L1 EQU 3 ; SSI0 Interrupt Priority Level (high) M_S1L EQU $30 ; SSI1 Interrupt Priority Level Mask M_S1L0 EQU 4 ; SSI1 Interrupt Priority Level (low) M_S1L1 EQU 5 ; SSI1 Interrupt Priority Level (high) M_SCL EQU $C0 ; SCI Interrupt Priority Level Mask M_SCL0 EQU 6 ; SCI Interrupt Priority Level (low) M_SCL1 EQU 7 ; SCI Interrupt Priority Level (high) M_T0L EQU $300 ; TIMER Interrupt Priority Level Mask M_T0L0 EQU 8 ; TIMER Interrupt Priority Level (low) M_T0L1 EQU 9 ; TIMER Interrupt Priority Level (high) ; EQUATES for TIMER ; Register Addresses Of TIMER0 M_TCSR0 EQU $FFFF8F ; Timer 0 Control/Status Register M_TLR0 EQU $FFFF8E ; TIMER0 Load Reg M_TCPR0 EQU $FFFF8D ; TIMER0 Compare Register M_TCR0 EQU $FFFF8C ; TIMER0 Count Register ; Register Addresses Of TIMER1 M_TCSR1 EQU $FFFF8B ; TIMER1 Control/Status Register M_TLR1 EQU $FFFF8A ; TIMER1 Load Reg M_TCPR1 EQU $FFFF89 ; TIMER1 Compare Register M_TCR1 EQU $FFFF88 ; TIMER1 Count Register ; Register Addresses Of TIMER2 M_TCSR2 EQU $FFFF87 ; TIMER2 Control/Status Register M_TLR2 EQU $FFFF86 ; TIMER2 Load Reg M_TCPR2 EQU $FFFF85 ; TIMER2 Compare Register

A-12 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark M_TCR2 EQU $FFFF84 ; TIMER2 Count Register M_TPLR EQU $FFFF83 ; TIMER Prescaler Load Register M_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register ; Timer Control/Status Register Bit Flags M_TE EQU 0 ; Timer Enable M_TOIE EQU 1 ; Timer Overflow Interrupt Enable M_TCIE EQU 2 ; Timer Compare Interrupt Enable M_TC EQU $F0 ; Timer Control Mask (TC0-TC3) M_INV EQU 8 ; Inverter Bit M_TRM EQU 9 ; Timer Restart Mode M_DIR EQU 11 ; Direction Bit M_DI EQU 12 ; Data Input M_DO EQU 13 ; Data Output M_PCE EQU 15 ; Prescaled Clock Enable M_TOF EQU 20 ; Timer Overflow Flag M_TCF EQU 21 ; Timer Compare Flag ; Timer Prescaler Register Bit Flags M_PS EQU $600000 ; Prescaler Source Mask M_PS0 EQU 21 M_PS1 EQU 22 ; Timer Control Bits M_TC0 EQU 4 ; Timer Control 0 M_TC1 EQU 5 ; Timer Control 1 M_TC2 EQU 6 ; Timer Control 2 M_TC3 EQU 7 ; Timer Control 3 ; EQUATES for Direct Memory Access (DMA) ; Register Addresses Of DMA M_DSTR EQU FFFFF4 ; DMA Status Register M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0 M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1 M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2 M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3 ; Register Addresses Of DMA0 M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register M_DCO0 EQU $FFFFED ; DMA0 Counter M_DCR0 EQU $FFFFEC ; DMA0 Control Register

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-13 ; Register Addresses Of DMA1 M_DSR1 EQU $FFFFEB ; DMA1 Source Address Register M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register M_DCO1 EQU $FFFFE9 ; DMA1 Counter M_DCR1 EQU $FFFFE8 ; DMA1 Control Register ; Register Addresses Of DMA2 M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5 ; DMA2 Counter M_DCR2 EQU $FFFFE4 ; DMA2 Control Register ; Register Addresses Of DMA4 M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register M_DCO3 EQU $FFFFE1 ; DMA3 Counter M_DCR3 EQU $FFFFE0 ; DMA3 Control Register ; Register Addresses Of DMA4 M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register M_DCO4 EQU $FFFFDD ; DMA4 Counter M_DCR4 EQU $FFFFDC ; DMA4 Control Register ; Register Addresses Of DMA5 M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register M_DCO5 EQU $FFFFD9 ; DMA5 Counter M_DCR5 EQU $FFFFD8 ; DMA5 Control Register ; DMA Control Register M_DSS EQU $3 ; DMA Source Space Mask (DSS0-Dss1) M_DSS0 EQU 0 ; DMA Source Memory space 0 M_DSS1 EQU 1 ; DMA Source Memory space 1 M_DDS EQU $C ; DMA Destination Space Mask (DDS-DDS1) M_DDS0 EQU 2 ; DMA Destination Memory Space 0 M_DDS1 EQU 3 ; DMA Destination Memory Space 1 M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0) M_DAM0 EQU 4 ; DMA Address Mode 0 M_DAM1 EQU 5 ; DMA Address Mode 1 M_DAM2 EQU 6 ; DMA Address Mode 2 M_DAM3 EQU 7 ; DMA Address Mode 3 M_DAM4 EQU 8 ; DMA Address Mode 4 M_DAM5 EQU 9 ; DMA Address Mode 5 M_D3D EQU 10 ; DMA Three Dimensional Mode

A-14 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark M_DRS EQU $F800 ; DMA Request Source Mask (DRS0-DRS4) M_DCON EQU 16 ; DMA Continuous Mode M_DPR EQU $60000 ; DMA Channel Priority M_DPR0 EQU 17 ; DMA Channel Priority Level (low) M_DPR1 EQU 18 ; DMA Channel Priority Level (high) M_DTM EQU $380000 ; DMA Transfer Mode Mask (DTM2-DTM0) M_DTM0 EQU 19 ; DMA Transfer Mode 0 M_DTM1 EQU 20 ; DMA Transfer Mode 1 M_DTM2 EQU 21 ; DMA Transfer Mode 2 M_DIE EQU 22 ; DMA Interrupt Enable bit M_DE EQU 23 ; DMA Channel Enable bit ; DMA Status Register M_DTD EQU $3F ; Channel Transfer Done Status MASK (DTD0-DTD5) M_DTD0 EQU 0 ; DMA Channel Transfer Done Status 0 M_DTD1 EQU 1 ; DMA Channel Transfer Done Status 1 M_DTD2 EQU 2 ; DMA Channel Transfer Done Status 2 M_DTD3 EQU 3 ; DMA Channel Transfer Done Status 3 M_DTD4 EQU 4 ; DMA Channel Transfer Done Status 4 M_DTD5 EQU 5 ; DMA Channel Transfer Done Status 5 M_DACT EQU 8 ; DMA Active State M_DCH EQU $E00 ; DMA Active Channel Mask (DCH0-DCH2) M_DCH0 EQU 9 ; DMA Active Channel 0 M_DCH1 EQU 10 ; DMA Active Channel 1 M_DCH2 EQU 11 ; DMA Active Channel 2 ; EQUATES for Enhanced Filter Co-Processop (EFCOP) M_FDIR EQU $FFFFB0 ; EFCOP Data Input Register M_FDOR EQU $FFFFB1 ; EFCOP Data Output Register M_FKIR EQU $FFFFB2 ; EFCOP K-Constant Register M_FCNT EQU $FFFFB3 ; EFCOP Filter Counter M_FCSR EQU $FFFFB4 ; EFCOP Control Status Register M_FACR EQU $FFFFB5 ; EFCOP ALU Control Register M_FDBA EQU $FFFFB6 ; EFCOP Data Base Address M_FCBA EQU $FFFFB7 ; EFCOP Coefficient Base Address M_FDCH EQU $FFFFB8 ; EFCOP Decimation/Channel Register ; EQUATES for Phase Locked Loop (PLL) ; Register Addresses Of PLL

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-15 M_PCTL EQU $FFFFFD ; PLL Control Register ; PLL Control Register M_MF EQU $FFF : Multiplication Factor Bits Mask (MF0-MF11) M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2) M_XTLR EQU 15 ; XTAL Range select bit M_XTLD EQU 16 ; XTAL Disable Bit M_PSTP EQU 17 ; STOP Processing State Bit M_PEN EQU 18 ; PLL Enable Bit M_PCOD EQU 19 ; PLL Clock Output Disable Bit M_PD EQU $F00000 ; PreDivider Factor Bits Mask (PD0-PD3) ; EQUATES for BIU ; Register Addresses Of BIU M_BCR EQU $FFFFFB ; Bus Control Register M_DCR EQU $FFFFFA ; DRAM Control Register M_AAR0 EQU $FFFFF9 ; Address Attribute Register 0 M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1 M_AAR2 EQU $FFFFF7 ; Address Attribute Register 2 M_AAR3 EQU $FFFFF6 ; Address Attribute Register 3 M_IDR EQU $FFFFF5 ; ID Register ; Bus Control Register M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4) M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14) M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2) M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3) M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4) M_BBS EQU 21 ; Bus State M_BLH EQU 22 ; Bus Lock Hold M_BRH EQU 23 ; Bus Request Hold ; DRAM Control Register M_BCW EQU $3 ; In Page Wait States Bits Mask (BCW0-BCW1) M_BRW EQU $C ; Out Of Page Wait States Bits Mask (BRW0-BRW1) M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPLE EQU 11 ; Page Logic Enable M_BME EQU 12 ; Mastership Enable M_BRE EQU 13 ; Refresh Enable M_BSTR EQU 14 ; Software Triggered Refresh M_BRF EQU $7F8000 ; Refresh Rate Bits Mask (BRF0-BRF7)

A-16 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark M_BRP EQU 23 ; Refresh prescaler ; Address Attribute Registers M_BAT EQU $3 ; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1) M_BAAP EQU 2 ; Address Attribute Pin Polarity M_BPEN EQU 3 ; Program Space Enable M_BXEN EQU 4 ; X Data Space Enable M_BYEN EQU 5 ; Y Data Space Enable M_BAM EQU 6 ; Address Muxing M_BPAC EQU 7 ; Packing Enable M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3) M_BAC EQU $FFF000 ; Address to Compare Bits Mask (BAC0-BAC11) ; control and status bits in SR M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR M_CA EQU 0 ; Carry M_V EQU 1 ; Overflow M_Z EQU 2 ; Zero M_N EQU 3 ; Negative M_U EQU 4 ; Unnormalized M_E EQU 5 ; Extension M_L EQU 6 ; Limit M_S EQU 7 ; Scaling Bit M_I0 EQU 8 ; Interupt Mask Bit 0 M_I1 EQU 9 ; Interupt Mask Bit 1 M_S0 EQU 10 ; Scaling Mode Bit 0 M_S1 EQU 11 ; Scaling Mode Bit 1 M_SC EQU 13 ; Sixteen_Bit Compatibility M_DM EQU 14 ; Double Precision Multiply M_LF EQU 15 ; DO-Loop Flag M_FV EQU 16 ; DO-Forever Flag M_SA EQU 17 ; Sixteen-Bit Arithmetic M_CE EQU 19 ; Instruction Cache Enable M_SM EQU 20 ; Arithmetic Saturation M_RM EQU 21 ; Rounding Mode M_CP0 EQU 22 ; bit 0 of priority bits in SR M_CP1 EQU 23 ; bit 1 of priority bits in SR ; control and status bits in OMR M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR M_MA equ0 ; Operating Mode A M_MB equ1 ; Operating Mode B M_MC equ2 ; Operating Mode C M_MD equ3 ; Operating Mode D M_EBD EQU 4 ; External Bus Disable bit in OMR M_SD EQU 6 ; Stop Delay M_MS EQU 7 ; Memory Switch bit in OMR M_CDP0 EQU 8 ; bit 0 of priority bits in OMR M_CDP1 EQU 9 ; bit 1 of priority bits in OMR M_BEN EQU 10 ; Burst Enable

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-17 M_TAS EQU 11 ; TA Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_ATE EQU 15 ; Address Tracing Enable bit in OMR. M_XYS EQU 16 ; Stack Extension space select bit in OMR. M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR. M_EOV EQU 18 ; Extended stack OVerflow flag in OMR. M_WRP EQU 19 ; Extended WRaP flag in OMR. M_SEN EQU 20 ; Stack Extension Enable bit in OMR. ; EQUATES for DSP56307 interrupts ; Last update: June 11 1995 page 132,55,0,0,0 opt mex intequ ident 1,0 if @DEF(I_VEC) ;leave user definition as is. else I_VEC EQU $0 endif ; Non-Maskable interrupts I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ; Stack Error I_ILL EQU I_VEC+$04 ; Illegal Instruction I_DBG EQU I_VEC+$06 ; Debug Request I_TRAP EQU I_VEC+$08 ; Trap I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt ; Interrupt Request Pins I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 ; IRQC I_IRQD EQU I_VEC+$16 ; IRQD

A-18 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark ; DMA Interrupts I_DMA0 EQU I_VEC+$18 ; DMA Channel 0 I_DMA1 EQU I_VEC+$1A ; DMA Channel 1 I_DMA2 EQU I_VEC+$1C ; DMA Channel 2 I_DMA3 EQU I_VEC+$1E ; DMA Channel 3 I_DMA4 EQU I_VEC+$20 ; DMA Channel 4 I_DMA5 EQU I_VEC+$22 ; DMA Channel 5 ; Timer Interrupts I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare I_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow ; ESSI Interrupts I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data w/ exception Status I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data w/ exception Status I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data w/ exception Status I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data w/ exception Status I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot ; SCI Interrupts I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD EQU I_VEC+$54 ; SCI Transmit Data I_SCIIL EQU I_VEC+$56 ; SCI Idle Line I_SCITM EQU I_VEC+$58 ; SCI Timer ; HOST Interrupts I_HRDF EQU I_VEC+$60 ; Host Receive Data Full I_HTDE EQU I_VEC+$62 ; Host Transmit Data Empty I_HC EQU I_VEC+$64 ; Default Host Command ; EFCOP Filter Interrupts

Power Consumption Benchmark MOTOROLA DSP56307 Technical Data A-19 I_FDIIE EQU I_VEC+$68 ; EFilter input buffer empty I_FDOIE EQU I_VEC+$6A ; EFilter output buffer full ; INTERRUPT ENDING ADDRESS I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space

A-20 DSP56307 Technical Data MOTOROLA Power Consumption Benchmark NOTES:

MOTOROLA DSP56307 Technical Data I-1 INDEX A ABE bit in OMR 2-50 AC electrical characteristics 2-4 Access 2-47 address bus 1-1 Address Trace mode 2-50 address tracing mode iii address, electronic mail ii ALU iii

applications

v arbitration bus timings 2-50 Arithmetic Logic Unit iii Asynchronous Bus Arbitration mode 2-50 ATE bit in OMR 2-50 B benchmark test algorithm bootstrap programs see appendix of UserÕs Manual bootstrap ROM iii boundary scan (JTAG) timing diagram 2-72 bus acquisition timings 2-51 address 1-2 control 1-1 data 1-2 external address 1-6 external data 1-6 multiplexed 1-2 non-multiplexed 1-2 release timings 2-52, 2-53 C clock 1-1, 1-5 external 2-4 internal 2-4 operation 2-7

contents

crystal oscillator circuits 2-6 D Data Arithmetic Logic Unit iii data bus 1-1 data memory expansion iv DC electrical characteristics 2-3 DE signal 1-30 Debug Event signal (DE signal) 1-30 Debug mode entering 1-30 external indication 1-30 Debug support iii design considerations electrical 4-3 PLL 4-5, 4-6 power consumption 4-4 thermal 4-1 Direct Memory Access iii DMA iii document conventions ii documentation list vi Double Data Strobe 1-2 DRAM controller iv out of page read access 2-44 Wait states selection guide 2-32 write access 2-45 out of page and refresh timings

11 Wait states 2-38

15 Wait states 2-41

4 Wait states 2-32

8 Wait states 2-35

Wait states selection guide 2-21 write accesses 2-30 Page mode timings

1 Wait state 2-22

2 Wait states 2-24

3 Wait states 2-26

4 Wait states 2-28

description

UserÕs Manual vi E EFCOP iii interrupts

F I-2 DSP56307 Technical Data MOTOROLA electrical design considerations 4-3 Enhanced Synchronous Serial Interface 1-1 Enhanced Synchronous Serial Interface (ESSI) 20, 1-23 Enhanced Synchronous Serial Interfaces v equates see appendix of UserÕs Manual ESSI receiver timing 2-67 timings 2-63 transmitter timing 2-66 external address bus 1-6 external bus control 1-6, 1-8, 1-9 external bus synchronous timings 2-47 external clock operation 2-4 external data bus 1-6 external interrupt timing (negative edge-triggered) 2-15 external level-sensitive fast interrupt timing 2-15 external memory access (DMA Source) timing external memory expansion port 1-6 External Memory Interface 2-18 External Memory Interface (Port A) 2-18 F Filtering Coprocessor iii functional groups 1-2 functional signal groups 1-1 G General Purpose Input/Output v GPIO v, 1-2 Timers 1-2 GPIO timing 2-70 Ground 1-4 PLL 1-4 ground 1-1 H helpline electronic mail (email) address ii HI08 Host Port Control Register (HPCR) 1-14, 1- HI08 timing 2-54 Host Inteface 1-1 Host Interface v, 1-2, 1-14, 1-15, 1-17, 1-18, 1- Host Interface timing 2-54 Host Port Control Register (HPCR) 1-14, 1-15, 1- Host Request Double 1-2 Single 1-2 HPCR register 1-14, 1-15, 1-16, 1-17, 1-18, 1- HR 1-2 I information sources vi instruction cache iii internal clocks 2-4 internet address ii interrupt and mode control 1-1, 1-11 interrupt control 1-11 interrupt timing 2-10 external level-sensitive fast 2-15 external negative edge-triggered 2-15 synchronous from Wait state 2-16 interrupts EFCOP 20 see appendix of UserÕs Manual J Joint Test Action Group (JTAG) interface 1-28 JTAG iii JTAG reset timing diagram 2-73 JTAG timing 2-71 JTAG/OnCE Interface signals Debug Event signal (DE signal) 1-30 M maximum ratings 2-1, 2-2 Memory external interface 2-18 memory expansion port iii mode control 1-11 Mode select timing 2-10 multiplexed bus 1-2 multiplexed bus timings read 2-59 write 2-60 N non-multiplexed bus 1-2

O MOTOROLA DSP56307 Technical Data I-3 non-multiplexed bus timings read 2-57 write 2-58 O off-chip memory iii OnCE Debug request 2-73 module timing 2-73 OnCE module iii interface 1-28 OnCE/JTAG 1-2 OnCE/JTAG port 1-1 on-chip DRAM controller iv On-Chip Emulation module iii on-chip memory iii operating mode select timing 2-16 ordering information 5-1 P package PBGA description 3-2, 3-3, 3-4, 3-7, 3-11 PBGA ball grid drawing (bottom) 3-3 ball grid drawing (top) 3-2 ball list by name 3-7 ball list by number 3-4 mechanical drawing 3-11 PCU iii Phase Lock Loop iii, 2-9 PLL iii, 1-1, 1-5, 2-9 Characteristics 2-9 performance issues 4-5 PLL design considerations 4-5, 4-6 PLL performance issues 4-6 Port A 1-1, 1-6, 2-18 Port B 1-1, 1-2, 1-16 Port C 1-1, 1-2, 1-20 Port D 1-1, 1-2, 1-23 Port E 1-1 Power 1-2 power 1-1, 1-3 power consumption benchmark test 3 power consumption design considerations 4-4 power management v Program Control Unit iii program memory expansion iv program RAM iii R recovery from Stop state using IRQA 2-16, 2-17 RESET 1-11 reset bus signals 1-6, 1-7 clock signals 1-5 essi signals 1-20, 1-23 host interface signals 1-14 interrupt signals 1-11 JTAG signals 1-29 mode control 1-11 OnCE signals 1-29 phase lock loop signals 1-5 sci signals 1-26 timers 1-27 Reset timing 2-10, 2-14 reset timing synchronous 2-14 ROM, bootstrap iii S SCI v, 1-2, 1-25 Asynchronous mode timing 2-62 Synchronous mode timing 2-62 timing 2-61 Serial Communication Interface 1-25 Serial Communications Interface v Serial Communications Interface (SCI) 1-1 signal groupings 1-1 signals 1-1 functional grouping 1-2 Single Data Strobe 1-2 SRAM read access 2-20 read and write accesses 2-18 support iv write access 2-20 Stop mode v Stop state recovery from 2-16, 2-17 Stop timing 2-10 supply voltage 2-2 Switch mode iii synchronous bus timings

1 WS (BCR controlled) 2-48

synchronous interrupt from Wait state timing 2- synchronous reset timing 2-14

T I-4 DSP56307 Technical Data MOTOROLA T table of contents ii TAP iii target applications v technical assistance ii Test Access Port iii Test Access Port timing diagram 2-72 Test Clock (TCLK) input timing diagram 2-71 thermal characteristics 2-2 thermal design considerations 4-1 Timer event input restrictions 2-68 interrupt generation 2-68 timing 2-68 Timers 1-1, 1-2, 1-27 timing Asynchronous Bus Arbitration mode 2-50 BSR 2-72 bus acquisition 2-51 bus arbitration 2-50 bus release 2-52, 2-53 DMA external source 2-17 DRAM access 2-22, 2-24, 2-26, 2-28, 2-30, 45, 2-46 ESSI 2-63, 2-66, 2-67 GPIO 2-70 Host Interface 2-54 interrupt 2-10, 2-15, 2-16 JTAG 2-71 JTAG reset 2-73 mode select 2-10 multiplexed bus 2-59, 2-60 non-multiplexed bus 2-57, 2-58 OnCE module 2-73 operating mode select 2-16 Reset 2-10 SCI 2-61 SCI Asynchronous mode 2-62 SCI Synchronous mode 2-62 SRAM read and write 2-18 Stop 2-10 Stop state recovery 2-16 synchronous external bus 2-47 synchronous reset 2-14 TAP 2-72 TCLK 2-71 Timer 2-68 W Wait mode v World Wide Web vi X X-data RAM iii Y Y-data RAM iii

Order Number: DSP56307/D Revision 0, 8/10/98

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