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DSP56362 MOTOROLA | Alldatasheet

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This document contains information on a new product. Specifications and information herein are subject to change without notice. IMOTOROLA DSP56362 Advance Information Motorola designed the DSP56362 to support digital audio applications requiring digital audio compression and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56362 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Motorola Symphony™ DSP family, as shown in Figure 1. This design provides a two-fold performance increase over Motorola’s popular Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. Figure 1 DSP56362 Block Diagram PLL OnCE Clock Generator Internal Data Bus Switch YAB XAB PAB YDB XDB PDB GDB MODB/IRQB MODC/IRQC External Data Bus Switch MODD/IRQD DSP56300 1216 24-Bit DDB DAB Peripheral Core YM_EB XM_EB PM_EB PIO_EB Expansion Area SHI JTAG RESET MODA/IRQA PINIT/NMI EXTAL Address Control Data Triple Timer Host Interface ESAI Address Generation Unit Six Channel DMA Unit Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 × 24 + 56 → 56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter Power Mngmnt. DRAM/SRAM Bus Interface I - Cache Control External Address Bus Switch AA0456G Memory Expansion Area Program RAM/ Instruction Cache 3072 × 24 Program ROM 30K × 24 Bootstrap ROM 192 × 24 X Data RAM 5632 × 24 ROM 6144 × 24 Y Data RAM 5632 × 24 ROM 6144 × 24 CLKOUT DAX (SPDIF) Technical Data DSP56362/D Rev. 3, 02/2004 24-Bit Audio Digital Signal Processor Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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!! DSP56362 Advance Information MOTOROLA FOR TECHNICAL ASSISTANCE: Telephone: 1-800-521-6274 Email: dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) “asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low “deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage * PIN True Asserted V IL/VOL PIN False Deasserted V IH/VOH PIN True Asserted V IH/VOH PIN False Deasserted V IL/VOL Note: *Values for V IL, VOL, VIH, and VOH are defined by individual product specifications. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 1 OVERVIEW

FEATURES

• Multimode, multichannel decoder software functionality – Dolby Digital and Pro Logic – MPEG2 5.1 –D T S – Bass management
• Digital audio post-processing capabilities – 3D Virtual surround sound – Lucasfilm THX5.1 – Soundfield processing – Equalization
• Digital Signal Processing Core – 100 MIPS with a 100 MHz clock at 3.3 V +/- 5% – Object code compatible with the DSP56000 core – Highly parallel instruction set – Data arithmetic logic unit (ALU)
• Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)
• 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)
• Conditional ALU instructions
• 24-bit or 16-bit arithmetic support under software control – Program control unit (PCU)
• Position independent code (PIC) support
• Addressing modes optimized for DSP applications (including immediate offsets)
• On-chip instruction cache controller
• On-chip memory-expandable hardware stack
• Nested hardware DO loops
• Fast auto-return interrupts – Direct memory access (DMA)
• Six DMA channels supporting internal and external accesses
• One-, two-, and three- dimensional transfers (including circular buffering) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2 DSP56362 Advance Information MOTOROLA

• End-of-block-transfer interrupts
• Triggering from interrupt lines and all peripherals – Phase-locked loop (PLL)
• Software programmable PLL-based frequency synthesizer for the core clock
• Allows change of low-power divide factor (DF) without loss of lock
• Output clock with skew elimination – Hardware debugging support
• On-Chip Emulation (OnCE‘) module
• Joint Action Test Group (JTAG) test access port (TAP)
• Address trace mode reflects internal program RAM accesses at the external port
• On-Chip Memories – Modified Harvard architecture allows simultaneous access to program and data memories – 30720 x 24-bit on-chip program ROM 1 (disabled in 16-bit compatibility mode) – 6144 x 24-bit on-chip X-data ROM 1 – 6144 x 24-bit on-chip Y-data ROM 1 – Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable – 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)
• Off-Chip Memory Expansion – Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM. – Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM. – External memory expansion port( twenty-four data pins for high speed external memory access allowing for a large number of external accesses per sample) – Chip select logic for glueless interface to SRAMs – On-chip DRAM controller for glueless interface to DRAMs
• Peripheral and Support Circuits – Enhanced serial audio interface (ESAI) includes:
• Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.
• Master or slave capability
• I 2S, Sony, AC97, and other audio protocol implementations 1.These ROMs may be factory programmed with data or programs provided by the application developer. Instruction Cache Switch Mode Program RAM Size Instruction Cache Size X Data RAM Size Y Data RAM Size Disabled Disabled 3072 × 24-bit 0 5632 × 24-bit 5632 × 24-bit Enabled Disabled 2048 × 24-bit 1024 × 24-bit 5632 × 24-bit 5632 × 24-bit Disabled Enabled 5120 × 24-bit 0 5632 × 24-bit 3584 × 24-bit Enabled Enabled 4096 × 24-bit 1024 × 24-bit 5632 × 24-bit 3584 × 24-bit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 3 – Serial host interface (SHI) features:

• SPI protocol with multi-master capability
• I 2C protocol with single-master capability
• Ten-word receive FIFO
• Support for 8-, 16-, and 24-bit words. – Byte-wide parallel host interface (HDI08) with DMA support – DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340, and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines – Triple timer module with single external interface or GPIO line – On-chip peripheral registers are memory mapped in data memory space
• Reduced Power Dissipation – Very low-power (3.3 V) CMOS design – Wait and stop low-power standby modes – Fully-static logic, operation frequency down to 0 Hz (dc) – Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) Package
• 144-pin plastic thin quad flat pack (LQFP) surface-mount package DOCUMENTATION Table 1 lists the documents that provide a complete description of the DSP56362 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 1 DSP56362 Documentation Document Name Description Order Number DSP56300 Family Manual Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set DSP56300FM/AD DSP56362 User’s Manual Detailed description of memory, peripherals, and interfaces DSP56362UM/AD DSP56362 Advance Information Electrical and timing specifications; pin and package descriptions DSP56362/D There is also a product brief for this chip. DSP56362 Product Brief Brief description of the chip DSP56362P/D Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 1-1 SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The input and output signals of the DSP56362 are organized into functional groups, which are listed in Table 1-1 and illustrated in Figure 1-1. The DSP56362 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 1-1 DSP56362 Functional Signal Groupings Functional Group Number of Signals Detailed

Description

Power (VCC) 20 Table 1-2 Ground (GND) 19 Table 1-3 Clock and PLL 4 Table 1-4 Address bus Port A1

18 Table 1-5

Interrupt and mode control 5 Table 1-8 HDI08 Port B2 16 Table 1-9 SHI 5 Table 1-10 ESAI Port C3 12 Table 1-11 Digital audio transmitter (DAX) Port D4 2 Table 1-12 Timer 1 Table 1-13 JTAG/OnCE Port 6 Table 1-14 Port A is the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. Port D signals are the GPIO port signals which are multiplexed with the DAX signals. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-2 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Signal Groupings Figure 1-1 Signals Identified by Functional Group DSP56362

18 External

(SHI) Timer 02 PLL JTAG/ OnCE Port Power Inputs: PLL External I/O Internal Logic Address Bus Data Bus Bus Control HDI08 SHI/ESAI/DAX/Timer A0–A17 D0–D23 AA0–AA3/ RAS0–RAS3 CAS RD WR TA BR BG BB TCK TDI TDO TMS TRST DE CLKOUT PCAP PINIT/NMI VCCP VCCQH VCCQL VCCA VCCD VCCC VCCH VCCS Digital Audio Transmitter (DAX)2 Grounds: PLL PLL Internal Logic Address Bus Data Bus Bus Control HDI08 SHI/ESAI/DAX/Timer GNDP GNDP1 GNDQ GNDA GNDD GNDC GNDH GNDS Interrupt/ Mode Control MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET Host Interface (HDI08) Port1 Non- Multiplexed Bus H0–H7 HA0 HA1 HA2 HCS/HCS Single DS HRW HDS/HDS Single HR HOREQ/HOREQ HACK/HACK ACI ADO TIO0 EXTAL Clock and Multiplexed Bus HAD0–HAD7 HAS/HAS HA8 HA9 HA10 Double DS HRD/HRD HWR/HWR Double HR HTRQ/HTRQ HRRQ/HRRQ Port B GPIO PB0–PB7 PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 Port D GPIO PD0 PD1 Port C GPIO PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 Timer GPIO TIO0 Port A Notes: 1. The HDI08 port supports a nonmultiplexed or a multiplexed bus, single or double data strobe (DS), and single or double host request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HDI08 signals can also be configured alternately as GPIO signals (PB0–PB15). Signals with dual designations (e.g., HAS /HAS) have configurable polarity. 2. The ESAI signals are multiplexed with the port C GPIO signals (PC0–PC11). The DAX signals are multiplexed with the Port D GPIO signals (PD0–PD1). The timer 0 signal can be configured alternately as the timer GPIO signal (TIO0). SPI Mode MOSI SS MISO SCK HREQ I2C Mode HA0 HA2 SDA SCL HREQ Enhanced Serial Audio Interface (ESAI)2 SCKR FSR HCKR SCKT FST HCKT SDO5/SDI0 SDO4/SDI1 SDO3/SDI2 SDO2/SDI3 SDO1 SDO0 AA0601 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Power MOTOROLA DSP56362 Advance Information 1-3 POWER Table 1-2 Power Inputs Power Name Description VCCP PLL Power—V CCP is VCC dedicated for PLL use. The voltage should be well- regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. VCCQL (4) Quiet Core (Low) Power— VCCQL is an isolated power for the core processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCQ inputs. VCCQH (3) Quiet External (High) Power—V CCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There are three VCCQH inputs. VCCA (3) Address Bus Power—V CCA is an isolated power for sections of the address bus I/ O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are three VCCA inputs. VCCD (4) Data Bus Power—V CCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCD inputs. VCCC (2) Bus Control Power—V CCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCC inputs. VCCH Host Power—V CCH is an isolated power for the HDI08 I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCH input. VCCS (2) SHI, ESAI, DAX, and Timer Power—V CCS is an isolated power for the SHI, ESAI, DAX, and Timer I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCS inputs. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-4 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Ground GROUND Table 1-3 Grounds Ground Name Description GNDP PLL Ground—GND P is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip package. There is one GNDP connection. GNDP1 PLL Ground 1—GND P1 is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. There is one GNDP1 connection. GNDQ (4) Quiet Ground—GND Q is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections. GNDA (4) Address Bus Ground—GND A is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. GNDD (4) Data Bus Ground—GND D is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDD connections. GNDC (2) Bus Control Ground—GND C is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDC connections. GNDH Host Ground—GND H is an isolated ground for the HDI08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDH connection. GNDS (2) SHI, ESAI, DAX, and Timer Ground—GND S is an isolated ground for the SHI, ESAI, DAX, and Timer I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDS connections. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Clock and PLL MOTOROLA DSP56362 Advance Information 1-5 CLOCK AND PLL EXTERNAL MEMORY EXPANSION PORT (PORT A) When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and tri- states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0 –AA3/RAS3, RD, WR, BB, CAS. Table 1-4 Clock and PLL Signals Signal Name Type State during Reset Signal Description EXTAL Input Input External Clock Input—An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. This input cannot tolerate 5V. CLKOUT Output Chip-driven Clock Output—CLKOUT provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. CLKOUT is not functional at frequencies of 100 MHz and above. PCAP Input Input PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. PINIT/ NMI Input Input PLL Initial/Non maskable Interrupt—During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET deassertion and during normal instruction processing, the PINIT/NMI Schmitt- trigger input is a negative-edge-triggered non maskable interrupt (NMI) request internally synchronized to CLKOUT. PINIT/NMI cannot tolerate 5 V. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-6 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions External Memory Expansion Port (Port A) External Address Bus External Data Bus External Bus Control Table 1-5 External Address Bus Signals Signal Name Type State during Reset Signal Description A0–A17 Output Tri-stated Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A17 do not change state when external memory spaces are not being accessed. Table 1-6 External Data Bus Signals Signal Name Type State during Reset Signal Description D0–D23 Input/Output Tri-stated Data Bus—When the DSP is the bus master, D0–D23 are active-high, bidirectional input/ outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0–D23 are tri-stated. Table 1-7 External Bus Control Signals Signal Name Type State during Reset Signal Description AA0–AA3/ RAS0– RAS3 Output Tri-stated Address Attribute or Row Address Strobe—When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are can be tri-stated outputs with programmable polarity. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 1-7 CAS Output Tri-stated Column Address Strobe—When the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the bus mastership enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. RD Output Tri-stated Read Enable—When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0–D23). Otherwise, RD is tri- stated. WR Output Tri-stated Write Enable—When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0–D23). Otherwise, the signals are tri-stated. TA Input Ignored Input Transfer Acknowledge—If the DSP56362 is the bus master and there is no external bus activity, or the DSP56362 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the bus control register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result. Table 1-7 External Bus Control Signals (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-8 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions External Memory Expansion Port (Port A) BR Output Output (deasserted) Bus Request—BR is an active-low output, never tri- stated. BR is asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56362 is a bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the DSP56362 is the bus master. (See the description of bus “parking” in the BB signal description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. BG Input Ignored Input Bus Grant—BG is an active-low input. BG is asserted by an external bus arbitration circuit when the DSP56362 becomes the next bus master. When BG is asserted, the DSP56362 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. The default mode of operation of this signal requires a setup and hold time referred to CLKOUT. But CLKOUT operation is not guaranteed from 100MHz and up, so the asynchronous bus arbitration must be used for clock frequencies 100MHz and above. The asynchronous bus arbitration is enabled by setting the ABE bit in the OMR register. Table 1-7 External Bus Control Signals (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 1-9 BB Input/ Output Input Bus Busy—BB is a bidirectional active-low input/output. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. This is called “bus parking” and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB is done by an “active pull-up” method (i.e., BB is driven high and then released and held high by an external pull-up resistor). The default mode of operation of this signal requires a setup and hold time referred to CLKOUT. But CLKOUT operation is not guaranteed from 100MHz and up, so the asynchronous bus arbitration must be used for clock frequencies 100MHz and above. The asynchronous bus arbitration is enabled by setting the ABE bit in the OMR register. BB requires an external pull-up resistor. Table 1-7 External Bus Control Signals (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-10 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Interrupt and Mode Control INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 1-8 Interrupt and Mode Control Signal Name Type State during Reset Signal Description MODA/IRQA Input Input Mode Select A/External Interrupt Request A— MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If IRQA is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQA to exit the wait state. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. This input is 5 V tolerant. MODB/IRQB Input Input Mode Select B/External Interrupt Request B— MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQB is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the wait state. This input is 5 V tolerant. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Interrupt and Mode Control MOTOROLA DSP56362 Advance Information 1-11 MODC/IRQC Input Input Mode Select C/External Interrupt Request C— MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state. This input is 5 V tolerant. MODD/IRQD Input Input Mode Select D/External Interrupt Request D— MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQD is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQD to exit the wait state. This input is 5 V tolerant. Table 1-8 Interrupt and Mode Control (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-12 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Host Interface (HDI08) HOST INTERFACE (HDI08) The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware. Host Port Configuration Signal functions associated with the HDI08 vary according to the interface operating mode as determined by the HDI08 port control register (HPCR). See 6.5.6 Host Port Control Register (HPCR) on page Section 6-13 for detailed descriptions of this register and (See Host Interface (HDI08) on page Section 6-1.) for descriptions of the other HDI08 configuration registers. RESET Input Input Reset— RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the reset state and the internal phase generator is reset. The Schmitt- trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in “lock- step.” When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input is 5 V tolerant. Table 1-8 Interrupt and Mode Control (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Host Interface (HDI08) MOTOROLA DSP56362 Advance Information 1-13 Table 1-9 Host Interface Signal Name Type State during Reset Signal Description H0–H7 HAD0– HAD7 PB0–PB7 Input/ output Input/ output Input, output, or disconnected GPIO disconnected Host Data— When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, these signals are lines 0–7 of the bidirectional, tri-state data bus. Host Address— When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0–7 of the address/data bidirectional, multiplexed, tri- state bus. Port B 0–7—When the HDI08 is configured as GPIO, these signals are individually programmable as input, output, or internally disconnected. The default state after reset for these signals is GPIO disconnected. This input is 5 V tolerant. HA0 HAS/ HAS PB8 Input Input Input, output, or disconnected GPIO disconnected Host Address Input 0—When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address Strobe— When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable, but is configured active-low (HAS) following reset. Port B 8—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-14 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Host Interface (HDI08) HA1 HA8 PB9 Input Input Input, output, or disconnected GPIO disconnected Host Address Input 1—When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address 8—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus. Port B 9—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. HA2 HA9 PB10 Input Input Input, Output, or Disconnected GPIO disconnected Host Address Input 2—When the HDI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. Host Address 9—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. Port B 10—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Table 1-9 Host Interface (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Host Interface (HDI08) MOTOROLA DSP56362 Advance Information 1-15 HRW HRD/ HRD PB11 Input Input Input, Output, or Disconnected GPIO disconnected Host Read/Write—When HDI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. Host Read Data—When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host read data strobe (HRD) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD) after reset. Port B 11—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. HDS/ HDS HWR/ HWR PB12 Input Input Input, output, or disconnected GPIO disconnected Host Data Strobe— When HDI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS) following reset. Host Write Data—When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR) following reset. Port B 12—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Table 1-9 Host Interface (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-16 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Host Interface (HDI08) HCS HA10 PB13 Input Input Input, output, or disconnected GPIO disconnected Host Chip Select— When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. Host Address 10—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. Port B 13—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. HOREQ/ HOREQ HTRQ/ HTRQ PB14 Output Output Input, output, or disconnected GPIO disconnected Host Request—When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host request (HOREQ) output. The polarity of the host request is programmable, but is configured as active-low (HOREQ) following reset. The host request may be programmed as a driven or open-drain output. Transmit Host Request— When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. Port B 14—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Table 1-9 Host Interface (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Host Interface (HDI08) MOTOROLA DSP56362 Advance Information 1-17 HACK/ HACK HRRQ/ HRRQ PB15 Input Output Input, output, or disconnected GPIO disconnected Host Acknowledge—When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt- trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset. Receive Host Request—When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. Port B 15—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 5 V tolerant. Table 1-9 Host Interface (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-18 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Serial Host Interface SERIAL HOST INTERFACE The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I 2C mode. Table 1-10 Serial Host Interface Signals Signal Name Signal Type State during Reset Signal Description SCK SCL Input or output Input or output Tri-stated SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock—SCL carries the clock for I 2C bus transactions in the I2C mode. SCL is a Schmitt- trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Serial Host Interface MOTOROLA DSP56362 Advance Information 1-19 MISO SDA Input or output Input or open-drain output Tri-stated SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge—In I 2C mode, SDA is a Schmitt-trigger input when receiving and an open- drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. Table 1-10 Serial Host Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-20 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Serial Host Interface MOSI HA0 Input or output Input Tri-stated SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0—This signal uses a Schmitt- trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SS HA2 Input Input Tri-stated SPI Slave Select—This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. I2C Slave Address 2—This signal uses a Schmitt- trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. Table 1-10 Serial Host Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Serial Host Interface MOTOROLA DSP56362 Advance Information 1-21 HREQ Input or Output Tri-stated Host Request—This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 5 V tolerant. Table 1-10 Serial Host Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-22 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Enhanced Serial Audio Interface ENHANCED SERIAL AUDIO INTERFACE Table 1-11 Enhanced Serial Audio Interface Signals Signal Name Signal Type State during Reset Signal Description HCKR PC2 Input or output Input, output, or disconnected GPIO disconnected High Frequency Clock for Receiver—When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high- frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C 2—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. HCKT PC5 Input or output Input, output, or disconnected GPIO disconnected High Frequency Clock for Transmitter—When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C 5—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Enhanced Serial Audio Interface MOTOROLA DSP56362 Advance Information 1-23 FSR PC1 Input or output Input, output, or disconnected GPIO disconnected Frame Sync for Receiver—This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port C 1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. FST PC4 Input or output Input, output, or disconnected GPIO disconnected Frame Sync for Transmitter—This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C 4—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Table 1-11 Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-24 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Enhanced Serial Audio Interface SCKR PC0 Input or output Input, output, or disconnected GPIO disconnected Receiver Serial Clock—SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port C 0—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SCKT PC3 Input or output Input, output, or disconnected GPIO disconnected Transmitter Serial Clock—This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C 3—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Table 1-11 Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Enhanced Serial Audio Interface MOTOROLA DSP56362 Advance Information 1-25 SDO5 SDI0 PC6 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 5—When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0—When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C 6—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO4 SDI1 PC7 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 4—When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1—When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C 7—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Table 1-11 Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-26 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Enhanced Serial Audio Interface SDO3 SDI2 PC8 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 3—When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2—When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. Port C 8—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO2 SDI3 PC9 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 2—When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register. Serial Data Input 3—When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. Port C 9—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO1 PC10 Output Input, output, or disconnected GPIO disconnected Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C 10—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Table 1-11 Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Enhanced Serial Audio Interface MOTOROLA DSP56362 Advance Information 1-27 SDO0 PC11 Output Input, output, or disconnected GPIO disconnected Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial transmit shift register. Port C 11—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Table 1-11 Enhanced Serial Audio Interface Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-28 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions Digital Audio Interface (DAX) DIGITAL AUDIO INTERFACE (DAX) Table 1-12 Digital Audio Interface (DAX) Signals Signal Name Type State During Reset Signal Description ACI PD0 Input Input, output, or disconnected Disconnecte d Audio Clock Input—This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 × Fs, 384 × Fs or 512 × Fs, respectively). Port D 0—When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. ADO PD1 Output Input, output, or disconnected Disconnecte d Digital Audio Data Output—This signal is an audio and non-audio output in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format. Port D 1—When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Signal/Connection Descriptions Timer MOTOROLA DSP56362 Advance Information 1-29 TIMER JTAG/OnCE INTERFACE Table 1-13 Timer Signal Signal Name Type State during Reset Signal Description TIO0 Input or Output Input Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/ status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected it to Vcc through a pull-up resistor in order to ensure a stable logic level at the input. This input is 5 V tolerant. Table 1-14 JTAG/OnCE™ Interface Signal Name Type State during Reset Signal Description TCK Input Input Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 5 V tolerant. TDI Input Input Test Data Input—TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. TDO Output Tri- stated Test Data Output—TDO is a test data serial output signal used for test instructions and data. TDO can be tri-stated and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1-30 DSP56362 Advance Information MOTOROLA Signal/Connection Descriptions JTAG/OnCE Interface TMS Input Input Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. TRST Input Input Test Reset—TRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. The use of TRST is not recommended for new designs. It is recommended to leave TRST disconnected. This input is 5 V tolerant. DE Input/ Output Input Debug Event—DE is an open-drain, bidirectional, active-low signal providing, as an input, a means of entering the debug mode of operation from an external command controller, and, as an output, a means of acknowledging that the chip has entered the debug mode. This signal, when asserted as an input, causes the DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters the debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor. This is not a standard part of the JTAG TAP controller. The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered the debug mode. All other interface with the OnCE module must occur through the JTAG port. The use of DE is not recommended for new designs. It is recommended to leave DE disconnected. This input is not 5 V tolerant. Table 1-14 JTAG/OnCE™ Interface (Continued) Signal Name Type State during Reset Signal Description Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 2-1 SECTION 2 SPECIFICATIONS INTRODUCTION The DSP56362 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56362 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications will be published after full characterization and device qualifications are complete. MAXIMUM RATINGS Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or V CC). The suggested value for a pullup or pulldown resistor is 10 kΩ. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-2 DSP56362 Advance Information MOTOROLA Specifications Thermal Characteristics THERMAL CHARACTERISTICS Table 2-1 Maximum Ratings Rating1 Symbol Value1, 2 Unit Supply Voltage VCC −0.3 to +4.0 V All input voltages excluding “5 V tolerant” inputs3 VIN GND −0.3 to VCC + 0.3 V All “5 V tolerant” input voltages3 VIN5 GND −0.3 to VCC + 3.95 V Current drain per pin excluding VCC and GND I1 0 m A Operating temperature range TJ −40 to +105 °C Storage temperature TSTG −55 to +125 °C Notes: 1. GND = 0 V, V CC = 3.3 V ± .16V, TJ = 0°C to +100°C, CL = 50 pF 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3. CAUTION: All “5 V Tolerant” input voltages must not be more than 3.95 V greater than the supply voltage; this restriction applies to “power on”, as well as during normal operation. In any case, the input voltages cannot be more than 5.75 V. “5 V Tolerant” inputs are inputs that tolerate 5 V. Table 2-2 Thermal Characteristics Characteristic Symbol LQFP Value Unit Junction-to-ambient thermal resistance1 RθJA or θJA 45.3 °C/W Junction-to-case thermal resistance2 RθJC or θJC 10.1 °C/W Thermal characterization parameter ΨJT 5.5 °C/W Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single- sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111.) Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. 2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 2-3 DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics6 Characteristics Symbol Min Typ Max Unit Supply voltage VCC 3.14 3.3 3.46 V Input high voltage V

• D(0:23), BG , BB, TA, DE, and PINIT/ NMI VIH 2.0 — V CC
• M O D1/IRQ1, RESET, and TCK/TDI/ TMS/TRST/ESAI/Timer/HDI08/ SHI(SPI mode) pins VIHP 2.0 — V CC + 3.95
• S H I(I2C mode) pins 1.5 V CC + 3.95
• EXTAL 8 VIHX 0.8 ξ VCC —V CC Input low voltage V
• D(0:23), BG , BB, TA, MOD1/IRQ1, RESET, PINIT/NMI VIL –0.3 — 0.8
• All JTAG/ESAI/Timer/HDI08/ SHI (SPI mode) pins VILP –0.3 — 0.8
• S H I(I2C mode) pins –0.3 — 0.3 × VCC
• EXTAL 8 VILX –0.3 0.2 ξ VCC Input leakage current IIN –10 — 10 µA High impedance (off-state) input current (@ 2.4 V / 0.4 V) ITSI –10 — 10 µA Output high voltage
• TTL (I OH = –0.4 mA)5,7 VOH 2.4 — V
• C M O S ( IOH = –10 µιχροA)5 VCC – 0.01 — — Output low voltage
• TTL (I OL = 3.0 mA, open-drain pins IOL = 6.7 mA)5,7 VOL —— 0.4 V
• C M O S ( IOL = 10 µιχροA)5 0.01 Internal supply current2: (Operating frequency 100MHz for current measurements)
• In Normal mode I CCI — 127 181 mA
• In Wait mode I CCW —7 . 5 1 1 m A Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-4 DSP56362 Advance Information MOTOROLA Specifications AC ELECTRICAL CHARACTERISTICS The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56362 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed.

• In Stop mode 4 ICCS — 100 150 µA PLL supply current —1 2 . 5 m A Input capacitance5 CIN — — 10 pF Notes: 1. Refers to MODA/IRQA , MODB/IRQB, MODC/IRQC, and MODD/IRQD pins 2. Power Consumption Considerations on page 4-3 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3V at TJ = 100°C. Maximum internal supply current is measured with VCC = 3.46 V at TJ = 100°C. 3. Deleted. 4. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). 5. Periodically sampled and not 100% tested 6. V CC = 3.3 V ± 5% V; TJ = 0°C to +100°C, CL = 50 pF 7. This characteristic does not apply to PCAP. 8. Driving EXTAL to the low V IHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 ξ VCC and the maximum VILX should be no higher than 0.1 ξ VCC. Table 2-3 DC Electrical Characteristics6 (Continued) Characteristics Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 2-5 INTERNAL CLOCKS Table 2-4 Internal Clocks, CLKOUT Characteristics Symbol Expression1, 2 Min Typ Max Internal operation frequency and CLKOUT with PLL enabled f— (Ef × MF)/ (PDF × DF) — Internal operation frequency and CLKOUT with PLL disabled f — Ef/2 — Internal clock and CLKOUT high period TH

• With PLL disabled — ET C —
• With PLL enabled and MF ≤ 4 0.49 × ETC × PDF × DF/MF — 0.51 × ETC × PDF × DF/MF
• With PLL enabled and MF > 4 0.47 × ETC × PDF × DF/MF — 0.53 × ETC × PDF × DF/MF Internal clock and CLKOUT low period TL
• With PLL disabled — ET C —
• With PLL enabled and MF ≤ 4 0.49 × ETC × PDF × DF/MF — 0.51 × ETC × PDF × DF/MF
• With PLL enabled and MF > 4 0.47 × ETC × PDF × DF/MF — 0.53 × ETC × PDF × DF/MF Internal clock and CLKOUT cycle time with PLL enabled TC — ETC × PDF × DF/MF — Internal clock and CLKOUT cycle time with PLL disabled TC —2 × ETC — Instruction cycle time ICYC —T C — Notes: 1. DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle 2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-6 DSP56362 Advance Information MOTOROLA Specifications EXTERNAL CLOCK OPERATION EXTERNAL CLOCK OPERATION The DSP56362 system clock is an externally supplied square wave voltage source connected to EXTAL(Figure 2-1) Figure 2-1 External Clock Timing Table 2-5 Clock Operation 100 and 120 MHz Values No. Characteristics Symbol

100 MHz 120 MHz

Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. Ef 0 100.0 0 120.0

2 EXTAL input high1, 2

• With PLL disabled (46.7%–53.3% duty cycle6) 4.67 ns ∞ 0.00 ns ∞
• With PLL enabled (42.5%–57.5% duty cycle6) 4.25 ns 157.0 µs 0.00 ns 157.0 µs

3 EXTAL input low1, 2 ETL

• With PLL disabled (46.7%–53.3% duty cycle6) 4.67 ns ∞ 4.67 ns — EXTAL VILC VIHC Midpoint Note: The midpoint is 0.5 (V IHC + VILC). ETH ETL ETC CLKOUT With PLL Disabled CLKOUT With PLL Enabled AA0459 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 2-7

• With PLL enabled (42.5%–57.5% duty cycle6) 4.25 ns 157.0 µs 4.25 ns 1570.00 EXTAL cycle time2 ETC • With PLL disabled 10.00 ns ∞ 8.33 ns —
• With PLL enabled 10.00 ns 273.1 µs 8.33 ns 273.1 µs

5 CLKOUT change from EXTAL fall with PLL

disabled 4.3 ns 11.0 ns CLKOUT rising edge from EXTAL rising edge with PLL enabled (MF = 1, PDF = 1, Ef > 15 MHz)3,5 0.0 ns 1.8 ns CLKOUT falling edge from EXTAL rising edge with PLL enabled (MF = 2 or 4, PDF = 1, Ef > 15 MHz)3,5 0.0 ns 1.8 ns CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF ≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)3,5 0.0 ns 1.8 ns Instruction cycle time = ICYC = TC See Table 2-5 (46.7%–53.3% duty cycle) ICYC• With PLL disabled 0.00 ns ∞

• With PLL enabled 0.00 ns 8.53 µs 8.53 µs Notes: 1. Measured at 50% of the input transition 2. The maximum value for PLL enabled is given for minimum V CO and maximum MF. 3. Periodically sampled and not 100% tested 4. The maximum value for PLL enabled is given for minimum V CO and maximum DF. 5. The skew is not guaranteed for any other MF value. 6. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. Table 2-5 Clock Operation (Continued) 100 and 120 MHz Values No. Characteristics Symbol

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2-8 DSP56362 Advance Information MOTOROLA Specifications Phase Lock Loop (PLL) Characteristics PHASE LOCK LOOP (PLL) CHARACTERISTICS RESET, STOP, MODE SELECT, AND INTERRUPT TIMING Table 2-6 PLL Characteristics Characteristics

100 MHz

VCO frequency when PLL enabled (MF × Ef × 2/PDF) 30 200 MHz PLL external capacitor (PCAP pin to VCCP) (CPCAP

• @ M F ≤ 4( M F × 580) − 100 (MF × 780) − 140 pF
• @ M F > 4 M F × 830 MF × 1470 pF Note: C PCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (680 × MF) – 120, for MF ≤ 4, or 1100 × MF, for MF > 4. Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values 6 No. Characteristics Expression

8 Delay from RESET assertion to

all pins at reset value3 — — 26.0 26.0 ns Required RESET duration4

• Power on, external clock generator, PLL disabled 50 × ETC 500.0 — 416.7 — ns
• Power on, external clock generator, PLL enabled 1000 × ETC 10.0 — 8.3 — µs
• Power on, internal oscillator 75000 × ETC 750 — 625 — µs
• During STOP, XTAL disabled (PCTL Bit 16 = 0) 75000 × ETC 750 — 625 — µs
• During STOP, XTAL enabled (PCTL Bit 16 = 1) 2.5 × TC 25.0 — 20.8 — ns
• During normal operation 2.5 × TC 25.0 — 20.8 — ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Reset, Stop, Mode Select, and Interrupt Timing MOTOROLA DSP56362 Advance Information 2-9 Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5

• Minimum 3.25 × TC + 2.0 34.5 — 29.1 ns
• Maximum 20.25 T C + 7.50 — 211.5 176.2 ns Synchronous reset setup time from RESET deassertion to CLKOUT Transition 1
• M i n i m u m TC 5.9 — ns
• Maximum — 10.0 ns Synchronous reset deasserted, delay time from the CLKOUT Transition 1 to the first external address output
• Minimum 3.25 × TC + 2.0 33.5 — ns
• Maximum 20.25 T C + 7.5 — 207.5 ns 13 Mode select setup time 30.0 — 30.0 ns 14 Mode select hold time 0.0 — 0.0 ns Minimum edge-triggered interrupt request assertion width 6.6 — 5.5 ns Minimum edge-triggered interrupt request deassertion width 6.6 — 5.5 ns Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid
• Caused by first interrupt instruction fetch 4.25 × TC + 2.0 44.5 — 37.4 ns
• Caused by first interrupt instruction execution 7.25 × TC + 2.0 74.5 — 62.4 ns Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution 10 × TC + 5.0 105.0 — 88.3 ns Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values 6 No. Characteristics Expression

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2-10 DSP56362 Advance Information MOTOROLA Specifications Reset, Stop, Mode Select, and Interrupt Timing Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts1 (3.75 + WS) × TC – 10.94 — (Note 9) — (Note 9) ns Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1 (3.25 + WS) × TC – 10.94 — (Note 9) — (Note 9) Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1

• D R A M f o r a l l W S (WS + 3.5) × TC – 10.94 — (Note 9) — (Note 9) ns
• S R A M W S = 1 (WS + 3.5) × TC – 10.94 — (Note 9) — (Note 9) ns
• S R A M W S = 2 , 3 1.75 × TC – 4.0 — (Note 9) — (Note 9) ns
• S R A M W S ≥ 4 2.75 × TC – 4.0 — (Note 9) — (Note 9) ns Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 Synchronous interrupt delay time from the CLKOUT Transition 2 to the first external address output valid caused by the first instruction fetch after coming out of Wait Processing state
• Minimum 9.25 × TC + 1.0 93.5 — 78.1 — ns
• Maximum 24.75 × TC + 5.0 — 252.5 — 211.2 ns

24 Duration for IRQA assertion to

recover from Stop state 0.6 × TC − 0.1 5.9 — 4.9 — ns Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values 6 No. Characteristics Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Reset, Stop, Mode Select, and Interrupt Timing MOTOROLA DSP56362 Advance Information 2-11 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) PLC × ETC × PDF + (128 K − PLC/2) × TC 1.3 13.6 — — ms
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) PLC × ETC × PDF + (23.75 ± 0.5) × TC 232.5 ns 12.3 ms — —
• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) PLC × ETC × PDF + (128K − PLC/2) × TC 13.6 — ms
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) PLC × ETC × PDF +
• PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) 5.5 × TC 55.0 — 45.8 — ns Interrupt Requests Rate
• HI08, ESAI, SHI, Timer 12T C — 120.0 — 100.0 ns
• D M A 8 T C — 80.0 — 66.7 ns
• I R Q, NMI (edge trigger) 8T C — 80.0 — 66.7 ns
• I R Q, NMI (level trigger) 12T C — 120.0 — 100.0 ns Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values 6 No. Characteristics Expression

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2-12 DSP56362 Advance Information MOTOROLA Specifications Reset, Stop, Mode Select, and Interrupt Timing DMA Requests Rate

• Data read from HI08, ESAI, SHI 6TC — 60.0 — 50.0 ns
• Data write to HI08, ESAI, SHI 7TC — 70.0 — 58.0 ns
• Timer 2T C — 20.0 — 16.7 ns
• I R Q, NMI (edge trigger) 3T C — 30.0 — 25.0 ns Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values 6 No. Characteristics Expression

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Reset, Stop, Mode Select, and Interrupt Timing MOTOROLA DSP56362 Advance Information 2-13 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid 4.25 × TC + 2.0 44.0 — 37.4 — ns Notes: 1. When using fast interrupts and IRQA , IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. 2. This timing depends on several settings: For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored). For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100 MHz = 40.96µs). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well. 3. Periodically sampled and not 100% tested 4. For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. 5. If PLL does not lose lock 6. V CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF 7. WS = number of wait states (measured in clock cycles, number of T C) 8. Use expression to compute maximum value. 9. These values depend on the number of wait states (WS) selected Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values 6 No. Characteristics Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-18 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) EXTERNAL MEMORY EXPANSION PORT (PORT A) SRAM Timing Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz 3 No. Characteristics Symbol Expression1 100 MHz 120 MHz Unit Min Max Min Max 100 Address valid and AA assertion pulse width tRC, tWC 101 Address and AA valid to WR assertion tAS

100 MHz:

0.25 × TC − 2.0 [WS = 1] 0.5 — 0.1 — ns 1.25 × TC − 2.0

102 WR assertion

All frequencies: WS × TC − 4.0 [2 ≤ WS ≤ 3] 16.0 — 12.7 — ns

103 WR deassertion to

0.25 × TC − 2.0 [1 ≤ WS ≤ 3] 0.5 — 0.1 — ns 1.25 × TC − 2.0 2.25 × TC − 2.0 All frequencies: 1.25 × TC − 4.0 [4 ≤ WS ≤ 7] 8.5 —6 . 4— 2.25 × TC − 4.0 [WS ≥ 8] 18.5 — 14.7 — 104 Address and AA valid to input data valid tAA, tAC [WS ≥ 1] —1 0 . 5 7 . 6n s Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-19

105 RD assertion to

[WS ≥ 1] —5 . 5—3 . 4 n s 106 RD deassertion to data not valid (data hold time) tOHZ 0.0 — 0.0 — ns

107 Address valid to

deassertion (data setup time) tDS (tDW) [WS ≥ 1] 4.5 — 3.2 — ns 109 Data hold time from WR deassertion tDH 0.25 × TC − 2.0 [1 ≤ WS ≤ 3] 0.5 — 0.1 — ns1.25 × TC − 2.0 2.25 × TC − 2.0

110 WR assertion to

0.75 × TC − 3.7 [WS = 1] —— ns 2.5 — 0.25 × TC − 3.7 −0.25 × TC − 3.7 111 WR deassertion to data high impedance 0.25 × TC + 0.2 [1 ≤ WS ≤ 3] —— ns —2 . 3 1.25 × TC + 0.2 2.25 × TC + 0.2 112 Previous RD deassertion to data active (write) 1.25 × TC − 4.0 [1 ≤ WS ≤ 3] —— ns 6.4 — 2.25 × TC − 4.0 3.25 × TC − 4.0 Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz 3 (Continued) No. Characteristics Symbol Expression1 100 MHz 120 MHz Unit Min Max Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-20 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A)

113 RD deassertion

0.75 × TC − 4.0 [1 ≤ WS ≤ 3] 3.5 — 2.2 — ns1.75 × TC − 4.0 2.75 × TC − 4.0

114 WR deassertion

0.5 × TC − 4.0 [WS = 1] 1.0 — 0.2 — ns TC − 2.0 2.5 × TC − 4.0 3.5 × TC − 4.0

115 Address valid to

116 RD assertion pulse

117 RD deassertion to

0.25 × TC − 2.0 [1 ≤ WS ≤ 3] 0.5 — 0.1 — ns1.25 × TC − 2.0 2.25 × TC − 2.0 118 TA setup before RD or WR deassertion4

119 TA hold after RD or

WR deassertion 0 — 0.0 — ns Notes: 1. WS is the number of wait states specified in the BCR. 2. Timings 100, 107 are guaranteed by design, not tested. 3. All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc 4. In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active 5. Timing 110, 111, and 112, are not specified for 100 MHz. Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz 3 (Continued) No. Characteristics Symbol Expression1 100 MHz 120 MHz Unit Min Max Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-22 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) DRAM Timing The selection guides provided in Figure 2-13 and Figure 2-16 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance. Figure 2-13 DRAM Page Mode Wait States Selection Guide Chip Frequency (MHz) DRAM Type (tRAC ns) 100 40 66 80 100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

Note: This figure should be used for primary selection. For exact and detailed timings see the following tables. AA0472 120 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-23 Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 No. Characteristics Symbol Expression 20 MHz6 30 MHz6 Unit Min Max Min Max 131 Page mode cycle time for two consecutive accesses of the same direction tPC 2 × TC 100.0 — 66.7 — ns Page mode cycle time for mixed (read and write) accesses. 1.25 x Tc 62.5 — 41.7 —

132 CAS assertion to data valid

(read) tCAC TC − 7.5 — 42.5 — 25.8 ns

133 Column address valid to

data valid (read) tAA 1.5 × TC − 7.5 — 67.5 — 42.5 ns

134 CAS deassertion to data not

valid (read hold time) tOFF 0.0 — 0.0 — ns

135 Last CAS assertion to RAS

deassertion tRSH 0.75 × TC − 4.0 33.5 — 21.0 — ns

136 Previous CAS deassertion to

RAS deassertion tRHCP 2 × TC − 4.0 96.0 — 62.7 — ns 137 CAS assertion pulse width tCAS 0.75 × TC − 4.0 33.5 — 21.0 — ns 138 Last CAS deassertion to RAS deassertion4 tCRP ns• BRW[1:0] = 00 1.75 × TC − 6.0 81.5 — 52.3 — 139 CAS deassertion pulse width tCP 0.5 × TC − 4.0 21.0 — 12.7 — ns

140 Column address valid to

CAS assertion tASC 0.5 × TC − 4.0 21.0 — 12.7 — ns

141 CAS assertion to column

address not valid tCAH 0.75 × TC − 4.0 33.5 — 21.0 — ns

142 Last column address valid to

RAS deassertion tRAL 2 × TC − 4.0 96.0 — 62.7 — ns

143 WR deassertion to CAS

assertion tRCS 0.75 × TC − 3.8 33.7 — 21.2 — ns

144 CAS deassertion to WR

assertion tRCH 0.25 × TC − 3.7 8.8 — 4.6 — ns

145 CAS assertion to WR

deassertion tWCH 0.5 × TC − 4.2 20.8 — 12.5 — ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-24 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) 146 WR assertion pulse width tWP 1.5 × TC − 4.5 70.5 — 45.5 — ns

147 Last WR assertion to RAS

deassertion tRWL 1.75 × TC − 4.3 83.2 — 54.0 — ns

148 WR assertion to CAS

deassertion tCWL 1.75 × TC − 4.3 83.2 — 54.0 — ns

149 Data valid to CAS assertion

(Write) tDS 0.25 × TC − 4.0 8.5 — 4.3 — ns

150 CAS assertion to data not

valid (write) tDH 0.75 × TC − 4.0 33.5 — 21.0 — ns

151 WR assertion to CAS

assertion tWCS TC − 4.3 45.7 — 29.0 — ns

152 Last RD assertion to RAS

deassertion tROH 1.5 × TC − 4.0 71.0 — 46.0 — ns 153 RD assertion to data valid tGA T C − 7.5 — 42.5 — 25.8 ns

154 RD deassertion to data not

valid 5 tGZ 0.0 — 0.0 — ns 155 WR assertion to data active 0.75 × TC − 0.3 37.2 — 24.7 — ns

156 WR deassertion to data high

impedance 0.25 × TC — 12.5 — 8.3 ns Notes: 1. The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 2 × TC for read-after-read or write-after-write sequences). 4. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 5. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 6. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state. See Figure 2-13. Table 2-10 DRAM Page Mode Timings, Two Wait States 1, 2, 3, 7 No. Characteristics Symbol Expression

80 MHz

Page mode cycle time for two consecutive accesses of the same direction tPC 3 × TC 37.5 — ns Page mode cycle time for mixed (read and write) accesses. 2.75 x Tc 34.4 — Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (Continued) No. Characteristics Symbol Expression 20 MHz6 30 MHz6 Unit Min Max Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-25 132 CAS assertion to data valid (read) tCAC 1.5 × TC − 6.5 — 12.3 ns

133 Column address valid to data valid

(read) tAA 2.5 × TC − 6.5 — 24.8 ns

134 CAS deassertion to data not valid (read

hold time) tOFF 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 1.75 × TC − 4.0 17.9 — ns

136 Previous CAS deassertion to RAS

deassertion tRHCP 3.25 × TC − 4.0 36.6 — ns 137 CAS assertion pulse width tCAS 1.5 × TC − 4.0 14.8 — ns 138 Last CAS deassertion to RAS deassertion5 tCRP ns• BRW[1:0] = 00 2.0 × TC − 6.0 19.0 — 139 CAS deassertion pulse width tCP 1.25 × TC − 4.0 11.6 — ns 140 Column address valid to CAS assertion tASC TC − 4.0 8.5 — ns

141 CAS assertion to column address not

valid tCAH 1.75 × TC − 4.0 17.9 — ns

142 Last column address valid to RAS

deassertion tRAL 3 × TC − 4.0 33.5 — ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC − 3.8 11.8 — ns 144 CAS deassertion to WR assertion tRCH 0.5 × TC − 3.7 2.6 — ns 145 CAS assertion to WR deassertion tWCH 1.5 × TC − 4.2 14.6 — ns 146 WR assertion pulse width tWP 2.5 × TC − 4.5 26.8 — ns 147 Last WR assertion to RAS deassertion tRWL 2.75 × TC − 4.3 30.1 — ns 148 WR assertion to CAS deassertion tCWL 2.5 × TC − 4.3 27.0 — ns 149 Data valid to CAS assertion (write) tDS 0.25 × TC − 3.0 0.1 — ns 150 CAS assertion to data not valid (write) tDH 1.75 × TC − 4.0 17.9 — ns 151 WR assertion to CAS assertion tWCS TC − 4.3 8.2 — ns 152 Last RD assertion to RAS deassertion tROH 2.5 × TC − 4.0 27.3 — ns 153 RD assertion to data valid tGA 1.75 × TC − 6.5 — 15.4 ns 154 RD deassertion to data not valid6 tGZ 0.0 — ns 155 WR assertion to data active 0.75 × TC − 0.3 9.1 — ns Table 2-10 DRAM Page Mode Timings, Two Wait States 1, 2, 3, 7 (Continued) No. Characteristics Symbol Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-26 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) impedance 0.25 × TC —3 . 1 n s Notes: 1. The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56362. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 × TC for read-after-read or write-after-write sequences). 5. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 7. There are not any fast enough DRAMs to fit to two wait states Page mode @ 100MHz. See Figure 2-13. Table 2-11 DRAM Page Mode Timings, Three Wait States 1, 2, 3 No. Characteristics Symbol Expression Page mode cycle time for two consecutive accesses of the same direction tPC 4 × TC 40.0 — ns Page mode cycle time for mixed (read and write) accesses. 3.5 x Tc 35.0 —

132 CAS assertion to data valid (read) tCAC

2 × TC − 7.0 — 13.0 ns (read) tAA 100 MHz: 3 × TC − 7.0 — 23.0 ns hold time) tOFF 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 2.5 × TC − 4.0 21.0 — ns deassertion tRHCP 4.5 × TC − 4.0 41.0 — ns 137 CAS assertion pulse width tCAS 2 × TC − 4.0 16.0 — ns 138 Last CAS deassertion to RAS assertion5 tCRP ns• BRW[1:0] = 00 2.25 × TC − 6.0 — — Table 2-10 DRAM Page Mode Timings, Two Wait States 1, 2, 3, 7 (Continued) No. Characteristics Symbol Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-27 139 CAS deassertion pulse width tCP 1.5 × TC − 4.0 11.0 — ns 140 Column address valid to CAS assertion tASC TC − 4.0 6.0 — ns valid tCAH 2.5 × TC − 4.0 21.0 — ns deassertion tRAL 4 × TC − 4.0 36.0 — ns

143 WR deassertion to CAS assertion tRCS

1.25 × TC − 4.0 8.5 ns

144 CAS deassertion to WR assertion tRCH

0.75 × TC − 4.0 3.5 ns 145 CAS assertion to WR deassertion tWCH 2.25 × TC − 4.2 18.3 — ns 146 WR assertion pulse width tWP 3.5 × TC − 4.5 30.5 — ns 147 Last WR assertion to RAS deassertion tRWL 3.75 × TC − 4.3 33.2 — ns 148 WR assertion to CAS deassertion tCWL 3.25 × TC − 4.3 28.2 — ns 149 Data valid to CAS assertion (write) tDS 0.5 × TC − 4.0 1.0 — ns 150 CAS assertion to data not valid (write) tDH 2.5 × TC − 4.0 21.0 — ns 151 WR assertion to CAS assertion tWCS 1.25 × TC − 4.3 8.2 — ns 152 Last RD assertion to RAS deassertion tROH 3.5 × TC − 4.0 31.0 — ns

153 RD assertion to data valid tGA

2.5 × TC − 7.0 — 18.0 ns 154 RD deassertion to data not valid6 tGZ 0.0 — ns 155 WR assertion to data active 0.75 × TC − 0.3 7.2 — ns impedance 0.25 × TC —2 . 5 n s Notes: 1. The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56362 . 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 × TC for read-after-read or write-after-write sequences). 5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. 6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Table 2-11 DRAM Page Mode Timings, Three Wait States 1, 2, 3 (Continued) No. Characteristics Symbol Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-28 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Table 2-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz 1, 2, 3 No. Characteristics Symbol Expression Page mode cycle time for two consecutive accesses of the same direction tPC 5 × TC 50.0 — 41.7 ns Page mode cycle time for mixed (read and write) accesses. 4.5 × TC 45.0 — 37.5 2.75 × TC − 7.0 — 20.5 — 15.9 ns (read) tAA 100 MHz: 3.75 × TC − 7.0 — 30.5 — 24.2 ns

134 CAS deassertion to data not valid

(read hold time) tOFF 0.0 — 0.0 — ns deassertion tRSH 3.5 × TC − 4.0 31.0 — 25.2 — ns deassertion tRHCP 6 × TC − 4.0 56.0 — 46.0 — ns 137 CAS assertion pulse width tCAS 2.5 × TC − 4.0 21.0 — 16.8 — ns 138 Last CAS deassertion to RAS assertion5 139 CAS deassertion pulse width tCP 2 × TC − 4.0 16.0 — 12.7 — ns

140 Column address valid to CAS

assertion tASC TC − 4.0 6.0 — 4.3 — ns valid tCAH 3.5 × TC − 4.0 31.0 — 25.2 — ns deassertion tRAL 5 × TC − 4.0 46.0 — 37.7 — ns 145 CAS assertion to WR deassertion tWCH 3.25 × TC − 4.2 28.3 — 22.9 — ns 146 WR assertion pulse width tWP 4.5 × TC − 4.5 40.5 — 33.0 — ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-29 deassertion tRWL 4.75 × TC − 4.3 43.2 — 35.3 — ns 148 WR assertion to CAS deassertion tCWL 3.75 × TC − 4.3 33.2 — 26.9 — ns 149 Data valid to CAS assertion (write) tDS 0.5 × TC − 4.0 1.0 — 0.2 — ns 150 CAS assertion to data not valid (write) tDH 3.5 × TC − 4.0 31.0 — 25.2 — ns 151 WR assertion to CAS assertion tWCS 1.25 × TC − 4.3 8.2 — 6.1 — ns 152 Last RD assertion to RAS deassertion tROH 4.5 × TC − 4.0 41.0 — 33.5 — ns 3.25 × TC − 7.0 — 25.5 — 20.1 ns 154 RD deassertion to data not valid6 tGZ 0.0 — 0.0 — ns 155 WR assertion to data active 0.75 × TC − 0.3 7.2 — 5.9 ns impedance 0.25 × TC —2 . 5—2 . 1n s Notes: 1. The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56362. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 × TC for read-after-read or write-after-write sequences). 5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Table 2-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz1, 2, 3 (Continued) No. Characteristics Symbol Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-30 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Figure 2-14 DRAM Page Mode Write Accesses RAS CAS A0–A17 WR RD D0–D23 ColumnRow Data Out Data Out Data Out Last ColumnColumn Add Address Address Address 136 135131 139 141 137 140 142 147 144151 148146 155 156 150 138 145 143 149 AA0473 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-31 Figure 2-15 DRAM Page Mode Read Accesses RAS CAS A0–A17 WR RD D0–D23 Column Last ColumnColumnRow Data In Data InData In Add Address Address Address 136 135131 137 140 141 142 143 152133 153 132 138139 134 154 AA0474 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-32 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Figure 2-16 DRAM Out-of-Page Wait States Selection Guide Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States 1, 2 No. Characteristics3 Symbol Expression 20 MHz4 30 MHz4 Unit Min Max Min Max

157 Random read or write

cycle time tRC 5 × TC 250.0 — 166.7 — ns

158 RAS assertion to data

valid (read) tRAC 2.75 × TC − 7.5 — 130.0 — 84.2 ns

159 CAS assertion to data

valid (read) tCAC 1.25 × TC − 7.5 — 55.0 — 34.2 ns

160 Column address valid to

data valid (read) tAA 1.5 × TC − 7.5 — 67.5 — 42.5 ns

161 CAS deassertion to data

not valid (read hold time) tOFF 0.0 — 0.0 — ns

162 RAS deassertion to RAS

assertion tRP 1.75 × TC − 4.0 83.5 — 54.3 — ns Chip Frequency (MHz) DRAM Type (tRAC ns) 100 66 80 100

8 Wait States

11 Wait States

15 Wait States

Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. 40 120 AA0475 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-33

163 RAS assertion pulse

width tRAS 3.25 × TC − 4.0 158.5 — 104.3 — ns

164 CAS assertion to RAS

deassertion tRSH 1.75 × TC − 4.0 83.5 — 54.3 — ns

165 RAS assertion to CAS

deassertion tCSH 2.75 × TC − 4.0 133.5 — 87.7 — ns

166 CAS assertion pulse

width tCAS 1.25 × TC − 4.0 58.5 — 37.7 — ns

167 RAS assertion to CAS

168 RAS assertion to column

169 CAS deassertion to RAS

assertion tCRP 2.25 × TC − 4.0 108.5 — 71.0 — ns

170 CAS deassertion pulse

width tCP 1.75 × TC − 4.0 83.5 — 54.3 — ns

171 Row address valid to

RAS assertion tASR 1.75 × TC − 4.0 83.5 — 54.3 — ns

172 RAS assertion to row

address not valid tRAH 1.25 × TC − 4.0 58.5 — 37.7 — ns

173 Column address valid to

CAS assertion tASC 0.25 × TC − 4.0 8.5 — 4.3 — ns

174 CAS assertion to column

address not valid tCAH 1.75 × TC − 4.0 83.5 — 54.3 — ns

175 RAS assertion to column

address not valid tAR 3.25 × TC − 4.0 158.5 — 104.3 — ns

176 Column address valid to

RAS deassertion tRAL 2 × TC − 4.0 96.0 — 62.7 — ns

177 WR deassertion to CAS

assertion tRCS 1.5 × TC − 3.8 71.2 — 46.2 — ns

178 CAS deassertion to WR

assertion tRCH 0.75 × TC − 3.7 33.8 — 21.3 — ns

179 RAS deassertion to WR

assertion tRRH 0.25 × TC − 3.7 8.8 — 4.6 — ns

180 CAS assertion to WR

deassertion tWCH 1.5 × TC − 4.2 70.8 — 45.8 — ns

181 RAS assertion to WR

deassertion tWCR 3 × TC − 4.2 145.8 — 95.8 — ns Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States 1, 2 (Continued) No. Characteristics3 Symbol Expression 20 MHz4 30 MHz4 Unit Min Max Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-34 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) 182 WR assertion pulse width tWP 4.5 × TC − 4.5 220.5 — 145.5 — ns

183 WR assertion to RAS

deassertion tRWL 4.75 × TC − 4.3 233.2 — 154.0 — ns

184 WR assertion to CAS

deassertion tCWL 4.25 × TC − 4.3 208.2 — 137.4 — ns

185 Data valid to CAS

assertion (write) tDS 2.25 × TC − 4.0 108.5 — 71.0 — ns

186 CAS assertion to data not

valid (write) tDH 1.75 × TC − 4.0 83.5 — 54.3 — ns

187 RAS assertion to data not

valid (write) tDHR 3.25 × TC − 4.0 158.5 — 104.3 — ns

188 WR assertion to CAS

assertion tWCS 3 × TC − 4.3 145.7 — 95.7 — ns

189 CAS assertion to RAS

assertion (refresh) tCSR 0.5 × TC − 4.0 21.0 — 12.7 — ns

190 RAS deassertion to CAS

assertion (refresh) tRPC 1.25 × TC − 4.0 58.5 — 37.7 — ns

191 RD assertion to RAS

deassertion tROH 4.5 × TC − 4.0 221.0 — 146.0 — ns 192 RD assertion to data valid tGA 4 × TC − 7.5 — 192.5 — 125.8 ns

193 RD deassertion to data

not valid3 tGZ 0.0 — 0.0 — ns

194 WR assertion to data

active 0.75 × TC − 0.3 37.2 — 24.7 — ns

195 WR deassertion to data

high impedance 0.25 × TC — 12.5 — 8.3 ns Notes: 1. The number of wait states for out of page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states. See Figure 2-16. Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States 1, 2 (Continued) No. Characteristics3 Symbol Expression 20 MHz4 30 MHz4 Unit Min Max Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-35 Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States 1, 2 No. Characteristics4 Symbol Expression3 80 MHz Unit Min Max

157 Random read or write cycle time tRC 9 × TC

1. 5 —n s 158 RAS assertion to data valid (read) tRAC 4.75 × TC − 6.5 52.9 ns 159 CAS assertion to data valid (read) tCAC 2.25 × TC − 6.5 — 21.6 ns 160 Column address valid to data valid (read) tAA 3 × TC − 6.5 — 31.0 ns

161 CAS deassertion to data not valid (read

hold time) tOFF 0.0 — ns 162 RAS deassertion to RAS assertion tRP 3.25 × TC − 4.0 36.6 — ns 163 RAS assertion pulse width tRAS 5.75 × TC − 4.0 67.9 — ns 164 CAS assertion to RAS deassertion tRSH 3.25 × TC − 4.0 36.6 — ns 165 RAS assertion to CAS deassertion tCSH 4.75 × TC − 4.0 55.4 — ns 166 CAS assertion pulse width tCAS 2.25 × TC − 4.0 24.1 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × TC ± 2 29.3 33.3 ns 168 RAS assertion to column address valid tRAD 1.75 × TC ± 2 19.9 23.9 ns 169 CAS deassertion to RAS assertion tCRP 4.25 × TC − 4.0 49.1 — ns 170 CAS deassertion pulse width tCP 2.75 × TC − 4.0 30.4 — ns 171 Row address valid to RAS assertion tASR 3.25 × TC − 4.0 36.6 — ns 172 RAS assertion to row address not valid tRAH 1.75 × TC − 4.0 17.9 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 5.4 — ns 174 CAS assertion to column address not valid tCAH 3.25 × TC − 4.0 36.6 — ns 175 RAS assertion to column address not valid tAR 5.75 × TC − 4.0 67.9 — ns 176 Column address valid to RAS deassertion tRAL 4 × TC − 4.0 46.0 — ns 177 WR deassertion to CAS assertion tRCS 2 × TC − 3.8 21.2 — ns 178 CAS deassertion to WR5 assertion tRCH 1.25 × TC − 3.7 11.9 — ns 179 RAS deassertion to WR5 assertion tRRH 0.25 × TC − 3.0 0.1 — ns 180 CAS assertion to WR deassertion tWCH 3 × TC − 4.2 33.3 — ns 181 RAS assertion to WR deassertion tWCR 5.5 × TC − 4.2 64.6 — ns 182 WR assertion pulse width tWP 8.5 × TC − 4.5 101. 8 —n s 183 WR assertion to RAS deassertion tRWL 8.75 × TC − 4.3 105. 1 —n s 184 WR assertion to CAS deassertion tCWL 7.75 × TC − 4.3 92.6 — ns 185 Data valid to CAS assertion (write) tDS 4.75 × TC − 4.0 55.4 — ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-36 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) 186 CAS assertion to data not valid (write) tDH 3.25 × TC − 4.0 36.6 — ns 187 RAS assertion to data not valid (write) tDHR 5.75 × TC − 4.0 67.9 — ns 188 WR assertion to CAS assertion tWCS 5.5 × TC − 4.3 64.5 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × TC − 4.0 14.8 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 1.75 × TC − 4.0 17.9 — ns 191 RD assertion to RAS deassertion tROH 8.5 × TC − 4.0 102. 3 —n s 192 RD assertion to data valid tGA 7.5 × TC − 6.5 — 87.3 ns 193 RD deassertion to data not valid4 tGZ 0.0 0.0 — ns 194 WR assertion to data active 0.75 × TC − 0.3 9.1 — ns 195 WR deassertion to data high impedance 0.25 × TC —3 . 1n s Notes: 1. The number of wait states for out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56362. 4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 5. Either t RCH or tRRH must be satisfied for read cycles. Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 No. Characteristics4 Symbol Expression3 100 MHz Unit Min Max 157 Random read or write cycle time tRC 12 × TC 120.0 — ns 158 RAS assertion to data valid (read) tRAC 6.25 × TC − 7.0 — 55.5 ns 159 CAS assertion to data valid (read) tCAC 3.75 × TC − 7.0 — 30.5 ns

160 Column address valid to data valid

(read) tAA 4.5 × TC − 7.0 — 38.0 ns hold time) tOFF 0.0 — ns 162 RAS deassertion to RAS assertion tRP 4.25 × TC − 4.0 38.5 — ns 163 RAS assertion pulse width tRAS 7.75 × TC − 4.0 73.5 — ns 164 CAS assertion to RAS deassertion tRSH 5.25 × TC − 4.0 48.5 — ns 165 RAS assertion to CAS deassertion tCSH 6.25 × TC − 4.0 58.5 — ns Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States 1, 2 (Continued) No. Characteristics4 Symbol Expression3 80 MHz Unit Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-37 166 CAS assertion pulse width tCAS 3.75 × TC − 4.0 33.5 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × TC ± 4 . 02 1 . 02 9 . 0n s 168 RAS assertion to column address valid tRAD 1.75 × TC ± 4.0 13.5 21.5 ns 169 CAS deassertion to RAS assertion tCRP 5.75 × TC − 4.0 53.5 — ns 170 CAS deassertion pulse width tCP 4.25 × TC − 4.0 38.5 — ns 171 Row address valid to RAS assertion tASR 4.25 × TC − 4.0 38.5 — ns 172 RAS assertion to row address not valid tRAH 1.75 × TC − 4.0 13.5 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 3.5 — ns

174 CAS assertion to column address not

valid tCAH 5.25 × TC − 4.0 48.5 — ns

175 RAS assertion to column address not

valid tAR 7.75 × TC − 4.0 73.5 — ns

176 Column address valid to RAS

deassertion tRAL 6 × TC − 4.0 56.0 — ns 177 WR deassertion to CAS assertion tRCS 3.0 × TC − 4.0 26.0 — ns 178 CAS deassertion to WR5 assertion tRCH 1.75 × TC − 4.0 13.5 — ns

179 RAS deassertion to WR5 assertion tRRH

180 CAS assertion to WR deassertion tWCH 5 × TC − 4.2 45.8 — ns 181 RAS assertion to WR deassertion tWCR 7.5 × TC − 4.2 70.8 — ns 182 WR assertion pulse width tWP 11.5 × TC − 4.5 110.5 — ns 183 WR assertion to RAS deassertion tRWL 11.75 × TC − 4.3 113.2 — ns 184 WR assertion to CAS deassertion tCWL 10.25 × TC − 4.3 103.2 — ns 185 Data valid to CAS assertion (write) tDS 5.75 × TC − 4.0 53.5 — ns 186 CAS assertion to data not valid (write) tDH 5.25 × TC − 4.0 48.5 — ns 187 RAS assertion to data not valid (write) tDHR 7.75 × TC − 4.0 73.5 — ns 188 WR assertion to CAS assertion tWCS 6.5 × TC − 4.3 60.7 — ns

189 CAS assertion to RAS assertion

(refresh) tCSR 1.5 × TC − 4.0 11.0 — ns

190 RAS deassertion to CAS assertion

(refresh) tRPC 2.75 × TC − 4.0 23.5 — ns 191 RD assertion to RAS deassertion tROH 11.5 × TC − 4.0 111.0 — ns 192 RD assertion to data valid tGA 10 × TC − 7.0 93.0 ns Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued) No. Characteristics4 Symbol Expression3 100 MHz Unit Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-38 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) 193 RD deassertion to data not valid4 tGZ 0.0 — ns 194 WR assertion to data active 0.75 × TC − 0.3 7.2 — ns

195 WR deassertion to data high

impedance 0.25 × TC —2 . 5 n s Notes: 1. The number of wait states for out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56362. 4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 5. Either t RCH or tRRH must be satisfied for read cycles. Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 No. Characteristics3 Symbol Expression 157 Random read or write cycle time tRC 16 × TC 160.0 — 133.3 — ns 158 RAS assertion to data valid (read) tRAC 8.25 × TC − 5.7 — 76.8 — 63.0 ns 159 CAS assertion to data valid (read) tCAC 4.75 × TC − 5.7 — 41.8 — 33.9 ns (read) tAA 5.5 × TC − 5.7 — 49.3 40.1 ns

161 CAS deassertion to data not valid

(read hold time) tOFF 0.0 0.0 — 0.0 — ns 162 RAS deassertion to RAS assertion tRP 6.25 × TC − 4.0 58.5 — 48.1 — ns 163 RAS assertion pulse width tRAS 9.75 × TC − 4.0 93.5 — 77.2 — ns 164 CAS assertion to RAS deassertion tRSH 6.25 × TC − 4.0 58.5 — 48.1 — ns 165 RAS assertion to CAS deassertion tCSH 8.25 × TC − 4.0 78.5 — 64.7 — ns 166 CAS assertion pulse width tCAS 4.75 × TC − 4.0 43.5 — 35.6 — ns

168 RAS assertion to column address

169 CAS deassertion to RAS assertion tCRP 7.75 × TC − 4.0 73.5 — 60.6 — ns 170 CAS deassertion pulse width tCP 6.25 × TC − 4.0 58.5 — 48.1 — ns

171 Row address valid to RAS

assertion tASR 6.25 × TC − 4.0 58.5 — 48.1 — ns Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued) No. Characteristics4 Symbol Expression3 100 MHz Unit Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-39

172 RAS assertion to row address not

valid tRAH 2.75 × TC − 4.0 23.5 — 18.9 — ns

173 Column address valid to CAS

assertion tASC 0.75 × TC − 4.0 3.5 — 2.2 — ns

174 CAS assertion to column address

not valid tCAH 6.25 × TC − 4.0 58.5 — 48.1 — ns

175 RAS assertion to column address

not valid tAR 9.75 × TC − 4.0 93.5 — 77.2 — ns deassertion tRAL 7 × TC − 4.0 66.0 — 54.3 — ns 177 WR deassertion to CAS assertion tRCS 5 × TC − 3.8 46.2 — 37.9 — ns 178 CAS deassertion to WR5 assertion tRCH 1.75 × TC − 3.7 13.8 — 10.9 — ns 179 RAS deassertion to WR5 assertion tRRH 0.25 × TC − 2.0 0.5 — 0.1 — ns 180 CAS assertion to WR deassertion tWCH 6 × TC − 4.2 55.8 — 45.8 — ns 181 RAS assertion to WR deassertion tWCR 9.5 × TC − 4.2 90.8 — 75.0 — ns 182 WR assertion pulse width tWP 15.5 × TC − 4.5 150.5 — 124.7 — ns 183 WR assertion to RAS deassertion tRWL 15.75 × TC − 4.3 153.2 — 126.9 — ns 184 WR assertion to CAS deassertion tCWL 14.25 × TC − 4.3 138.2 — 114.4 — ns 185 Data valid to CAS assertion (write) tDS 8.75 × TC − 4.0 83.5 — 68.9 — ns

186 CAS assertion to data not valid

(write) tDH 6.25 × TC − 4.0 58.5 — 48.1 — ns

187 RAS assertion to data not valid

(write) tDHR 9.75 × TC − 4.0 93.5 — 77.2 — ns 188 WR assertion to CAS assertion tWCS 9.5 × TC − 4.3 90.7 — 74.9 — ns (refresh) tCSR 1.5 × TC − 4.0 11.0 — 8.5 — ns (refresh) tRPC 4.75 × TC − 4.0 43.5 — 35.6 — ns 191 RD assertion to RAS deassertion tROH 15.5 × TC − 4.0 151.0 — 125.2 — ns 192 RD assertion to data valid tGA 14 × TC − 5.7 — 134.3 — 111.0 ns 193 RD deassertion to data not valid3 tGZ 0.0 — 0.0 — ns 194 WR assertion to data active 0.75 × TC − 0.3 7.2 — 5.9 — ns impedance 0.25 × TC —2 . 5—2 . 1 n s Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 (Continued) No. Characteristics3 Symbol Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-40 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Figure 2-17 DRAM Out-of-Page Read Access Notes: 1. The number of wait states for out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4. Either t RCH or tRRH must be satisfied for read cycles. Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 (Continued) No. Characteristics3 Symbol Expression A0–A17 WR RD D0–D23 Data Row Address Column Address In 157 163 165 162162 169 170 171 168 167 164 166 173 174 175 172 177 176 191 160 168 159 193 161 192 158 179 AA0476 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-41 Figure 2-18 DRAM Out-of-Page Write Access RAS CAS A0–A17 WR RD D0–D23 Data Out Column AddressRow Address 162 163 165 162 157 169 170 167 168 164 166 171 173 174 176 172 181 175 180188 182 184 183 187 185 194 186 195 AA0477 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-42 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Figure 2-19 DRAM Refresh Access RAS CAS WR 157 163 162162 190 170 165 189 177 AA0478 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-43 Synchronous Timings (SRAM) Table 2-17 External Bus Synchronous Timings (SRAM Access) 4 No. Characteristics Expression1, 2 100 MHz Unit Min Max

198 CLKOUT high to address, and

AA valid5 0.25 × TC + 4.0 — 6.5 ns

199 CLKOUT high to address, and

AA invalid5 0.25 × TC 2.5 — ns

200 TA valid to CLKOUT high

(setup time) 4.0 — ns

201 CLKOUT high to TA invalid

(hold time) 0.0 — ns 202 CLKOUT high to data out active 0.25 × TC 2.5 — ns 203 CLKOUT high to data out valid 0.25 × TC + 4.0 3.3 6.5 ns

204 CLKOUT high to data out

invalid 0.25 × TC 2.5 — ns

205 CLKOUT high to data out high

impedance 0.25 × TC —2 . 5n s

206 Data in valid to CLKOUT high

(setup) 4.0 — ns

207 CLKOUT high to data in invalid

(hold) 0.0 — ns 208 CLKOUT high to RD assertion 0.75 × TC + 4.0 8.2 11.5 ns

209 CLKOUT high to RD

deassertion 0.0 4.0 ns

210 CLKOUT high to WR assertion3

0.5 × TC + 4.3 [WS = 1 or WS ≥ 4] 6.3 9.3 ns All frequencies:

211 CLKOUT high to WR

deassertion 0.0 3.8 ns Notes: 1. WS is the number of wait states specified in the BCR. 2. The asynchronous delays specified in the expressions are valid for DSP56362. 3. If WS > 1, WR assertion refers to the next rising edge of CLKOUT. 4. External bus synchronous timings should be used only for reference to the clock and not for relative timings. 5. T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to determine whether the access referenced by A0–A23 is internal or external, when this mode is enabled Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-44 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Figure 2-20 Synchronous Bus Timings SRAM 1 WS (BCR Controlled) WR RD Data OutD0–D23 CLKOUT TA Data InD0–D23 A0–A17 AA0–AA3 199 201 200 211 210 208 209 207 198 205 204203 202 206 AA0479 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-45 Figure 2-21 Synchronous Bus Timings SRAM 2 WS (TA Controlled) A0–A17 WR RD Data OutD0–D23 AA0–AA3 CLKOUT TA Data InD0–D23 198 199 201 200 201 211 209 207 208 210 200 203 202 205 204 206 AA0480 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-46 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Arbitration Timings Table 2-18 Arbitration Bus Timings1 No. Characteristics Expression

212 CLKOUT high to BR assertion/

deassertion2 1.0 4.0 ns

213 BG asserted/deasserted to

CLKOUT high (setup) 4.0 — ns

214 CLKOUT high to BG deasserted/

asserted (hold) 0.0 — ns

215 BB deassertion to CLKOUT high

(input setup) 4.0 — ns

216 CLKOUT high to BB assertion

(input hold) 0.0 — ns

217 CLKOUT high to BB assertion

(output) 1.0 4.0 ns

218 CLKOUT high to BB deassertion

(output) 1.0 4.0 ns

219 BB high to BB high impedance

(output) —4 . 5n s

220 CLKOUT high to address and

controls active 0.25 × TC 2.5 — ns

221 CLKOUT high to address and

controls high impedance 0.25 × TC —2 . 5n s 222 CLKOUT high to AA active 0.25 × TC 2.5 — ns 223 CLKOUT high to AA deassertion 0.25 × TC + 4.0 3.2 6.5 ns

224 CLKOUT high to AA high

impedance 0.75 × TC —7 . 5n s Notes: 1. The asynchronous delays specified in the expressions are valid for DSP56362. 2. T212 is valid for Address Trace mode when the ATE bit in the OMR is set. BR is deasserted for internal accesses and asserted for external accesses. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-47 Figure 2-22 Bus Acquisition Timings A0–A17 BB AA0–AA3 CLKOUT BR BG RD, WR 212 214 216 215 220 217 213 222 AA0481 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-48 DSP56362 Advance Information MOTOROLA Specifications External Memory Expansion Port (Port A) Figure 2-23 Bus Release Timings Case 1 (BRT Bit in OMR Cleared) A0–A17 BB AA0–AA3 CLKOUT BR BG RD, WR 212 214 218 221 224 223 213 219 AA0482 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-49 Figure 2-24 Bus Release Timings Case 2 (BRT Bit in OMR Set) Table 2-19 Asynchronous Bus Arbitration timing No. Characteristics Expression

250 BB assertion window from BG

input negation. 2 .5* Tc + 5 — 20 ns

251 Delay from BB assertion to BG

assertion 2 * Tc + 5 20 — ns Comments: 1. Bit 13 in the OMR register must be set to enter Asynchro- nous Arbitration mode 2. At 100 MHz it is recommended to use Asynchronous Arbi- tration mode. 3. If Asynchronous Arbitration mode is active, none of the tim- ings in Table 2-19 is required. 4. In order to guarantee timings 250, and 251, it is recommend- ed to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 2-25. A0–A17 BB AA0–AA3 CLKOUT BR BG RD, WR 223 218 219 214 212 213 221 224 AA0483 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Host Interface (HDI08) Timing MOTOROLA DSP56362 Advance Information 2-51 PARALLEL HOST INTERFACE (HDI08) TIMING Table 2-20 Host Interface (HDI08) Timing1, 2 No. Characteristics3 Expression

317 Read data strobe assertion width4

HACK read assertion width TC + 9.9 19.9 — ns

318 Read data strobe deassertion width4

HACK read deassertion width —9 . 9 — n s 319 Read data strobe deassertion width4 after “Last Data Register” reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK deassertion width after “Last Data Register” reads5,6 2.5 × TC + 6.6 31.6 — ns

320 Write data strobe assertion width8

HACK write assertion width —1 3 . 2 — n s 321 Write data strobe deassertion width8 HACK write deassertion width

• after ICR, CVR and “Last Data Register” writes5 2.5 × TC + 6.6 31.6 — ns
• after IVR writes, or
• after TXH:TXM writes (with HBE=0), or after TXL:TXM writes (with HBE=1) 16.5 — 322 HAS assertion width —9 . 9 — n s 323 HAS deassertion to data strobe assertion9 —0 . 0 — n s 324 Host data input setup time before write data strobe deassertion8 Host data input setup time before HACK write deassertion —9 . 9 — n s 325 Host data input hold time after write data strobe deassertion8 Host data input hold time after HACK write deassertion —3 . 3 — n s 326 Read data strobe assertion to output data active from high impedance4 HACK read assertion to output data active from high impedance —3 . 3 — n s

327 Read data strobe assertion to output data valid4

HACK read assertion to output data valid —— 2 4 . 2 n s Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-52 DSP56362 Advance Information MOTOROLA Specifications Parallel Host Interface (HDI08) Timing 328 Read data strobe deassertion to output data high impedance4 HACK read deassertion to output data high impedance —— 9 . 9 n s 329 Output data hold time after read data strobe deassertion4 Output data hold time after HACK read deassertion —3 . 3 — n s 330 HCS assertion to read data strobe deassertion4 TC +9.9 19.9 — ns 331 HCS assertion to write data strobe deassertion8 —9 . 9 — n s 332 HCS assertion to output data valid —— 1 9 . 1 n s 333 HCS hold time after data strobe deassertion9 —0 . 0 — n s

334 Address (AD7–AD0) setup time before HAS

deassertion (HMUX=1) —4 . 7 — n s

335 Address (AD7–AD0) hold time after HAS

deassertion (HMUX=1) —3 . 3 — n s 336 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data strobe assertion9

• Read —0 — ns
• W r i t e 4 . 7 —

337 A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W

hold time after data strobe deassertion9 —3 . 3 — n s 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read4, 5, 10 TC 10 — ns 339 Delay from write data strobe deassertion to host request assertion for “Last Data Register” write5, 8, 10 2 × TC 20 — ns 340 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD = 0)5, 9, 10 —— 1 9 . 1 n s 341 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD = 1, open drain Host Request)5, 9, 10, 11 —— 300. 0 ns Table 2-20 Host Interface (HDI08) Timing1, 2 (Continued) No. Characteristics3 Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Host Interface (HDI08) Timing MOTOROLA DSP56362 Advance Information 2-53 342 Delay from DMA HACK deassertion to HOREQ assertion

• For “Last Data Register” read5 ns2 × TC + 19.1 39.1 —
• For “Last Data Register” write5 1.5 × TC + 19.1 34.1 —
• For other cases 0.0 — 343 Delay from DMA HACK assertion to HOREQ deassertion
• H R O D = 05 —— 2 0 . 2 n s 344 Delay from DMA HACK assertion to HOREQ deassertion for “Last Data Register” read or write
• HROD = 1, open drain Host Request 5, 11 —— 300. 0 ns Notes: 1. See Host Port Usage Considerations in the DSP56362 User Design Manual. 2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. 3. V CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF 4. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. 5. The “last data register” is the register at address $7, which is the last location to be read or written in data transfers. This is RXL/TXL in the little endian mode (HBE = 0), or RXH/TXH in the big endian mode (HBE = 1). 6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode. 10. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 11. In this calculation, the host request signal is pulled up by a 4.7 k Ω resistor in the open-drain mode. Table 2-20 Host Interface (HDI08) Timing1, 2 (Continued) No. Characteristics3 Expression

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Host Interface (HDI08) Timing MOTOROLA DSP56362 Advance Information 2-55 Figure 2-29 Write Timing Diagram, Non-Multiplexed Bus HWR, HDS HA0–HA2 HCS HD0–HD7 HOREQ, HRRQ, HTRQ 336 331 337 321 320 324 325 339340 341 333 AA0485 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-56 DSP56362 Advance Information MOTOROLA Specifications Parallel Host Interface (HDI08) Timing Figure 2-30 Read Timing Diagram, Multiplexed Bus HRD, HDS HA8–HA10 HAS HAD0–HAD7 HOREQ, HRRQ, HTRQ Address Data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 AA0486 322 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-58 DSP56362 Advance Information MOTOROLA Specifications Serial Host Interface SPI Protocol Timing Figure 2-33 Host DMA Read Timing Diagram SERIAL HOST INTERFACE SPI PROTOCOL TIMING Table 2-21 Serial Host Interface SPI Protocol Timing No. Characteristics Mode Filter Mode Expression 100MHz Unit Min Max

140 Tolerable spike width

on clock or data in — Bypassed nsNarrow — 50 Wide — 100

141 Minimum serial clock

cycle = tSPICC(min) Master Bypassed 6 ×TC+46 106 — nsNarrow 6 ×TC+152 212 — Wide 6 ×TC+223 283 — 326 317 318 327 328 329 Data Valid HOREQ (Output) HACK (Input) H0-H7 (Output) RXH Read 343 342342 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Serial Host Interface SPI Protocol Timing MOTOROLA DSP56362 Advance Information 2-59

142 Serial clock high period

Bypassed 0.5 ×tSPICC –10 43 — ns Narrow 0.5 ×tSPICC –10 96 — Wide 0.5 ×tSPICC –10 131 — Slave Bypassed 2.5 ×TC+12 37 — Narrow 2.5 ×TC+102 127 — Wide 2.5 ×TC+189 214 —

143 Serial clock low period

Bypassed 0.5 ×tSPICC –10 43 — ns Narrow 0.5 ×tSPICC –10 96 — Wide 0.5 ×tSPICC –10 131 — Slave Bypassed 2.5 ×TC+12 37 — Narrow 2.5 ×TC+102 127 — Wide 2.5 ×TC+189 214 —

144 Serial clock rise/fall

Master — — — 10 nsSlave — — — 2000 146 SS assertion to first SCK edge CPHA = 0 Slave Bypassed 3.5 ×TC+15 50 — ns Narrow 0 0 — Wide 0 0 — CPHA = 1 Slave Bypassed 10 10 — Narrow 0 0 — Wide 0 0 —

147 Last SCK edge to SS

Bypassed 12 12 — nsNarrow 102 102 — Wide 189 189 — 148 Data input valid to SCK edge (data input set-up time) Master /Slave Bypassed 0 0 — nsNarrow MAX{(20-T C), 0} 10 — Wide MAX{(40-T C), 0} 30 — 149 SCK last sampling edge to data input not valid Master /Slave Bypassed 2.5 ×TC+10 35 — nsNarrow 2.5 ×TC+30 55 — Wide 2.5 ×TC+50 75 —

150 SS assertion to data

out active Slave — 2 2 — ns

151 SS deassertion to data

high impedance Slave — 9 — 9 ns 152 SCK edge to data out valid (data out delay time) Master /Slave Bypassed 2 ×TC+33 — 53 nsNarrow 2 ×TC+123 — 143 Wide 2 ×TC+210 — 230 Table 2-21 Serial Host Interface SPI Protocol Timing (Continued) No. Characteristics Mode Filter Mode Expression 100MHz Unit Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-60 DSP56362 Advance Information MOTOROLA Specifications Serial Host Interface SPI Protocol Timing 153 SCK edge to data out not valid (data out hold time) Master /Slave Bypassed T C+5 15 — nsNarrow T C+55 65 — Wide T C+106 116 —

154 SS assertion to data

out valid (CPHA = 0) Slave — T C+33 — 43 ns 157 First SCK sampling edge to HREQ output deassertion Slave Bypassed 2.5 ×TC+30 — 55 nsNarrow 2.5 ×TC+120 — 145 Wide 2.5 ×TC+217 — 242 158 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed 2.5 ×TC+30 55 — nsNarrow 2.5 ×TC+80 105 — Wide 2.5 ×TC+136 161 — 159 SS deassertion to HREQ output not deasserted (CPHA = 0) Slave — 2.5 ×TC+30 55 — ns

160 SS deassertion pulse

width (CPHA = 0) Slave — T C+6 16 — ns

161 HREQ in assertion to

Bypassed 0.5 × tSPICC + 2.5×TC+43 121 — nsNarrow 0.5 ×tSPICC + 2.5×TC+43 174 — Wide 0.5 ×tSPICC + 2.5×TC+43 209 — 162 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) Master — 0 0 — ns 163 First SCK edge to HREQ in not asserted (HREQ in hold time) Master — 0 0 — ns Note: Periodically sampled, not 100% tested Table 2-21 Serial Host Interface SPI Protocol Timing (Continued) No. Characteristics Mode Filter Mode Expression 100MHz Unit Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Serial Host Interface SPI Protocol Timing MOTOROLA DSP56362 Advance Information 2-61 Figure 2-34 SPI Master Timing (CPHA = 0) SS (Input) MISO (Input) Valid MOSI (Output) MSB Valid LSB MSB LSB HREQ (Input) 141 142 143 144 144 141 144 144143 142 148 149 149 148 152 153 163 161 AA0271 SCK (CPOL=0 (Output) SCK (CPOL = 1 (Output) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-62 DSP56362 Advance Information MOTOROLA Specifications Serial Host Interface SPI Protocol Timing Figure 2-35 SPI Slave Timing (CPHA = 0) SS (Input) MISO (Input) Valid MOSI (Output) MSB Valid LSB MSB LSB HREQ (Input) 141 142 143 144 144 141 144 144143 142 148 148 149 152 153 163 161 162 149 AA0272 SCK (CPOL = 0 (Output) SCK (CPOL = 1 (Output) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Serial Host Interface SPI Protocol Timing MOTOROLA DSP56362 Advance Information 2-63 Figure 2-36 SPI Master Timing (CPHA = 1) SS (Input) MISO (Input) Valid MOSI (Output) MSB Valid LSB MSB LSB HREQ (Input) 141 142 143 144 144 141 144 144143 142 148 148 149 152 153 163 161 162 149 AA0272 SCK (CPOL = 0 (Output) SCK (CPOL = 1 (Output) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-64 DSP56362 Advance Information MOTOROLA Specifications Serial Host Interface SPI Protocol Timing Figure 2-37 SPI Slave Timing (CPHA = 0) SS (Input) MISO (Output) MOSI (Input) MSB LSB MSB LSB HREQ (Output) 141 142 143 144 144 141 144 144143 142 154 150 152 153 148 149 159157 153 151 Valid Valid 148 149 147 160 146 AA0273 SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Serial Host Interface SPI Protocol Timing MOTOROLA DSP56362 Advance Information 2-65 Figure 2-38 SPI Slave Timing (CPHA = 1) SS (Input) MISO (Output) MOSI (Input) MSB LSB MSB LSB HREQ (Output) 141 142 143 144 144 144 144143 142 150 152 148 149 158 153 151 Valid Valid 148 147 146 152 149 157 AA0274 SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-66 DSP56362 Advance Information MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING Table 2-22 SHI I2C Protocol Timing Standard I2C* No. Characteristics Symbol/ Expression Standard Fast-Mode Unit Min Max Min Max Tolerable spike width on SCL or SDA —Filters bypassed — 0 — 0 ns Narrow filters enabled — 50 — 50 ns Wide filters enabled — 100 — 100 ns

171 SCL clock frequency FSCL — 100 — 400 kHz

172 Bus free time TBUF 4.7 — 1.3 — µs 173 Start condition set-up time TSU;STA 4.7 — 0.6 — µs 174 Start condition hold time THD;STA 4.0 — 0.6 — µs 175 SCL low period TLOW 4.7 — 1.3 — µs 176 SCL high period THIGH 4.0 — 1.3 — µs 177 SCL and SDA rise time TR — 1000 20 + 0.1 × Cb 300 ns 178 SCL and SDA fall time TF — 300 20 + 0.1 × Cb 300 ns

179 Data set-up time TSU;DAT 250 — 100 — ns

180 Data hold time THD;DAT 0.0 — 0.0 0.9 µs 181 Stop condition set-up time TSU;STO 4.0 — 0.6 — µs

182 Capacitive load for each line Cb — 400 — 400 pF

Filters bypassed 10.6 — 28.5 — MHz Narrow filters enabled 11.8 — 39.7 — MHz Wide filters enabled 13.1 — 61.0 — MHz

184 HREQ in deassertion to last SCL edge

(HREQ in set-up time) tSU;RQI 0.0 — 0.0 — ns 186 First SCL sampling edge to HREQ output deassertion2 TNG;RQO Filters bypassed 2 × TC + 30 — 50 — 50 ns Narrow filters enabled 2 × TC + 120 — 140 — 140 ns Wide filters enabled 2 × TC + 208 — 228 — 228 ns 187 Last SCL edge to HREQ output not deasserted2 TAS;RQO Filters bypassed 2 × TC + 30 50 — 50 — ns Narrow filters enabled 2 × TC + 80 100 — 100 — ns Wide filters enabled 2 × TC + 135 155 — 155 — ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Serial Host Interface (SHI) I2C Protocol Timing MOTOROLA DSP56362 Advance Information 2-67 Programming the Serial Clock The programmed serial clock cycle, TI CCP, is specified by the value of the HDM[5:0] and HRS bits of the HCKR (SHI clock control register). The expression for TI CCP is where – HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. – HDM[7:0] are the divider modulus select bits. – A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 × TC (if HDM[5:0] = $02 and HRS = 1) to 4096 × TC (if HDM[7:0] = $FF and HRS = 0) The programmed serial clock cycle (TI CCP), SCL rise time (TR), and the filters selected should be chosen in order to achieve the desired SCL frequency, as shown in Table 2-23 188 HREQ in assertion to first SCL edge TAS;RQI 0.5 × TI2CCP 0.5 × TC - 21 Filters bypassed 4327 — 927 — ns Narrow filters enabled 4282 — 882 — ns Wide filters enabled 4238 — 838 — ns Note: R P (min) = 1.5 k¾ Table 2-22 SHI I2C Protocol Timing (Continued) Standard I2C* No. Characteristics Symbol/ Expression Standard Fast-Mode Unit Min Max Min Max Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-68 DSP56362 Advance Information MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing EXAMPLE: For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard-mode I2C environment (FSCL = 100 KHz (i.e. TSCL = 10µs), TR = 1000ns), with filters bypassed TI CCP = 10µs - 2.5×10ns - 45ns - 1000ns = 8930ns Choosing HRS = 0 gives Thus the HDM[7:0] value should be programmed to $38 (=56). Figure 2-39 I2C Timing Table 2-23 SCL Serial Clock Cycle generated as Master Filters bypassed TI CCP + 2.5 × TC + 45ns + TR Narrow filters enabled TI CCP + 2.5 × TC + 135ns + TR Wide filters enabled TI CCP + 2.5 × TC + 223ns + TR Start SCL HREQ SDA ACKMSB LSBStop 171 Stop 173 176 175 177 178 180 179 172 186 182 183 189 174 188 184 187 AA0275 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Enhanced Serial Audio Interface Timing MOTOROLA DSP56362 Advance Information 2-69 ENHANCED SERIAL AUDIO INTERFACE TIMING Table 2-24 Enhanced Serial Audio Interface Timing No. Characteristics1, 2, 3 Symbol Expression

430 Clock cycle5 tSSICC

4 x TC 40.0 — i ck nsRXC:3 xTC 30 — x ck TXC:MAX [3xTC;t454] 40 x ck 431 Clock high period

• For internal clock — 2 × TC − 10.0 10.0 — ns
• For external clock 1.5 × TC 15.0 — 432 Clock low period
• For internal clock — 2 × TC − 10.0 10.0 — ns
• For external clock 1.5 × TC 15.0 —

433 RXC rising edge to FSR out (bl)

high —— — 37.0 x ck ns— 22.0 i ck a 434 RXC rising edge to FSR out (bl) low —— — 37.0 x ck ns— 22.0 i ck a

435 RXC rising edge to FSR out (wr)

high6 —— — 39.0 x ck ns— 24.0 i ck a

436 RXC rising edge to FSR out (wr)

low6 —— 39.0 x ck ns— 24.0 i ck a

437 RXC rising edge to FSR out (wl)

high —— — 36.0 x ck ns— 21.0 i ck a

438 RXC rising edge to FSR out (wl)

low —— — 37.0 x ck ns— 22.0 i ck a 439 Data in setup time before RXC (TXC in synchronous mode) falling edge 0.0 — x ck ns19.0 — i ck

440 Data in hold time after RXC falling

edge —— 5.0 — x ck ns3.0 — i ck

441 FSR input (bl, wr) high before

RXC falling edge 6 —— 23.0 — x ck ns1.0 — i ck a

442 FSR input (wl) high before RXC

falling edge —— 1.0 — x ck ns23.0 — i ck a

443 FSR input hold time after RXC

falling edge —— 3.0 — x ck ns0.0 — i ck a

444 Flags input setup before RXC

— — 0.0 — x ck ns19.0 — i ck s Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-70 DSP56362 Advance Information MOTOROLA Specifications Enhanced Serial Audio Interface Timing

445 Flags input hold time after RXC

falling edge —— 6.0 — x ck ns0.0 — i ck s

446 TXC rising edge to FST out (bl)

high —— — 29.0 x ck ns— 15.0 i ck 447 TXC rising edge to FST out (bl) low —— — 31.0 x ck ns— 17.0 i ck

448 TXC rising edge to FST out (wr)

high6 —— — 31.0 x ck ns— 17.0 i ck

449 TXC rising edge to FST out (wr)

low6 —— — 33.0 x ck ns— 19.0 i ck

450 TXC rising edge to FST out (wl)

high —— — 30.0 x ck ns— 16.0 i ck 451 TXC rising edge to FST out (wl) low —— — 31.0 x ck ns— 17.0 i ck

452 TXC rising edge to data out enable

from high impedance —— — 31.0 x ck ns— 17.0 i ck

453 TXC rising edge to transmitter drive

enable assertion —— — 34.0 x ck ns— 20.0 i ck 454 TXC rising edge to data out valid — 23 + 0.5 × TC 21.0 — 28.0 x ck ns— 21.0 i ck

455 TXC rising edge to data out high

impedance7 —— — 31.0 x ck ns— 16.0 i ck

456 TXC rising edge to transmitter drive

enable deassertion7 —— — 34.0 x ck ns— 20.0 i ck

457 FST input (bl, wr) setup time before

TXC falling edge6 —— 2.0 — x ck ns21.0 — i ck

458 FST input (wl) to data out enable

— — — 27.0 — ns

459 FST input (wl) to transmitter drive

enable assertion — — — 31.0 — ns

460 FST input (wl) setup time before

TXC falling edge —— 2.0 — x ck ns21.0 — i ck

461 FST input hold time after TXC

falling edge —— 4.0 —— x ck ns0.0 — i ck

462 Flag output valid after TXC rising

edge — — — 32.0 x ck ns— 18.0 i ck 463 HCKR/HCKT clock cycle —— 4 0 . 0 — n s Table 2-24 Enhanced Serial Audio Interface Timing (Continued) No. Characteristics1, 2, 3 Symbol Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Enhanced Serial Audio Interface Timing MOTOROLA DSP56362 Advance Information 2-71

464 HCKT input rising edge to TXC

output — — — 27.5 ns

465 HCKR input rising edge to RXC

output — — — 27.5 ns Notes: 1. V CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF 2. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) 3. bl = bit length wl = word length wr = word length relative 4. TXC(SCKT pin) = transmit clock RXC(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 5. For the internal clock, the clock cycle at the pin is defined by Icyc and the ESAI control registers. 6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7. Periodically sampled and not 100% tested Table 2-24 Enhanced Serial Audio Interface Timing (Continued) No. Characteristics1, 2, 3 Symbol Expression iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-72 DSP56362 Advance Information MOTOROLA Specifications Enhanced Serial Audio Interface Timing Figure 2-40 ESAI Transmitter Timing Last Bit See Note TXC (Input/Output) FST (Bit) Out FST (Word) Out Data Out Transmitter Drive Enable FST (Bit) In FST (Word) In Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. First Bit 430 432 446 447 450 451 455 454454 452 459 456453 461 457 458 460 461 462 431 AA0490 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-74 DSP56362 Advance Information MOTOROLA Specifications Digital Audio Transmitter Timing Figure 2-43 ESAI HCKR Timing DIGITAL AUDIO TRANSMITTER TIMING Table 2-25 Digital Audio Transmitter Timing No. Characteristic Expression ACI frequency (see note) —— 5 0 M H z

220 ACI period 2 × TC 20 — ns

221 ACI high duration 0.5 × TC 5—n s 222 ACI low duration 0.5 × TC 5—n s 223 ACI rising edge to ADO valid 1.5 × TC —1 5n s Note: In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56362 internal clock frequency. For example, if the DSP56362 is running at 100 MHz internally, the ACI frequency should be less than 50 MHz. HCKR SCKR (output) 465 463 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 2-75 Figure 2-44 Digital Audio Transmitter Timing TIMER TIMING Table 2-26 Timer Timing No. Characteristics Expression 480 TIO Low 2 × TC + 2.0 22.0 — ns 481 TIO High 2 × TC + 2.0 22.0 — ns

482 Timer setup time from TIO (Input)

assertion to CLKOUT rising edge 9.0 10.0 ns 483 Synchronous timer delay time from CLKOUT rising edge to the external memory access address out valid caused by first interrupt instruction execution 10.25 × TC + 1.0 103. 5 —n s 484 CLKOUT rising edge to TIO (Output) assertion

• M i n i m u m 0.5 × TC + 3.5 8.5 — ns
• Maximum 0.5 × TC + 19.8 — 24.8 485 CLKOUT rising edge to TIO (Output) deassertion ns•M i n i m u m 60.5 × TC + 3.5 8.5 —
• Maximum 0.5 × TC + 19.0 — 24.8 Note: V CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF ACI ADO 220 223 AA1280 221 222 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-76 DSP56362 Advance Information MOTOROLA Specifications GPIO Timing Figure 2-45 TIO Timer Event Input Restrictions Figure 2-46 Timer Interrupt Generation Figure 2-47 External Pulse Generation GPIO TIMING Table 2-27 GPIO Timing No. Characteristics Expression

490 CLKOUT edge to GPIO out valid (GPIO

out delay time) — 31.0 ns

491 CLKOUT edge to GPIO out not valid

(GPIO out hold time) 3.0 — ns TIO 481480 AA0492 CLKOUT TIO (Input) First Interrupt Instruction Execution Address 482 483 AA0493 CLKOUT TIO (Output) 484 485 AA0494 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 2-77 Figure 2-48 GPIO Timing

492 GPIO In valid to CLKOUT edge (GPIO

in set-up time) 12.0 — ns

493 CLKOUT edge to GPIO in not valid

(GPIO in hold time) 0.0 — ns

494 Fetch to CLKOUT edge before GPIO

change 6.75 × TC 67.5 — ns

495 GPIO out rise time — — 13 ns

496 GPIO out fall time — — 13 ns

Note: V CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF Table 2-27 GPIO Timing (Continued) No. Characteristics Expression (Input) GPIO (Output) CLKOUT (Output) Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. A0–A17 490 491 492 494 493 AA0495 GPIO (Output) 495 496 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-78 DSP56362 Advance Information MOTOROLA Specifications JTAG Timing JTAG TIMING Figure 2-49 Test Clock Input Timing Diagram Table 2-28 JTAG Timing No. Characteristics All frequencies Unit Min Max 500 TCK frequency of operation (1/(TC × 3); maximum 22 MHz) 0.0 22.0 MHz 501 TCK cycle time in Crystal mode 45.0 — ns 502 TCK clock pulse width measured at 1.5 V 20.0 — ns 503 TCK rise and fall times 0.0 3.0 ns 504 Boundary scan input data setup time 5.0 — ns 505 Boundary scan input data hold time 24.0 — ns 506 TCK low to output data valid 0.0 40.0 ns 507 TCK low to output high impedance 0.0 40.0 ns 508 TMS, TDI data setup time 5.0 — ns 509 TMS, TDI data hold time 25.0 — ns 510 TCK low to TDO data valid 0.0 44.0 ns 511 TCK low to TDO high impedance 0.0 44.0 ns 512 TRST assert time 100.0 — ns 513 TRST setup time to TCK low 40.0 — ns Notes: 1. V CC = 3.3 V ± 0.16V; TJ = 0°C to +100°C, CL = 50 pF 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. TCK (Input) VM VMVIH VIL 501 502 502 503503 AA0496 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2-80 DSP56362 Advance Information MOTOROLA Specifications OnCE Module TimIng Figure 2-52 TRST Timing Diagram OnCE MODULE TIMING Figure 2-53 OnCE—Debug Request OnCE Module Timing No. Characteristics Expression

500 TCK frequency of operation

1/(TC × 3), max 22.0 MHz 0.0 22.0 MHz

514 DE assertion time in order to enter

Debug mode 1.5 × TC + 10.0 25.0 — ns 515 Response time when DSP56362 is executing NOP instructions from internal memory 5.5 × TC + 30.0 — 85.0 ns 516 Debug acknowledge assertion time 3 × TC + 10.0 40.0 — ns Note: V CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF TCK (Input) TRST (Input) 513 512 AA0499 DE 516515 514 AA0500 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 3-1 SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The DSP56362 is available in a 144-pin LQFP package. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

3-2 DSP56362 Advance Information MOTOROLA Packaging Pin-out and Package Information Top view of the LQFP package is shown in Figure 3-1 with its pin-outs. The LQFP package mechanical drawing is shown in Figure 3-2. Figure 3-1 DSP56362 Thin Quad Flat Pack (LQFP), Top View SCK SS HREQ SDO0 SDO1 SDO2 SDO3 VCCS GNDS SDO4 SDO5 FST FSR SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS HRW HACK HOREQ VCCS GNDS ADO ACI TIO0 HCS HA9 HA8 HAS HAD7 HAD6 HAD5 HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET VCCP PCAP GNDP GNDP1 VCCQH AA3 AA2 CAS DE GNDQ EXTAL VCCQL VCCC GNDC CLKOUT PINIT TA BR BB VCCC GNDC WR RD AA1 AA0 BG A0D7 VCCD GNDD D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQL GNDQ D20 VCCD GNDD D21 D22 D23 TRST TDO TDI TCK TMS MOSI MISO 1 37 73109 (Top View) Orientation Mark VCCA GNDA VCCA GNDA VCCA GNDA A10 A11 GNDQ VCCQL A12 A13 A14 VCCQH GNDA A15 A16 A17 VCCD GNDD AA0301 MODD MODC MODB MODA Note: Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table 3-2 for detailed information about pin functions and signal names. nc DSP56362 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Pin-out and Package Information MOTOROLA DSP56362 Advance Information 3-3 Table 3-1 DSP56362 LQFP Signal Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1 SCK/SCL 26 GNDS 51 AA2/RAS2

2 SS/HA2 27 ADO or PD1 52 CAS

3 HREQ 28 ACI or PD0 53 DE

4 SDO0 or PC11 29 TIO0 54 GNDQ

5 SDO1 or PC10 30 HCS/HCS, HA10, or PB13 55 EXTAL

6 SDO2/SDI3 or PC9 31 HA2, HA9, or PB10 56 VCCQL

7 SDO3/SDI2 or PC8 32 HA1, HA8, or PB9 57 VCCC

8 VCCS 33 HA0, HAS/HAS, or PB8 58 GNDC

9 GNDS 34 H7, HAD7, or PB7 59 CLKOUT

10 SDO4/SDI1 or PC7 35 H6, HAD6, or PB6 60 NC (not connected)

11 SDO5/SDI0 or PC6 36 H5, HAD5, or PB5 61 PINIT/NMI

12 FST or PC4 37 H4, HAD4, or PB4 62 TA

13 FSR or PC1 38 VCCH 63 BR

14 SCKT or PC3 39 GNDH 64 BB

15 SCKR or PC0 40 H3, HAD3, or PB3 65 VCCC

16 HCKT or PC5 41 H2, HAD2, or PB2 66 GNDC

17 HCKR or PC2 42 H1, HAD1, or PB1 67 WR

18 VCCQL 43 H0, HAD0, or PB0 68 RD

19 GNDQ 44 RESET 69 AA1/RAS1

20 VCCQH 45 VCCP 70 AA0/RAS0

21 HDS/HDS, HWR/HWR, or

22 HRW, HRD/HRD, or PB11 47 GNDP 72 A0

23 HACK/HACK,

HRRQ/HRRQ, or PB15 48 GNDP1 73 A1

24 HOREQ/HOREQ,

HTRQ/HTRQ, or PB14 49 VCCQH 74 VCCA

25 VCCS 50 AA3/RAS3 75 GNDA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

3-4 DSP56362 Advance Information MOTOROLA Packaging Pin-out and Package Information

76 A2 99 A17 122 D16

77 A3 100 D0 123 D17

78 A4 101 D1 124 D18

79 A5 102 D2 125 D19

80 V CCA 103 V CCD 126 V CCQL

81 GND A 104 GND D 127 GND Q

82 A6 105 D3 128 D20

83 A7 106 D4 129 V CCD

84 A8 107 D5 130 GND D

85 A9 108 D6 131 D21

86 V CCA 109 D7 132 D22

87 GND A 110 D8 133 D23

88 A10 111 V CCD 134 MODD/IRQD

89 A11 112 GND D 135 MODC/IRQC

90 GND Q 113 D9 136 MODB/IRQB

91 V CCQL 114 D10 137 MODA/IRQA

92 A12 115 D11 138 TRST

93 A13 116 D12 139 TDO

94 A14 117 D13 140 TDI

95 V CCQH 118 D14 141 TCK

96 GND A 119 V CCD 142 TMS

97 A15 120 GND D 143 MOSI/HA0

98 A16 121 D15 144 MISO/SDA

Note: Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some pins have two or more configurable functions; names assigned to these pins indicate the function for a specific configuration. For example, pin 34 is data line H7 in nonmultiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Table 3-2 DSP56362 LQFP Signal Identification by Name Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. not connected 60 D13 117 GND P1 48 A0 72 D14 118 GND Q 19 A1 73 D15 121 GND Q 54 Table 3-1 DSP56362 LQFP Signal Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Pin-out and Package Information MOTOROLA DSP56362 Advance Information 3-5 A10 88 D16 122 GND Q 90 A11 89 D17 123 GND Q 127 A12 92 D18 124 GND S 9 A13 93 D19 125 GND S 26 A14 94 D2 102 H0 43 A15 97 D20 128 H1 42 A16 98 D21 131 H2 41 A17 99 D22 132 H3 40 A2 76 D23 133 H4 37 A3 77 D3 105 H5 36 A4 78 D4 106 H6 35 A5 79 D5 107 H7 34 A6 82 D6 108 HA0 33 A7 83 D7 109 HA0 143 A8 84 D8 110 HA1 32 A9 85 D9 113 HA10 30 AA0 70 DE 53 HA2 2 AA1 69 EXTAL 55 HA2 31 AA2 51 FSR 13 HA8 32 AA3 50 FST 12 HA9 31 ACI 28 GND A 75 HACK /HACK 23 ADO 27 GND A 81 HAD0 43 BB 64 GND A 87 HAD1 42 BG 71 GND A 96 HAD2 41 BR 63 GND C 58 HAD3 40 CAS 52 GND C 66 HAD4 37 CLKOUT 59 GND D 104 HAD5 36 D0 100 GND D 112 HAD6 35 D1 101 GND D 120 HAD7 34 D10 114 GND D 130 HAS /HAS 33 D11 115 GND H 39 HCS /HCS 30 D12 116 GND P 47 HDS /HDS 21 Table 3-2 DSP56362 LQFP Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

3-6 DSP56362 Advance Information MOTOROLA Packaging Pin-out and Package Information HOREQ/HOREQ 24 PB9 32 SDO3 7 HRD/HRD 22 PC0 15 SDO4 10 HREQ 3 PC1 13 SDO5 11 HRRQ/HRRQ 23 PC10 5 SS 2 HRW 22 PC11 4 TA 62 HCKR 17 PC2 17 TCK 141 HCKT 16 PC3 14 TDI 140 HTRQ/HTRQ 24 PC4 12 TDO 139 HWR/HWR 21 PC5 16 TIO0 29 IRQA 137 PC6 11 TMS 142 IRQB 136 PC7 10 TRST 138 IRQC 135 PC8 7 V CCA 74 IRQD 134 PC9 6 V CCA 80 MISO 144 PCAP 46 V CCA 86 MODA 137 PD0 28 V CCC 57 MODB 136 PD1 27 V CCC 65 MODC 135 PINIT 61 V CCD 103 MODD 134 RAS0 70 V CCD 111 MOSI 143 RAS1 69 V CCD 119 NMI 61 RAS2 52 V CCD 129 PB0 43 RAS3 51 V CCH 38 PB1 42 RD 68 V CCP 45 PB10 31 RESET 44 V CCQH 20 PB11 22 SCK 1 V CCQH 49 PB12 21 SCKR 15 V CCQH 95 PB13 30 SCKT 14 V CCQL 18 PB14 24 SCL 1 V CCQL 56 PB15 23 SDA 144 V CCQL 91 PB2 41 SDI0 11 V CCQL 126 PB3 40 SDI1 10 V CCS 8 PB4 37 SDI2 7 V CCS 25 PB5 36 SDI3 6 WR 67 PB6 35 SDO0 4 PB7 34 SDO1 5 PB8 33 SDO2 6 Table 3-2 DSP56362 LQFP Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Pin-out and Package Information MOTOROLA DSP56362 Advance Information 3-7 LQFP PACKAGE MECHANICAL DRAWING Figure 3-2 DSP56362 144-pin LQFP Package Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

3-8 DSP56362 Advance Information MOTOROLA Packaging Ordering Drawings ORDERING DRAWINGS The detailed package drawing is available on the Motorola web page at: http://mot.sps.com/cgi-bin/cases Use package 918-03 for the search. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 4-1 SECTION 4 DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation: Where: T A = ambient temperature °C RqJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package W Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance. Where: R θJA = package junction-to-ambient thermal resistance °C/W RθJC = package junction-to-case thermal resistance °C/W RθCA = package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages.

• To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink.
• To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. TJ TA PD RθJA×()+= RθJA RθJC RθCA+= Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

4-2 DSP56362 Advance Information MOTOROLA Design Considerations Electrical Design Considerations

• If the temperature of the package case (T T) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ – TT)/PD. As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. ELECTRICAL DESIGN CONSIDERATIONS Use the following list of recommendations to assure correct DSP operation:
• Provide a low-impedance path from the board power supply to each V CC pin on the DSP and from the board ground to each GND pin.
• Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V CC and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.
• Use at least a four-layer PCB with two inner layers for V CC and GND.
• Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended. CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V CC). The suggested value for a pullup or pulldown resistor is 10 k ohm. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Power Consumption Considerations MOTOROLA DSP56362 Advance Information 4-3

• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits.
• All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the pins with internal pull-up resistors (TRST, TMS, DE, TCK, and TDI).
• Take special care to minimize noise levels on the V CCP, GNDP, and GNDP1 pins.
• If multiple DSP56362 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices.
• RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before deassertion of RESET.
• At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V CC never exceeds 3.95 V. POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula: where C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following:
• Set the EBD bit when not accessing external memory.
• Minimize external memory accesses and use internal memory accesses. Example 1 Current Consumption For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling at its maximum possible rate (50 MHz), the current consumption is IC V f ××= I5 0 1 0 12–× 3.3× 50× 106× 8.25mA== Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

4-4 DSP56362 Advance Information MOTOROLA Design Considerations PLL Performance Issues

• Minimize the number of pins that are switching.
• Minimize the capacitive load on the pins.
• Connect the unused inputs to pull-up or pull-down resistors.
• Disable unused peripherals.
• Disable unused pin activity (e.g., CLKOUT, XTAL). One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. where : I typF2 = current at F2 ItypF1 = current at F1 F2 = high frequency (any specified operating frequency) F1 = low frequency (any specified operating frequency lower than F2) Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. PLL PERFORMANCE ISSUES The following explanations should be considered as general observations on expected PLL behavior. There is no testing that verifies these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. Phase Skew Performance The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature, and voltage ranges. As defined in Figure 2-1, for input frequencies greater than 15 MHz and the MF ≤ 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between −1.4 ns and +3.2 ns. Phase Jitter Performance The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns. IM I P S§I M H z §I typF2 ItypF1–() F2 F1–()§== Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 4-5 Frequency Jitter Performance The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2–3%. Input (EXTAL) Jitter Requirements The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. HOST PORT CONSIDERATIONS Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This synchronization is a common problem when two asynchronous systems are connected, as they are in the host interface. The following paragraphs present considerations for proper operation. Host Programming Considerations

• Unsynchronized Reading of Receive Byte Registers—When reading the receive byte registers, receive register high (RXH), receive register middle (RXM), or receive register low (RXL), the host interface programmer should use interrupts or poll the receive register data full (RXDF) flag that indicates whether data is available. This ensures that the data in the receive byte registers will be valid.
• Overwriting Transmit Byte Registers—The host interface programmer should not write to the transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit register low (TXL), unless the transmit register data empty (TXDE) bit is set, indicating that the transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid data to the host receive (HRX) register.
• Synchronization of Status Bits from DSP to Host—HC, HOREQ , DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor (refer to the user’s manual for descriptions of these status bits). The host can read these status bits very quickly without regard to the clock rate used by the DSP, but the state of the bit could be changing during the read operation. This is not generally a system problem, because the bit will be read correctly in the next pass of any host polling routine. However, if the host asserts HEN for more than timing number 31, with a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

4-6 DSP56362 Advance Information MOTOROLA Design Considerations Host Port Considerations stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the host could read the wrong combination. Therefore, read the bits twice and check for consensus.

• Overwriting the Host Vector—The host interface programmer should change the host vector (HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt control logic will receive a stable vector.
• Cancelling a Pending Host Command Exception—The host processor may elect to clear the HC bit to cancel the host command exception request at any time before it is recognized by the DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the host command exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time that the HC bit is cleared.
• Variance in the Host Interface Timing—The host interface (HDI) may vary (e.g. due to the PLL lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HOREQ pin). DSP Programming Considerations
• Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)
• Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when reading status bits HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 5-1 SECTION 5

ORDERING INFORMATION

Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. For information on ordering this and all DSP Audio products, review the SG1004 selector guide at http://e- www.motorola.com/files/shared/doc/selector_guide/SG1004.pdf. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix A-1 APPENDIX A POWER CONSUMPTION BENCHMARK The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation. ;* ;* CHECKS Typical Power Consumption page 200,55,0,0,0 nolist I_VEC EQU $000000 ; Interrupt vectors for program debug only START EQU $8000 ; MAIN (external) program starting address INT_PROG EQU $100 ; INTERNAL program memory starting address INT_XDAT EQU $0 ; INTERNAL X-data memory starting address INT_YDAT EQU $0 ; INTERNAL Y-data memory starting address INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org P:START m o v e p# $ 0 1 2 3 F F , x : M _ B C R ;B C R :A r e a3:1w . s( S R A M ) ; Default: 1 w.s (SRAM) movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; Load the program move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; Load the X-data move #INT_XDAT,r0 move #XDAT_START,r1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix A-2 DSP56362 Advance Information MOTOROLA Power Consumption Benchmark do #(XDAT_END-XDAT_START),XLOAD_LOOP move p:(r1)+,x0 move x0,x:(r0)+ XLOAD_LOOP ; Load the Y-data move #INT_YDAT,r0 move #YDAT_START,r1 do #(YDAT_END-YDAT_START),YLOAD_LOOP move p:(r1)+,x0 move x0,y:(r0)+ YLOAD_LOOP jmp INT_PROG PROG_START move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 clr a clr b move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 bset #4,omr ; ebd sbr dor #60,_end mac x0,y0,a x:(r0)+,x1 y:(r4)+,y1 mac x1,y1,a x:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,a x:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end bra sbr nop nop nop nop PROG_END nop nop XDAT_START ;o r g x : 0 dc $262EB9 dc $86F2FE dc $E56A5F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Power Consumption Benchmark MOTOROLA DSP56362 Advance Information Appendix A-3 dc $616CAC dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 dc $6C6657 dc $C2A544 dc $A3662D dc $A4E762 dc $84F0F3 dc $E6F1B0 dc $B3829 dc $8BF7AE dc $63A94F dc $EF78DC dc $242DE5 dc $A3E0BA dc $EBAB6B dc $8726C8 dc $CA361 dc $2F6E86 dc $A57347 dc $4BE774 dc $8F349D dc $A1ED12 dc $4BFCE3 dc $EA26E0 dc $CD7D99 dc $4BA85E dc $27A43F dc $A8B10C dc $D3A55 dc $25EC6A dc $2A255B dc $A5F1F8 dc $2426D1 dc $AE6536 dc $CBBC37 dc $6235A4 dc $37F0D dc $63BEC2 dc $A5E4D3 dc $8CE810 dc $3FF09 dc $60E50E dc $CFFB2F dc $40753C dc $8262C5 dc $CA641A dc $EB3B4B dc $2DA928 dc $AB6641 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix A-4 DSP56362 Advance Information MOTOROLA Power Consumption Benchmark dc $28A7E6 dc $4E2127 dc $482FD4 dc $7257D dc $E53C72 dc $1A8C3 dc $E27540 XDAT_END YDAT_START ;o r g y : 0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc $24233D dc $802732 dc $2E3C83 dc $A43E00 dc $C2B639 dc $85A47E dc $ABFDDF dc $F3A2C dc $2D7CF5 dc $E16A8A dc $ECB8FB dc $4BED18 dc $43F371 dc $83A556 dc $E1E9D7 dc $ACA2C4 dc $8135AD dc $2CE0E2 dc $8F2C73 dc $432730 dc $A87FA9 dc $4A292E dc $A63CCF dc $6BA65C dc $E06D65 dc $1AA3A dc $A1B6EB dc $48AC48 dc $EF7AE1 dc $6E3006 dc $62F6C7 dc $6064F4 dc $87E41D dc $CB2692 dc $2C3863 dc $C6BC60 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Power Consumption Benchmark MOTOROLA DSP56362 Advance Information Appendix A-5 dc $43A519 dc $6139DE dc $ADF7BF dc $4B3E8C dc $6079D5 dc $E0F5EA dc $8230DB dc $A3B778 dc $2BFE51 dc $E0A6B6 dc $68FFB7 dc $28F324 dc $8F2E8D dc $667842 dc $83E053 dc $A1FD90 dc $6B2689 dc $85B68E dc $622EAF dc $6162BC dc $E4A245 YDAT_END Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-1 APPENDIX B IBIS MODEL [IBIS ver] 2.1 [File name] 56362.ibs [File Rev] 0.0 [Date] 29/6/2000 [Component] 56362 [Manufacturer] Motorola [Package] |variable typ min max R_pkg 45m 22m 75m L_pkg 2.5nH 1.1nH 4.3nH C_pkg 1.3pF 1.2pF 1.4pF [Pin]signal_name model_name 1 sck ip5b_io 2 ss_ ip5b_io 3 hreq_ ip5b_io 4 sdo0 ip5b_io 5 sdo1 ip5b_io 6 sdoi23 ip5b_io 7 sdoi32 ip5b_io 8 svcc power 9s g n d g n d 10 sdoi41 ip5b_io 11 sdoi50 ip5b_io 12 fst ip5b_io 13 fsr ip5b_io 14 sckt ip5b_io 15 sckr ip5b_io 16 hsckt ip5b_io 17 hsckr ip5b_io 18 qvccl power 19 gnd gnd 20 qvcch power 21 hp12 ip5b_io 22 hp11 ip5b_io 23 hp15 ip5b_io 24 hp14 ip5b_io 25 svcc power 26 sgnd gnd 27 ado ip5b_io 28 aci ip5b_io 29 tio ip5b_io 30 hp13 ip5b_io 31 hp10 ip5b_io 32 hp9 ip5b_io 33 hp8 ip5b_io Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-2 DSP56362 Advance Information MOTOROLA 34 hp7 ip5b_io 35 hp6 ip5b_io 36 hp5 ip5b_io 37 hp4 ip5b_io 38 svcc power 39 sgnd gnd 40 hp3 ip5b_io 41 hp2 ip5b_io 42 hp1 ip5b_io 43 hp0 ip5b_io 44 ires_ ip5b_i 45 pvcc power 46 pcap power 47 pgnd gnd 48 pgnd1 gnd 49 qvcch power 50 aa3 icbc_o 51 aa2 icbc_o 52 cas_ icbc_o 53 de_ ipbw_io 54 qgnd gnd 55 cxtldis_ iexlh_i 56 qvccl power 57 cvcc power 58 cgnd gnd 59 clkout icba_o 61 nmi_ ipbw_i 62 ta_ icbc_o 63 br_ icbc_o 64 bb_ icbc_o 65 cvcc power 66 cgnd gnd 67 wr_ icbc_o 68 rd_ icbc_o 69 aa1 icbc_o 70 aa0 icbc_o 71 bg_ icbc_o 72 eab0 icba_o 73 eab1 icba_o 74 avcc power 75 agnd gnd 76 eab2 icba_o 77 eab3 icba_o 78 eab4 icba_o 79 eab5 icba_o 80 avcc power 81 agnd gnd 82 eab6 icba_o 83 eab7 icba_o 84 eab8 icba_o 85 eab9 icba_o 86 avcc power 87 agnd gnd 88 eab10 icba_o Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-3 89 eab11 icba_o 90 qgnd gnd 91 qvcc power 92 eab12 icba_o 93 eab13 icba_o 94 eab14 icba_o 95 qvcch power 96 agnd gnd 97 eab15 icba_o 98 eab16 icba_o 99 eab17 icba_o 100 edb0 icba_io 101 edb1 icba_io 102 edb2 icba_io 103 dvcc power 104 dgnd gnd 105 edb3 icba_io 106 edb4 icba_io 107 edb5 icba_io 108 edb6 icba_io 109 edb7 icba_io 110 edb8 icba_io 111 dvcc power 112 dgnd gnd 113 edb9 icba_io 114 edb10 icba_io 115 edb11 icba_io 116 edb12 icba_io 117 edb13 icba_io 118 edb14 icba_io 119 dvcc power 120 dgnd gnd 121 edb15 icba_io 122 edb16 icba_io 123 edb17 icba_io 124 edb18 icba_io 125 edb19 icba_io 126 qvccl power 127 qgnd gnd 128 edb20 icba_io 129 dvcc power 130 dgnd gnd 131 edb21 icba_io 132 edb22 icba_io 133 edb23 icba_io 134 irqd_ ip5b_i 135 irqc_ ip5b_i 136 irqb_ ip5b_i 137 irqa_ ip5b_i 138 trst_ ip5b_i 139 tdo ip5b_o 140 tdi ip5b_i 141 tck ip5b_i 142 tms ip5b_i Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-4 DSP56362 Advance Information MOTOROLA 143 mosi ip5b_io 144 sda ip5b_io [Model] ip5b_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) [Model] ip5b_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-5 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02 1.500e+00 4.779e-02 2.709e-02 6.023e-02 1.700e+00 4.935e-02 2.803e-02 6.271e-02 1.900e+00 5.013e-02 2.851e-02 6.419e-02 2.100e+00 5.046e-02 2.876e-02 6.494e-02 2.300e+00 5.063e-02 2.892e-02 6.525e-02 2.500e+00 5.075e-02 2.904e-02 6.540e-02 2.700e+00 5.085e-02 2.912e-02 6.549e-02 2.900e+00 5.090e-02 2.876e-02 6.555e-02 3.100e+00 4.771e-02 2.994e-02 6.561e-02 3.300e+00 4.525e-02 3.321e-02 6.182e-02 3.500e+00 4.657e-02 3.570e-02 6.049e-02 3.700e+00 4.904e-02 3.801e-02 6.178e-02 3.900e+00 5.221e-02 4.029e-02 6.450e-02 4.100e+00 5.524e-02 4.253e-02 6.659e-02 4.300e+00 5.634e-02 4.463e-02 6.867e-02 4.500e+00 5.751e-02 4.645e-02 6.970e-02 4.700e+00 5.634e-02 4.786e-02 6.938e-02 4.900e+00 5.648e-02 4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02 6.500e+00 5.801e-02 4.733e-02 7.205e-02 6.600e+00 5.824e-02 4.737e-02 7.242e-02 [Pullup] |voltage I(typ) I(min) I(max) -3.30e+00 2.922e-04 2.177e-04 4.123e-04 -3.10e+00 2.881e-04 2.175e-04 4.021e-04 -2.90e+00 2.853e-04 2.173e-04 3.946e-04 -2.70e+00 2.836e-04 2.172e-04 3.893e-04 -2.50e+00 2.825e-04 2.171e-04 3.857e-04 -2.30e+00 2.819e-04 2.170e-04 3.834e-04 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-6 DSP56362 Advance Information MOTOROLA -2.10e+00 2.815e-04 2.169e-04 3.820e-04 -1.90e+00 2.813e-04 2.167e-04 3.812e-04 -1.70e+00 2.812e-04 2.520e-04 3.808e-04 -1.50e+00 2.811e-04 3.078e-02 3.806e-04 -1.30e+00 2.810e-04 2.684e-02 3.804e-04 -1.10e+00 2.809e-04 2.277e-02 3.802e-04 -9.00e-01 2.808e-04 1.864e-02 3.801e-04 -7.00e-01 2.997e-04 1.447e-02 3.799e-04 -5.00e-01 1.750e-02 1.031e-02 3.797e-04 -3.00e-01 1.048e-02 6.181e-03 3.776e-04 -1.00e-01 3.487e-03 2.084e-03 4.568e-03 [GND_clamp] |voltage I(typ) I(min) I(max) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-7 [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) [Model] ip5b_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-8 DSP56362 Advance Information MOTOROLA 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02 1.500e+00 4.779e-02 2.709e-02 6.023e-02 1.700e+00 4.935e-02 2.803e-02 6.271e-02 1.900e+00 5.013e-02 2.851e-02 6.419e-02 2.100e+00 5.046e-02 2.876e-02 6.494e-02 2.300e+00 5.063e-02 2.892e-02 6.525e-02 2.500e+00 5.075e-02 2.904e-02 6.540e-02 2.700e+00 5.085e-02 2.912e-02 6.549e-02 2.900e+00 5.090e-02 2.876e-02 6.555e-02 3.100e+00 4.771e-02 2.994e-02 6.561e-02 3.300e+00 4.525e-02 3.321e-02 6.182e-02 3.500e+00 4.657e-02 3.570e-02 6.049e-02 3.700e+00 4.904e-02 3.801e-02 6.178e-02 3.900e+00 5.221e-02 4.029e-02 6.450e-02 4.100e+00 5.524e-02 4.253e-02 6.659e-02 4.300e+00 5.634e-02 4.463e-02 6.867e-02 4.500e+00 5.751e-02 4.645e-02 6.970e-02 4.700e+00 5.634e-02 4.786e-02 6.938e-02 4.900e+00 5.648e-02 4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02 6.500e+00 5.801e-02 4.733e-02 7.205e-02 6.600e+00 5.824e-02 4.737e-02 7.242e-02 [Pullup] |voltage I(typ) I(min) I(max) -3.30e+00 2.922e-04 2.177e-04 4.123e-04 -3.10e+00 2.881e-04 2.175e-04 4.021e-04 -2.90e+00 2.853e-04 2.173e-04 3.946e-04 -2.70e+00 2.836e-04 2.172e-04 3.893e-04 -2.50e+00 2.825e-04 2.171e-04 3.857e-04 -2.30e+00 2.819e-04 2.170e-04 3.834e-04 -2.10e+00 2.815e-04 2.169e-04 3.820e-04 -1.90e+00 2.813e-04 2.167e-04 3.812e-04 -1.70e+00 2.812e-04 2.520e-04 3.808e-04 -1.50e+00 2.811e-04 3.078e-02 3.806e-04 -1.30e+00 2.810e-04 2.684e-02 3.804e-04 -1.10e+00 2.809e-04 2.277e-02 3.802e-04 -9.00e-01 2.808e-04 1.864e-02 3.801e-04 -7.00e-01 2.997e-04 1.447e-02 3.799e-04 -5.00e-01 1.750e-02 1.031e-02 3.797e-04 -3.00e-01 1.048e-02 6.181e-03 3.776e-04 -1.00e-01 3.487e-03 2.084e-03 4.568e-03 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-9 [GND_clamp] |voltage I(typ) I(min) I(max) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-10 DSP56362 Advance Information MOTOROLA [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) [Model] icba_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 1.299e-01 6.458e-02 2.331e-02 1.700e+00 1.366e-01 6.746e-02 1.755e-01 1.900e+00 1.404e-01 6.916e-02 1.847e-01 2.100e+00 1.423e-01 7.006e-02 1.907e-01 2.300e+00 1.433e-01 7.059e-02 1.940e-01 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-11 2.500e+00 1.440e-01 7.098e-02 1.958e-01 2.700e+00 1.445e-01 7.128e-02 1.970e-01 2.900e+00 1.450e-01 7.154e-02 1.979e-01 3.100e+00 1.454e-01 7.176e-02 1.986e-01 3.300e+00 1.458e-01 7.196e-02 1.993e-01 3.500e+00 1.461e-01 7.223e-02 1.999e-01 3.700e+00 1.464e-01 8.810e-02 2.004e-01 3.900e+00 1.469e-01 2.589e+00 2.009e-01 4.100e+00 1.490e-01 1.451e+01 2.015e-01 4.300e+00 1.501e+00 2.658e+01 2.030e-01 4.500e+00 1.813e+01 3.866e+01 2.385e-01 4.700e+00 3.540e+01 5.076e+01 9.563e+00 4.900e+00 5.269e+01 6.461e+01 2.682e+01 5.100e+00 7.541e+01 8.261e+01 4.409e+01 5.300e+00 1.012e+02 1.006e+02 6.258e+01 5.500e+00 1.270e+02 1.186e+02 8.836e+01 5.700e+00 1.527e+02 1.366e+02 1.141e+02 5.900e+00 1.785e+02 1.546e+02 1.399e+02 6.100e+00 2.043e+02 1.726e+02 1.657e+02 6.300e+00 2.301e+02 1.906e+02 1.915e+02 6.500e+00 2.559e+02 2.086e+02 2.173e+02 6.600e+00 2.688e+02 2.176e+02 2.302e+02 [Pullup] |voltage I(typ) I(min) I(max) -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.237e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.360e+00 1.444e+01 9.362e+00 -9.00e-01 4.275e-02 2.518e+00 4.663e-02 -7.00e-01 8.208e-03 2.012e-02 1.070e-02 -5.00e-01 5.635e-03 3.518e-03 7.068e-03 -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-12 DSP56362 Advance Information MOTOROLA [GND_clamp] |voltage I(typ) I(min) I(max) [POWER_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-13 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) [Model] icba_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-14 DSP56362 Advance Information MOTOROLA 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 1.299e-01 6.458e-02 2.331e-02 1.700e+00 1.366e-01 6.746e-02 1.755e-01 1.900e+00 1.404e-01 6.916e-02 1.847e-01 2.100e+00 1.423e-01 7.006e-02 1.907e-01 2.300e+00 1.433e-01 7.059e-02 1.940e-01 2.500e+00 1.440e-01 7.098e-02 1.958e-01 2.700e+00 1.445e-01 7.128e-02 1.970e-01 2.900e+00 1.450e-01 7.154e-02 1.979e-01 3.100e+00 1.454e-01 7.176e-02 1.986e-01 3.300e+00 1.458e-01 7.196e-02 1.993e-01 3.500e+00 1.461e-01 7.223e-02 1.999e-01 3.700e+00 1.464e-01 8.810e-02 2.004e-01 3.900e+00 1.469e-01 2.589e+00 2.009e-01 4.100e+00 1.490e-01 1.451e+01 2.015e-01 4.300e+00 1.501e+00 2.658e+01 2.030e-01 4.500e+00 1.813e+01 3.866e+01 2.385e-01 4.700e+00 3.540e+01 5.076e+01 9.563e+00 4.900e+00 5.269e+01 6.461e+01 2.682e+01 5.100e+00 7.541e+01 8.261e+01 4.409e+01 5.300e+00 1.012e+02 1.006e+02 6.258e+01 5.500e+00 1.270e+02 1.186e+02 8.836e+01 5.700e+00 1.527e+02 1.366e+02 1.141e+02 5.900e+00 1.785e+02 1.546e+02 1.399e+02 6.100e+00 2.043e+02 1.726e+02 1.657e+02 6.300e+00 2.301e+02 1.906e+02 1.915e+02 6.500e+00 2.559e+02 2.086e+02 2.173e+02 6.600e+00 2.688e+02 2.176e+02 2.302e+02 [Pullup] |voltage I(typ) I(min) I(max) -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.237e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.360e+00 1.444e+01 9.362e+00 -9.00e-01 4.275e-02 2.518e+00 4.663e-02 -7.00e-01 8.208e-03 2.012e-02 1.070e-02 -5.00e-01 5.635e-03 3.518e-03 7.068e-03 -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-15 [GND_clamp] |voltage I(typ) I(min) I(max) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-16 DSP56362 Advance Information MOTOROLA [POWER_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) [Model] icbc_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-17 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 9.632e-02 4.783e-02 2.331e-02 1.700e+00 1.012e-01 4.994e-02 1.302e-01 1.900e+00 1.039e-01 5.118e-02 1.369e-01 2.100e+00 1.053e-01 5.184e-02 1.412e-01 2.300e+00 1.060e-01 5.223e-02 1.436e-01 2.500e+00 1.065e-01 5.251e-02 1.449e-01 2.700e+00 1.069e-01 5.274e-02 1.458e-01 2.900e+00 1.073e-01 5.293e-02 1.464e-01 3.100e+00 1.076e-01 5.309e-02 1.470e-01 3.300e+00 1.078e-01 5.324e-02 1.475e-01 3.500e+00 1.081e-01 5.344e-02 1.479e-01 3.700e+00 1.083e-01 6.705e-02 1.483e-01 3.900e+00 1.086e-01 2.529e+00 1.487e-01 4.100e+00 1.103e-01 1.438e+01 1.491e-01 4.300e+00 1.437e+00 2.638e+01 1.503e-01 4.500e+00 1.800e+01 3.839e+01 1.810e-01 4.700e+00 3.519e+01 5.041e+01 9.452e+00 4.900e+00 5.241e+01 6.419e+01 2.664e+01 5.100e+00 7.505e+01 8.210e+01 4.384e+01 5.300e+00 1.007e+02 1.000e+02 6.224e+01 5.500e+00 1.264e+02 1.179e+02 8.794e+01 5.700e+00 1.522e+02 1.359e+02 1.136e+02 5.900e+00 1.779e+02 1.538e+02 1.394e+02 6.100e+00 2.036e+02 1.717e+02 1.651e+02 6.300e+00 2.293e+02 1.896e+02 1.908e+02 6.500e+00 2.550e+02 2.075e+02 2.165e+02 6.600e+00 2.678e+02 2.165e+02 2.293e+02 [Pullup] |voltage I(typ) I(min) I(max) -3.30e+00 2.677e+02 1.896e+02 2.677e+02 -3.10e+00 2.420e+02 1.716e+02 2.420e+02 -2.90e+00 2.163e+02 1.537e+02 2.163e+02 -2.70e+00 1.906e+02 1.358e+02 1.906e+02 -2.50e+00 1.649e+02 1.179e+02 1.649e+02 -2.30e+00 1.392e+02 9.996e+01 1.392e+02 -2.10e+00 1.135e+02 8.205e+01 1.135e+02 -1.90e+00 8.778e+01 6.413e+01 8.778e+01 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-18 DSP56362 Advance Information MOTOROLA -1.70e+00 6.208e+01 5.035e+01 6.208e+01 -1.50e+00 4.368e+01 3.834e+01 4.368e+01 -1.30e+00 2.649e+01 2.633e+01 2.649e+01 -1.10e+00 9.302e+00 1.433e+01 9.303e+00 -9.00e-01 3.838e-02 2.477e+00 4.183e-02 -7.00e-01 8.115e-03 1.789e-02 1.045e-02 -5.00e-01 5.634e-03 3.503e-03 7.064e-03 -3.00e-01 3.370e-03 2.053e-03 4.233e-03 -1.00e-01 1.118e-03 6.789e-04 1.410e-03 [GND_clamp] |voltage I(typ) I(min) I(max) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-19 [POWER_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 2.677e+02 1.896e+02 2.677e+02 -3.10e+00 2.420e+02 1.716e+02 2.420e+02 -2.90e+00 2.163e+02 1.537e+02 2.163e+02 -2.70e+00 1.906e+02 1.358e+02 1.906e+02 -2.50e+00 1.649e+02 1.179e+02 1.649e+02 -2.30e+00 1.392e+02 9.996e+01 1.392e+02 -2.10e+00 1.135e+02 8.205e+01 1.135e+02 -1.90e+00 8.778e+01 6.413e+01 8.778e+01 -1.70e+00 6.208e+01 5.035e+01 6.208e+01 -1.50e+00 4.368e+01 3.834e+01 4.368e+01 -1.30e+00 2.649e+01 2.633e+01 2.649e+01 -1.10e+00 9.300e+00 1.433e+01 9.301e+00 -9.00e-01 2.962e-02 2.475e+00 3.075e-02 -7.00e-01 2.501e-04 1.354e-02 6.708e-04 -5.00e-01 2.066e-06 6.280e-05 1.204e-05 -3.00e-01 2.487e-09 5.128e-07 1.417e-08 -1.00e-01 5.672e-11 5.639e-09 6.832e-11 0.000e+00 5.334e-11 1.992e-09 5.783e-11 [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) [Model] ipbw_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-20 DSP56362 Advance Information MOTOROLA [GND_clamp] |voltage I(typ) I(min) I(max) [POWER_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 [Model] ipbw_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-21 [Pulldown] |voltage I(typ) I(min) I(max) 1.000e-01 3.729e-03 1.940e-03 4.177e-03 3.000e-01 1.076e-02 5.578e-03 1.216e-02 5.000e-01 1.723e-02 8.907e-03 1.965e-02 7.000e-01 2.311e-02 1.191e-02 2.663e-02 9.000e-01 2.836e-02 1.455e-02 3.305e-02 1.100e+00 3.292e-02 1.680e-02 3.887e-02 1.300e+00 3.675e-02 1.862e-02 4.404e-02 1.500e+00 3.979e-02 1.997e-02 4.850e-02 1.700e+00 4.205e-02 2.085e-02 5.223e-02 1.900e+00 4.347e-02 2.136e-02 5.518e-02 2.100e+00 4.413e-02 2.162e-02 5.728e-02 2.300e+00 4.445e-02 2.176e-02 5.843e-02 2.500e+00 4.465e-02 2.186e-02 5.899e-02 2.700e+00 4.479e-02 2.194e-02 5.931e-02 2.900e+00 4.492e-02 2.200e-02 5.953e-02 3.100e+00 4.502e-02 2.206e-02 5.971e-02 3.300e+00 4.511e-02 2.211e-02 5.986e-02 3.500e+00 4.519e-02 2.219e-02 5.999e-02 3.700e+00 4.526e-02 3.324e-02 6.010e-02 3.900e+00 4.536e-02 2.452e+00 6.021e-02 4.100e+00 4.614e-02 1.423e+01 6.032e-02 4.300e+00 1.344e+00 2.615e+01 6.065e-02 4.500e+00 1.783e+01 3.808e+01 8.548e-02 4.700e+00 3.495e+01 5.001e+01 9.298e+00 4.900e+00 5.208e+01 6.371e+01 2.640e+01 5.100e+00 7.463e+01 8.154e+01 4.352e+01 5.300e+00 1.002e+02 9.937e+01 6.184e+01 5.500e+00 1.259e+02 1.172e+02 8.745e+01 5.700e+00 1.515e+02 1.350e+02 1.131e+02 5.900e+00 1.771e+02 1.529e+02 1.387e+02 6.100e+00 2.027e+02 1.707e+02 1.643e+02 6.300e+00 2.283e+02 1.885e+02 1.899e+02 6.500e+00 2.539e+02 2.064e+02 2.155e+02 6.600e+00 2.667e+02 2.153e+02 2.283e+02 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-22 DSP56362 Advance Information MOTOROLA [Pullup] |voltage I(typ) I(min) I(max) -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.635e+01 2.613e+01 2.635e+01 -1.10e+00 9.243e+00 1.421e+01 9.245e+00 -9.00e-01 5.536e-02 2.435e+00 6.260e-02 -7.00e-01 2.847e-02 2.689e-02 3.437e-02 -5.00e-01 2.025e-02 1.265e-02 2.451e-02 -3.00e-01 1.208e-02 7.503e-03 1.467e-02 -1.00e-01 3.994e-03 2.474e-03 4.868e-03 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information Appendix B-23 [GND_clamp] |voltage I(typ) I(min) I(max) [POWER_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix B-24 DSP56362 Advance Information MOTOROLA [Model] iexlh_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) [POWER_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 2.653e+02 1.870e+02 2.653e+02 -3.10e+00 2.398e+02 1.693e+02 2.398e+02 -2.90e+00 2.143e+02 1.516e+02 2.143e+02 -2.70e+00 1.888e+02 1.339e+02 1.888e+02 -2.50e+00 1.633e+02 1.162e+02 1.633e+02 -2.30e+00 1.378e+02 9.847e+01 1.378e+02 -2.10e+00 1.123e+02 8.076e+01 1.123e+02 -1.90e+00 8.682e+01 6.305e+01 8.682e+01 -1.70e+00 6.133e+01 4.947e+01 6.133e+01 -1.50e+00 4.313e+01 3.766e+01 4.313e+01 -1.30e+00 2.614e+01 2.585e+01 2.614e+01 -1.10e+00 9.145e+00 1.404e+01 9.145e+00 -9.00e-01 1.797e-02 2.364e+00 1.797e-02 -7.00e-01 3.667e-06 7.589e-03 3.667e-06 -5.00e-01 7.730e-10 2.072e-05 7.748e-10 -3.00e-01 2.293e-11 5.767e-08 2.476e-11 -1.00e-01 2.096e-11 1.163e-09 2.278e-11 0.000e+00 2.004e-11 9.618e-10 2.186e-11 [End] Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 1 INDEX A ac electrical characteristics 2-4 Address Trace mode iv, 2-44, 2-47 ALU iii applications v arbitration bus timings 2-47 Arithmetic Logic Unit iii B benchmark test algorithm A-1, B-1 bootstrap ROM iv Boundary Scan (JTAG Port) timing diagram 2- bus address 1-2 data 1-2 multiplexed 1-2 non-multiplexed 1-2 bus acquisition timings 2-48 bus release timings 2-49, 2-50 C case outline drawing 3-8 clock external 2-5 operation 2-6 clocks internal 2-5 D Data Arithmetic Logic Unit iii data memory expansion iv DAX iv, 1-2, 1-19 dc electrical characteristics 2-3 Debug support iv description, general i design considerations electrical 4-3 PLL 4-5, 4-6 power consumption 4-4 thermal 4-1 Digital Audio Transmitter iv, 1-19 Direct Memory Access iii DMA iii DRAM out of page read access 2-41 wait states selection guide 2-33 write access 2-42 out of page and refresh timings 11 wait states 2-37 15 wait states 2-39 4 wait states 2-33 8 wait states 2-36 Page mode read accesses 2-32 wait states selection guide 2-22 write accesses 2-31 Page mode timings 1 wait state 2-23 2 wait states 2-24 3 wait states 2-27 4 wait states 2-29 refresh access 2-43 DRAM controller iv DSP programming 4-8 DSP56300 core features iii DSP56362 features iii specifications 2-1 E electrical design considerations 4-3 Enhanced Serial Audio Interface iv ESAI iv, 1-2 ESSI receiver timing 2-75, 2-76 timings 2-71 transmitter timing 2-74 EXTAL jitter 4-6 external bus control 1-7, 1-8 external bus synchronous timings (SRAM access) 2-44 external clock operation 2-5 external interrupt timing (negative edge- triggered) 2-15 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

external level-sensitive fast interrupt timing 2-15 external memory access (DMA Source) timing 2- External Memory Expansion Port 2-18 F functional groups 1-2 functional signal groups 1-1 G general description i General Purpose Input/Output iv GPIO iv, 1-2, 1-25 GPIO timing 2-80 Ground 1-4 PLL 1-4 H DSP programming 4-8 DSP synchronization 4-8 Host synchronization 4-6 HDI08 timing 2-52 Host Interface iv, 1-2, 1-11, 1-12, 1-14, 1-15 Host Interface timing 2-52 host port configuration 1-11 Host Port considerations 4-6 Host programming 4-6 Host Request Double 1-2 Single 1-2 I instruction cache iv internal clocks 2-5 interrupt and mode control 1-9 interrupt control 1-9 interrupt timing 2-9 external level-sensitive fast 2-15 external negative edge-triggered 2-15 synchronous from Wait state 2-16 J Jitter 4-6 JTAG 1-25 JTAG Port iv reset timing diagram 2-84 timing 2-82, 2-83 M maximum ratings 2-1, 2-2 mechanical drawings 3-8 Memory Expansion Port iv Mfax system 3-8 mode control 1-9 Mode select timing 2-9 multiplexed bus 1-2 multiplexed bus timings read 2-57 write 2-58 N non-multiplexed bus 1-2 non-multiplexed bus timings read 2-55 write 2-56 O off-chip memory iv OnCE module timing 2-85 OnCE module iv, 1-25 Debug request 2-85 on-chip DRAM controller iv On-Chip Emulation module iv on-chip memory iv operating mode select timing 2-16 ordering drawings 3-8 ordering information 5-1 P package 144-pin TQFP 3-1 TQFP description 3-2, 3-3 PCU iii Phase Lock Loop iii, 2-8 PLL iii, 2-8 Characteristics 2-8 performance issues 4-5 PLL design considerations 4-5, 4-6 PLL performance issues 4-6 Port A 1-2 Port C 1-2, 1-19 Port D 1-2, 1-19 power consumption benchmark test A-1, B-1 power consumption design considerations 4-4 power management v Program Control Unit iii Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA DSP56362 Advance Information 3 program memory expansion iv program RAM iv R recovery from Stop state using IRQA 2-16, 2-17 RESET 1-10 Reset timing 2-9, 2-14 synchronous 2-14 ROM, bootstrap iv S Serial Host Interface iv, 1-16 SHI iv, 1-2, 1-16 signal groupings 1-1 signals 1-1 functional grouping 1-2 SRAM 2-45 Access 2-44 read access 2-21 read and write accesses 2-18 support iv write access 2-21 Stop mode v Stop state recovery from 2-16, 2-17 Stop timing 2-9 supply voltage 2-2 Switch mode iv Synchronization 4-6 synchronous bus timings SRAM 2 wait states 2-46 SRAM 1 wait state (BCR controlled) 2-45 synchronous interrupt from Wait state timing 2- synchronous Reset timing 2-14 T TAP iv target applications v Test Access Port iv Test Access Port timing diagram 2-84 Test Clock (TCLK) input timing diagram 2-83 thermal characteristics 2-2 thermal design considerations 4-1 Timer iv, 1-2, 1-25 event input restrictions 2-78 interrupt generation 2-79 timing 2-78 Timing Digital Audio Transmitter (DAX) 2-77 Enhanced Serial Audio Interface (ESAI) 2- General Purpose I/O (GPIO) Timing 2-71 OnCE™ (On Chip Emulator) Timing 2-71 Serial Host Interface (SHI) SPI Protocol Timing 2-60 Serial Host Interface (SHI) Timing 2-60 timing interrupt 2-9 mode select 2-9 Reset 2-9 Stop 2-9 TQFP 3-1 pin list by number 3-3 pin-out drawing (top) 3-2 TQFP package drawing 3-8 W Wait mode v X X data RAM iv Y Y data RAM iv Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P .O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre

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Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors DSP56362/D Rev. 3 Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. © Motorola Inc. 2004 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...