AN-291 AD | Alldatasheet
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| ANALOG AN-291 ONE TECHNOLOGY WAY e P.O. BOX 9106 e NORWOOD, MASSACHUSETTS 02062-9106 @ 617/329-4700 Asynchronous Clock Interfacing with the AD7878 3 | by John Reidy The AD7878 is a fast, complete, 12-bit A/D converter with sion of the microprocessor clock out. As mentioned pre- a versatile DSP interface consisting of an 8-word, first-in, viously, CS and DMRD must not go low near a rising first-out (FIFO) memory and associated control logic. AD7878 CLK IN edge. Also, when writing to the device, The FIFO memory allows up to eight samples to be the internal latch signal is the overlap between the CLK digitized before the microprocessor is required to ser- IN low signal and the CS and DMWR signals (see data vice the A/D converter. An on-chip status/control register sheet, page 7). To satisfy the above restrictions, the allows the user to program the effective length of the relative phase of the microprocessor CLK OUT signal FIFO and contains the FIFO out of range, FIFO empty and and the memory control signals (CS, DMRD and DMWR) FIFO word count information. must be correct for synchronous operation. For example
5 A * the ADSP-2100 CLK OUT can drive the AD7878 CLK IN
Due to the complexity of the AD7878 internal logic, there directly; whereas, the TMS32010/32020 CLK OUT must are timing constraints which must be adhered to when be inverted before being applied to the AD7878. performing read/write operations to the device. One 19 APP ~ method of abiding by these constraints is to use syn- A leading issue with synchronous interfacing is the pro- chronous clock interfacing as recommended in the cur- cessor CLK OUT frequency: frequencies greater than rent data sheet. However, such interfacing is not suitable 8 MHz make synchronous interfacing impossible, e.g., for every microprocessor. Another disadvantage is a ADSP-2100A and the TMS320C25 when operated at their possible reduction in throughput rate depending on the maximum speed. Frequencies less than 8 MHz reduce microprocessor clock frequency. This application note the ADC’s maximum throughput rate, examples of these discusses the AD7878 timing constraints and shows an are the TMS32010 and the TMS32020. Some processors alternative interfacing method that is suitable for any such as the DSP56000 do not have a CLK OUT. The microprocessor and will operate at any sampling fre- above issues can be avoided by using an alternative quency up to the maximum of 100 kHz. interfacing option as discussed below. The AD7878 is designed so that all internal logic opera- The second option is to “gate off” the ADC clock when tions are performed on a rising CLK IN edge, e.g., FIFO reading/writing to the ADC. The following constraints memory and contro! register updating and ALFL status apply when using this mode of interfacing: output updating occur on a rising CLK IN edge. A read 1. DMIRD cannot go low within 20 ns before a rising CLK operation, an activity which is controlled external to the IN edge or 5ns after a rising CLK IN edge, see device, must be initiated around a falling CLK IN edge. Figure 1. Initiating a read operation (i.e., taking CS and DMRD ae low) on or near the rising edge of a CLK IN signal may 2. When writing to the AD7878, the clock must be cause the device to clock itself into an idle state with the stopped in the low contiition. only method of recovery being to reset the device. 3. The clock must not be stopped during conversion or There are two schemes which ensure correct timing when CONVST is low. operation when interfacing to microprocessors: mel a ans 1, Synchronous clock operation. om \\_ FF V_[_ 2. Stopping the CLK IN input while reading/writing to Ft ea gre oa the device. 7 ‘ont wvely | es TI AM Synchronous clock operation is covered extensively in a the data sheet. Briefly, for synchronous clock operation us the ADC clock must be the same as or an inverted ver- Figure 1. DMRD Asynchronous Timing Constraint ANALOG-TO-DIGITAL CONVERTERS 3-13
. . + % allowed during conversion. Figure 2. Asynchronous Clock Interfacing with the «|