DSP201

DSP201 BURR-BROWN | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 19

Technical content

FEATURES

l ZERO-CHIP INTERFACE TO DSP ICs: AD, AT&T, MOTOROLA, TI l SINGLE CHANNEL: DSP201 l DUAL CHANNEL: DSP202 Two Serial Inputs or Cascade from Single 32-Bit Word l UPDATE RATE TO 500kHz l DYNAMIC SPECIFICATIONS: Signal/(Noise + Distortion) = 90dB; THD = –92dB l USER SELECTABLE 16-BIT OR 18-BIT DATA WORDS

DESCRIPTION

The DSP201 and DSP202 are high performance digi- tal-to-analog converters designed for simplicity of use with modern digital signal processing ICs. Both are complete with all interface logic for use directly with DSP ICs, and provide analog output voltages updated at up to 500kHz. The DSP201 offers a single complete voltage output channel, accepting either 16 bits or 18 bits of input data, and can be driven by 16-bit, 24-bit, or 32-bit serial ports. The DSP202 offers two complete voltage output channels, with either two separate input ports, or a mode to drive both output channels from a single 32-bit word. Both the DSP201 and DSP202 are packaged in stan- dard, low-cost 28-pin plastic DIP packages. Each is offered in two performance grades to match applica- tion requirements. Latch Enable Reset Select Sync Format Select Word Length (16/18) Channel A Data In Sync Bit Clock Channel B Data In Cascade Control Logic Convert Command 18-Bit DAC 18-Bit DAC Reference Channel B on DSP202 Only Analog Voltage Output Channel A Analog Voltage Output Channel B International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 DSP-Compatible Single/Dual DIGITAL-TO-ANALOG CONVERTERS © 1991 Burr-Brown Corporation PDS-1067C Printed in U.S.A. July, 1993

TA = 0°C to 70°C, Output Update Frequency, fS, = 400kHz, VA+ = VD + = +5V, VA– = VD – = –5V, unless otherwise specified. DSP201JP DSP201KP DSP202JP DSP202KP PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 18 * Bits DYNAMIC RANGE 108 * dB ANALOG OUTPUT Voltage Range R L = 375Ω± 3* V Impedance 0.1 * Ω Current R L = 375Ω± 8* m A Slew Rate R L = 1.5kΩ , CL = 100pF 15 * V/ µs Settling Time to 0.006% R L = 1.5kΩ , CL = 100pF 2.5 * µs for Full-Scale Step THROUGHPUT SPEED (1) Update Rate CASC = LOW on DSP202 500 * kHz DSP202 in Cascade Mode CASC = HIGH 300 kHz AC ACCURACY (2, 3) Signal to (Noise + Distortion) Ratio fOUT = 1kHz 82 86 88 90 dB (4) fOUT = 1kHz (–60dB) 30 32 dB fOUT = 10kHz 80 86 86 90 dB Total Harmonic Distortion f OUT = 1kHz –90 –85 –92 –88 dB Channel Separation f OUT = 1kHz to 100kHz 105 * dB on DSP202 DC ACCURACY Integral Nonlinearity Error ±0.006 ±0.004 % Differential Nonlinearity Error ±0.006 ±0.004 % Bipolar Zero Error (5) ±10 * mV Bipolar Zero Error Drift 20 * ppm FSR/ °C Bipolar Zero Mismatch (5) DSP202 Channels 5 * mV Gain Error 13 * * % Gain Error Drift 100 * ppm/ °C Gain Error Mismatch DSP202 Channels 1 3 * * % Digital Feedthrough ENABLE = HIGH –105 * dB Power Supply Sensitivity –5.1 < V A–, VD – < –4.9 –60 * dB DIGITAL INPUTS Format Serial; MSB first; 16/18-bit and Cascaded Coding Binary Twos Complement Logic Levels VIL IIL = ±10µA 0 +0.8 * * V VIH IIH = ±10µA +2.4 +5 * * V Data Transfer Clock Frequency 12 * * MHz Duty Cycle 40 50 60 * * * % DIGITAL OUTPUTS VOL IOL = 4mA 0 +0.4 * * V VOH IOH = 4mA +2.4 +5 * * V POWER SUPPLIES Rated Voltage Current IA+ 18 * mA IA– 17 * mA ID + 13 * mA ID – 25 * mA Power Consumption 365 450 * * mW TEMPERATURE RANGE Specification 0 +70 * * oC Storage –40 +125 * * oC NOTES: (1) The data transfer clock must be at least 24 times the update rate for the standard mode, and 40 times the update rate in the DSP202 Cascade Mode. (2) All dynamic specifications are based on 2048-point FFTs. (3) Data for the 1kHz test is bandlimited to 0 to 20kHz. Data for the 10kHz test is bandlimited to 0 to 40kHz. (4) All specifications in dB are referred to a full-scale output, ±3Vp-p. (5) Adjustable to zero with external potentiometer.

BIPOLAR ZERO ERROR AND GAIN ERROR vs TEMPERATURE Ambient Temperature (°C) Bipolar Zero Error (mV) –10 –50 –25 0 25 50 75 100 Gain Error (% of 6V Full Scale Range) 0.3 0.2 0.1 –0.1 Gain Error Bipolar Zero Error INTEGRAL AND DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE (For Worst-Case Codes.) Ambient Temperature (°C) Absolute Value of Error (%) 0.020 0.015 0.010 0.005 0.0 –50 –25 0 25 50 75 100 Differential Non-Linearity Integral Non-Linearity SIGNAL-TO-(NOISE + DISTORTION) vs OUTPUT UPDATE RATE Output Update Rate (kHz) 0.4 4 40 400 Signal-to-(Noise + Distortion) Ratio (dB) f = 0dB Output not band-limited. OUT TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY Output Frequency (kHz) 0.2 2 20 200 –50 –60 –70 –80 –90 –100 Total Harmonic Distortion (dB) f = 0dB Output not band-limited. OUT SIGNAL-TO-(NOISE + DISTORTION) RATIO vs TEMPERATURE AND AMPLITUDE Ambient Temperature (°C) Signal-to-(Noise +Distortion) Ratio (dB) 100 –50 –25 0 25 50 75 100 f = 1kHz, 0dBOUT f = 1kHz, –60dBOUT f = 1kHz, –20dBOUT DYNAMIC PERFORMANCE vs TEMPERATURE Ambient Temperature (°C) SINAD, SNR and SFDR (dB) 100 –50 –25 0 25 50 75 100 f = 1kHz, ±3Vp-pOUT THD (dB) –80 –85 –90 –95 –100 Signal-to-(Noise + Distortion) (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD)Spurious Free Dynamic Range (SFDR) TYPICAL PERFORMANCE CURVES TA = +25°C; Update Frequency, fS = 400kHz; VA+ = VD + = +5V; VA– = VD – = 5V; SWL = HIGH; CASC = LOW; Output Bandwidth Limited to 20kHz; unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

INTERMODULATION DISTORTION vs TEMPERATURE Ambient Temperature (°C) Intermodulation Distortion (dB) –85 –90 –95 –100 –105 –50 –25 0 25 50 75 100 f + f = 0dB f = 9.5kHz f = 11.5kHz OUT 1 OUT 2 OUT 1 OUT 2 POWER SUPPLY REJECTION vs SUPPLY RIPPLE FREQUENCY Supply Ripple Frequency (kHz) 0.1 1 10 100 –35 –45 –55 –65 –75 Supply Ripple Rejection (dB) V + = V +A D V – = V –A D OUTPUT VOLTAGE SETTLING TIME Settling Time (µs) 0123456 7 89 1 0 0.1 0.01 0.001Accuracy (% of 6V Full Scale Range) R = 1.5k C = 100pF L L +Full Scale to –Full Scale Transition –Full Scale to +Full Scale Transition TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C; Update Frequency, fS = 400kHz; VA+ = VD + = +5V; VA– = VD – = 5V; SWL = HIGH; CASC = LOW; Output Bandwidth Limited to 20kHz; unless otherwise noted. The DSP201 and DSP202 are ESD (electrostatic discharge) sensitive devices, and normal standard precautions should be taken. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. When not in use, devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed.

PACKAGE INFORMATION

MODEL PACKAGE NUMBER (1) DSP201JP 28-Pin Plastic DIP 215 DSP201KP 28-Pin Plastic DIP 215 DSP202JP 28-Pin Plastic DIP 215 DSP202KP 28-Pin Plastic DIP 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.

ORDERING INFORMATION

OF (NOISE + DIST.) MODEL CHANNELS RATIO, dB min 1-24 25-99 100+ DSP201JP 1 82 DSP201KP 1 88 DSP202JP 2 82 DSP202KP 2 88 ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY

PIN # NAME DESCRIPTION 1V A– –5V Analog Power. 2 No Internal Connection. 3 No Internal Connection. 4 AGND Analog Ground. 5 No Internal Connection. D + +5V Digital Power. 7V D + +5V Digital Power. 8 RESET Reset. If LOW, DAC output will be 0V after two convert commands, and will remain there as long as the Reset input is LOW. If HIGH, normal operation proceeds. Two convert commands are required after Reset goes from LOW to HIGH before the output will relate to the input word. 9 SSF Select Sync Format In. Tie HIGH for use with Motorola and TI DSP ICs. Tie LOW for use with AT&T DSP ICs. 10 SWL Select Word Length In. If HIGH, DSP201 accepts first 16 bits of data. If LOW, DSP201 accepts first 18 bits of data. 11 SYNC Data Synchronization Output. Active HIGH when SSF is HIGH, active LOW when SSF is LOW. 12 XCLK Data Transfer Clock Input. 13 SIN Serial Data In. MSB first, Binary Two’s Comple- ment format. 14 No Internal Connection. 15 CONV Convert Command In. DAC is updated on falling edge, and initiates clocking new data in. 16 DGND Digital Ground. 17 ENABLE Latch Enable In. If LOW, DAC output will be latched with new data word on falling edge of Convert Command. If HIGH, Convert Commands will be ignored. 18 DGND Digital Ground. 19 DGND Digital Ground. 20 V D – –5V Digital Power. 21 VOUT Voltage Out. 22 AGND Analog Ground. 23 VOS VOS Adjust In. 24 MSB MSB Adjust In. 25 VPOT Trim Reference Out for MSB adjustment. 26 V A+ +5V Analog Power. 27 DGND Digital Ground. 28 AGND Analog Ground. DSP201 PIN CONFIGURATION V – AGND V + V + RESET SSF SWL SYNC XCLK SIN A D D AGND DGND V + VPOT MSB VOS AGND VOUT V – DGND DGND ENABLE DGND CONV DSP201 A D

DSP202 PIN CONFIGURATION DSP202 PIN ASSIGNMENTS PIN # NAME DESCRIPTION 1V A– –5V Analog Power. 2 MSBB Channel B MSB Adjust In. 3 VOSB Channel B VOS Adjust In. 4 AGNDB Channel B Analog Ground. 5 VOUTB Channel B Voltage Out. D + +5V Digital Power. 7V D + +5V Digital Power. 8 RESET Reset. If LOW, DAC output will be 0V after two Convert Commands, and will remain there as long as the Reset input is LOW. If HIGH, normal operation proceeds. Two Convert Commands are required after Reset goes from LOW to HIGH before the output will relate to the input word. 9 SSF Select Sync Format In. Tie HIGH for use with Motorola and TI DSP ICs. Tie LOW for use with AT&T DSP ICs. 10 SWL Select Word Length In. If HIGH, DSP202 accepts first 16 bits of data. If LOW, DSP202 accepts first 18 bits of data. Must be HIGH if CASC is HIGH. 11 SYNC Data Synchronization Output. Active HIGH when SSF is HIGH, active LOW when SSF is LOW. 12 XCLK Data Transfer Clock Input. 13 SINA Channel A Serial Data In. MSB first, Binary Two’s Complement format. In Cascade Mode, connect to SINB and to DSP IC output. 14 SINB Channel B Serial Data In. MSB first, Binary Two’s Complement format. In Cascade Mode, connect to SINA and to DSP IC output. 15 CONV Convert Command In. DAC is updated on falling edge, and initiates clocking new data in. 16 CASC Select Cascade Mode In. If HIGH, DSP202 accepts a 32-bit word, and uses the first 16 bits to update channel A, and the second 16 bits to update channel B. In Cascade Mode, SINA and SINB are connected together. If CASC is LOW, data is strobed into both channels on each clock cycle. 17 ENABLE Latch Enable In. If LOW, DAC output will be latched with new data word on falling edge of Convert Command. If HIGH, Convert Commands will be ignored. 18 DGND Digital Ground. 19 DGND Digital Ground. 20 V D – –5V Digital Power. 21 VOUTA Channel A Voltage Out. 22 AGNDA Channel A Analog Ground. 23 VOSA Channel A VOS Adjust In. 24 MSBA Channel A MSB Adjust In. 25 VPOT Trim Reference Out for MSB adjustments. 26 V A+ +5V Analog Power. 27 DGND Digital Ground. 28 AGND Analog Ground. V – MSBB VOSB AGNDB VOUTB V + V + RESET SSF SWL SYNC XCLK SINA SINB A D D AGND DGND V + VPOT MSBA VOSA AGNDA VOUTA V – DGND DGND ENABLE CASC CONV DSP202 A D

The DSP201 and DSP202 are basic voltage output digital- to-analog converters with complete logic interface circuitry for ease of use with standard digital signal processing ICs. Data words are transmitted from the DSP IC on its serial port, leaving the DSP IC parallel ports free for digital communication. The DSP201 and DSP202 are pipelined internally. When the user gives a convert command at time t, two actions are initiated. First, the data stored in the internal shift registers following the previous convert command (at t – 1) is used to update the output D/A converters immediately. Second, the DSP201 or DSP202 transmits a synchronization pulse to the DSP IC and starts clocking new data into the shift register using the system Bit Clock. This data is then used to update the D/As when the t + 1 convert command is received. Both the DSP201 and DSP202 are 18-bit D/As internally. On-chip logic can be programmed to use 18-bits of data to update the D/A outputs, or can be programmed to update the D/A based on 16-bit data words. Additionally, the logic in the DSP202 can accept a 32-bit data word (the Cascade Mode), and update both D/A channels simultaneously with 16 bits each. All of these modes can be hard-wired or logic- controlled externally, so that no extra overhead on the part of the DSP IC is required. In the 16-bit modes, the DSP201 and DSP202 will append zeros to the 16-bits transferred to each of the internal D/As, which are full 18-bit converters. The 18-bit word-length mode can be used with DSP ICs programmed for either 24- bit or 32-bit output words, in which case the DSP201 or DSP202 will clock in the first 18-bits of data after the synchronization pulse, and ignore additional information on the serial line. When programmed to accept 16-bit words, the DSP201 and DSP202 can be used with DSP ICs pro- grammed to output 16-, 24-, or 32-bit words, and will ignore additional information after the first 16 bits on the serial line. The DSP201 and DSP202 are complete voltage output D/A converters, with on-chip references and output amplifiers to drive ±3V into 375Ω loads. State-of-the-art bipolar tech- nologies are used in the D/A section to maximize the output update rate, to maximize dynamic performance, and to eliminate glitch problems. Advanced plastic packaging meth- ods makes this performance attainable economically. BASIC OPERATION DATA FORMAT AND OUTPUT LEVELS The DSP201 and DSP202 accept serial data, MSB first, in standard Binary Two’s Complement format. The length of the data words can be selected as shown below, and the D/A output level generated by a specific input code is shown in Table I. As with all standard D/As, the output ranges from negative full scale (–3V) to 1 LSB below positive full scale (+3V – 1LSB). The bipolar output amplifiers are designed to drive 375Ω loads at full speed and accuracy. UPDATING THE OUTPUT With ENABLE (pin 17) LOW, the falling edge of a Convert Command arriving on CONV (pin 15) will immediately update the D/A outputs with the data stored in the internal shift registers following the previous Convert Command. The Convert Command can be asynchronous to any other signals or clocks without reducing accuracy, although sys- tem accuracy is often enhanced by synchronizing digital signals. For a full-scale change in the input code, the output will typically settle to within ±0.006% of its final level within 2.5µs. The slew rate of the output amplifier is typically 15V/ µs, for a full power bandwidth close to 800kHz. All of the specifications and typical performance curves are achieved with a full 400kHz update rate, unless otherwise specified. The DSP201 and DSP202 are guaranteed operational to a full 500kHz update rate, which exceeds the maximum Bit Clock rate for most standard DSP ICs. DATA TRANSFER Data is transmitted serially to the DSP201 or DSP202, and is clocked into the internal shift registers on the rising edge of the external Data Transfer Clock or Bit Clock (XCLK input on pin 12.) This clock can be as fast as 12MHz. The Data Transfer Clock can tolerate duty cycles from 40% to 60%. As indicated in the timing diagrams in Figure 1, either 16- or 18-bits of data will be clocked into the DSP201 or DSP202, or 32-bits will be clocked into the DSP202 in the INPUT CODE OUTPUT VOLTAGE 16-BIT MODE AND HEX 16-BIT MODE AND BINARY DSP202 CASCADE MODE 18-BIT MODE DSP202 CASCADE MODE 18-BIT MODE 0000...0000 0000 00000 0V 0V 1111...1111 FFFF 3FFFF –92 µV –23 µV Theoretical LSB Size 91.6µV 22.9 µV TABLE I. Output Voltage vs Input Code.

FIGURE 1. DSP201 and DSP202 Timing.

Cascade Mode, but internal digital overhead requires addi- tional Data Transfer Clock cycles before a new Convert Command can be sent. The minimum time between Convert Commands is 24 times the Data Transfer Clock period for either the DSP201 or the DSP202 in standard modes, and 40 times the Data Transfer clock period for the DSP202 in the Cascade Mode. There is no maximum time between Convert Commands. These additional clock cycles are used to set up the internal shift registers and logic, and are included in the specifica- tions for maximum update rate. This means a 12MHz Bit Clock can achieve the maximum specified update rate of 500kHz. DATA SYNCHRONIZATION The DSP201 and DSP202 have internal logic to generate a synchronization pulse (SYNC on pin 11) to signal the host processor to transmit data. The synchronization pulse is sent when a Convert Command is received, and the SYNC output changes on the rising edge of XCLK. Timing is shown in Figure 1. The synchronization pulse can be programmed to be either active High or active Low, depending on the logic level input on SSF (Select Sync Format on pin 9.) If SSF is LOW, SYNC will be normally HIGH, and will transmit a LOW pulse after a Convert Command is received. If SSF is HIGH, SYNC will be normally LOW, and will transmit a HIGH pulse after a Convert Command is received. The SYNC pulse will be as wide as one clock cycle on the Data Transfer Clock input on XCLK (pin 12.) SELECTING WORD LENGTH If the Select Word Length input (SWL, pin 10) is HIGH, the DSP201 or DSP202 will accept 16 bits of data after a Convert Command, with the timing shown in Figure 1. After these 16 bits, additional data on SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins 13 and 14) will be ignored. Transparent to the user, the internal shift register will append two zeroes to the 16-bit data words before updating the D/As on the next Convert Command. If SWL is LOW, the DSP201 or DSP202 will clock 18 bits of data into the internal shift register after a Convert Com- mand, with the timing shown in Figure 1. Subsequent data on SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins 13 and 14) will be ignored. In the 16-bit mode, an increment of 1 LSB will change the D/A output by approximately 91.6µV (the 6V full scale range divided by 2 16), while an LSB in the 18-bit mode will change the output approximately 22.9µV (6V/218). The DSP201 and DSP202 analog performance is tested in production using the 16-bit mode (with SWL HIGH), and the typical performance curves were generated using the 16- bit mode. Verification is made during final test that the 18- bit mode functions, but the extra resolution of these last two bits is not used when testing the analog performance. DSP202 CASCADE MODE If CASC on the DSP202 (pin 16) is HIGH, the Cascade Mode is implemented. In this mode, SINA (pin 13) and SINB (pin 14) are strapped together and connected to the serial output port of an appropriate DSP IC or other data word source. A Convert Command initiates the transfer of a 32-bit word to the DSP202. In the Cascade Mode, care must be taken to make sure SWL (pin 10) is HIGH. LATCH ENABLE If ENABLE (pin 17) is LOW, the D/A outputs will be latched with new data on the falling edge of the Convert Command. Taking ENABLE HIGH causes the DSP201 or DSP202 to ignore Convert Commands. With ENABLE HIGH when a Convert Command arrives at time t, data latched in the internal shift register after the Convert Com- mand at t – 1 is not latched to the D/As, but a new synchronization pulse is still generated and the data in the shift register is overwritten. This feature allows multiple DSP201s or DSP202s to share a single DSP IC and still be independently updated. RESET Taking RESET (pin 8) LOW will cause the D/As to output 0V after two Convert Commands are received. The two Convert Commands clear out the internal shift registers, and data input on the serial input lines will be ignored while RESET is low. This facilitates designing an analog output system that goes into a known, benign state either at power- up, after fault conditions or during a calibration cycle. ENABLE (pin 17) must be LOW when resetting the DSP201 or DSP202 outputs to 0V. After RESET is taken HIGH, two Convert Commands are required before the output will relate to the input data. Also, ENABLE must be LOW for the data to be latched to the D/As. The first Convert Command again latches the outputs at 0V, and the second Convert Command drives the output to the level determined by the data clocked in after the first Convert Command. A RESET command after power up is not required for proper operation of the DSP201 or DSP202. LAYOUT CONSIDERATIONS Because of the high resolution, linearity and speed of the DSP201 and DSP202, system design problems such as ground path resistance, contact resistance and power supply quality become very important. GROUNDS To achieve the maximum performance from the DSP201 or DSP202, care should be taken to minimize the effect of current flows in the system grounds that may corrupt the output voltages generated by the D/As. Pin 22 on the DSP201 and pins 4 and 22 on the DSP202 are the most

critical internal grounds, and care should be taken especially at these points to make them as close as possible to the same potential as the system analog ground. The design of the DSP201 and DSP202 insures that these pins will have minimal current flowing through them. Internally, power currents are directed to the digital grounds (pins 18, 19, and 27) for internal digital currents, which are primarily switching currents, and to the analog grounds (pin 28, plus pin 4 on the DSP201) for analog currents, which are primarily from the internal current switches and the output amplifier. Pin 16 on the DSP201 is used internally as a logic level, and injects essentially no current into the ground. Wherever possible, it is strongly recommended that separate analog and digital ground planes be used. With an LSB level of 92µV in 16-bit modes, and one quarter of that in 18-bit modes, the currents switched in a typical DSP system (processor, memory, etc.) can easily corrupt the output accuracy of the D/A’s unless great care is taken to analyze and design for current flows. POWER SUPPLY DECOUPLING All of the supplies should be decoupled to the appropriate grounds using tantalum capacitors in parallel with ceramic capacitors, as shown in Figures 2 and 3. For optimum performance of any high resolution D/A, all of the supplies need to be as clean as possible. If separate digital and analog supplies are available in a system, care should be taken to insure that the difference between the analog and the digital supplies is not more than 0.5V for more than a few hundred milliseconds, as may occur at power-on. Separate –5V analog and digital supplies are not needed. These pins are kept separate internally to minimize cou- pling. Drive pin 20 from the –5V analog supply, and make sure that the decoupling shown in Figure 2 or 3 are placed as close as possible to the D/As. CALIBRATION AND ADJUSTMENT OPTIONAL EXTERNAL OFFSET AND MSB TRIMS All of the specifications for the DSP201 and DSP202, plus the typical performance curves, are based on the perfor- mance of these D/As without external trims. In most appli- cations, external trims are not required. If external trims are not used, pins 23, 24, and 25 on the DSP201 should be left open, as should pins 2, 3, 23, 24 and 25 on the DSP202. These pins should not be decoupled with capacitors or tied to any specific potential, or the noise on the D/A outputs may increase. ADJUSTING OFFSET Where required by specific applications, offsets can be trimmed using the circuits in Figure 2 (DSP201) or Figure 3 (DSP202.) As with all standard D/As, offset on the DSP201 and DSP202 means the difference of the output from the ideal negative full scale value. The DSP201 and DSP202 use a current switching D/A architecture, and the current from this is internally amplified to produce a ±3V output range. Negative full scale output thus results from having all of the internal current switches turned off. Offset on the DSP201 and DSP202 should not be confused with the delta from 0V with an input code of 0000...0000 (0000 hex for 16-bit Modes, 00000 hex for 18-bit Modes). This is often described as bipolar zero error, and includes the effects of both offset and gain error. To trim the offsets, first latch the D/As with 1000...0000 (8000 hex or 20000 hex). Then adjust the offset adjustment pots to produce an output of –3.000000V. ADJUSTING THE MSB WEIGHT The MSB adjustment circuitry shown in Figure 2 for the DSP201 and in Figure 4 for the DSP202 basically change the weight of the MSB by adding to or subtracting from the current controlled by the internal MSB switch. Depending on the application, the MSB adjustments can be made in one of three different ways to optimize the system performance using the DSP201 or DSP202. For dynamic performance, the MSB can be adjusted to minimize distor- tion of either a full-scale or low level sine-wave output. For applications stressing differential linearity, the 0000...0000 (0000 hex or 00000 hex) to 1000...0000 (FFFF hex or 3FFFF hex) transition can be trimmed to change the output of the D/As precisely 1 LSB (92µV in the 16-bit Mode or 23µV in the 18-bit Mode.) To adjust for minimum distortion of full-scale sinewaves, strobe the inputs to the DSP201 or DSP202 with codes representing ideal full scale sine waves, then trim the MSB adjustment circuit to minimize distortion, as measured by either a distortion analyzer or by digitizing the output with an appropriate A/D and running FFT analyses. In many audio applications, it is more appropriate to adjust for minimum distortion with low level sinewave outputs. This minimizes zero-crossover error, which can be a con- cern in high-end audio systems. To do this, strobe the inputs to the DSP201 or DSP202 with codes representing ideal low-level sine waves (–60dB from full scale works well), and then trim the MSB adjustment circuit to minimize distortion, again using a distortion analyzer or FFT analyses to check the results of the trims. The MSB adjustment circuits can also be used to trim the D/A outputs directly for the transition from 0000...0000 (0000 hex or 00000 hex) to 1111...1111 (FFFF hex or 3FFFF hex), eliminating differential linearity error at the major carry. Ideally, this transition of the digital input code should cause the D/A outputs to change 92µV in the 16-bit Mode or 23µV in the 18-bit Mode. A simple way to make this adjustment is to continually load alternately the codes 1111...1111 (FFFF hex or 3FFFF hex) and 0000...0000 (0000 hex or 00000 hex) into the DSP201 or DSP202. An amplifier with sufficient gain can then drive an oscilloscope input, and the transition output step can be adjusted.

Gain error on the DSP201 or DSP202 cannot be directly adjusted. If required in a specific application, gain can be trimmed out at the system level by adjusting the gain used in an output amplifier stage, such as would be used in any active output filter. In this case, the bipolar zero error should be adjusted first as discussed above. Then, the gain on the output amplifier should be adjusted to minimize the devia- tion from ideal for –Full Scale (1000...000; 8000 hex or 20000 hex) and +Full Scale (0111...1111; 7FFF hex or 1FFFF hex.) An alternative for calibrating on a bench is to tie SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins 13 and 14) HIGH, and provide a Bit Clock and periodic Convert Commands. This loads 1111...1111 (FFFF HEX or 3FFFFHEX ), driving the output to 1LSB below 0V. Then periodically bring RESET (pin 8) LOW for at least two Convert Commands, which is the equivalent of loading all 0s, so the output is 0V. Now the output can be adjusted for an ideal transition step. ADJUSTING BIPOLAR ZERO ERROR If it is important in a specific application to adjust bipolar zero error, the user should first adjust the MSB trim circuits, and then use the offset adjust circuits to adjust the outputs to 0V with input codes of all 0s (0000...0000; 0000 hex or 00000 hex.) In this case, it is not possible to also trim offset at –Full Scale, as described above.FIGURE 2. DSP201 Power Supply Connections and Optional Adjust Circuits. DSP201 –5V 100kΩ 100kΩ 2.2µF AGND V + VPOT MSB VOS AGND V – DGND DGND 2.2µF V – AGNDB V + V + –5V +5V 2.2µF A A D D D 2.2µF +5V –5V +5V 100kΩ 3.3kΩ Offset Adjust –5V 0.01µF+ 0.01µF 0.01µF 0.01µF MSB Adjust

FIGURE 6. Analog Input and Analog Output System. *See Burr-Brown DSP101/102 product data sheet for full description of this ADC.

2 VIN

FIGURE 7. DSP202 with Dual DSP ICs.

DSP201 or DSP202 after receiving a Convert Command. synchronization mode is shown in Figure 1. using the DSP201 plus the Burr-Brown DSP101 A/D. the two channels of the DSP202. Figure 8. This circuit can maximize the update rate for the cascade mode as shown in Figure 9. TMS320C30, by making use of the second serial port. analog output of the DSP201. DSP56001s, as indicated in Figure 7. LOW), and will ignore the trailing bits on the serial line. vert Command is received by the DSP201 or DSP202. Timing is shown in Figure 1.

24 Bit Clock pulses between convert commands, the maxi-

NOTE: (1) Serial output is 16-bit MSB first. FIGURE 8. Using DSP202 with TMS320C30’s Dual SIO.